Merge branch 'ks8851-fixes'
Lukas Wunner says: ==================== ks8851 fixes & cleanups Four fixes and two cleanups for the Microchip (formerly Micrel) KSZ8851 SPI Ethernet driver. Some of the fixes might even pass as stable material, but I haven't marked them as such for cautiousness: Doesn't hurt letting them bake in linux-next for a few weeks to raise the confidence, even though we've tested them extensively on our Revolution Pi open source PLCs. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
commit
cb8075d934
drivers/net/ethernet/micrel
@ -142,6 +142,12 @@ struct ks8851_net {
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static int msg_enable;
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/* SPI frame opcodes */
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#define KS_SPIOP_RD (0x00)
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#define KS_SPIOP_WR (0x40)
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#define KS_SPIOP_RXFIFO (0x80)
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#define KS_SPIOP_TXFIFO (0xC0)
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/* shift for byte-enable data */
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#define BYTE_EN(_x) ((_x) << 2)
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@ -535,9 +541,8 @@ static void ks8851_rx_pkts(struct ks8851_net *ks)
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/* set dma read address */
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ks8851_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI | 0x00);
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/* start the packet dma process, and set auto-dequeue rx */
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ks8851_wrreg16(ks, KS_RXQCR,
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ks->rc_rxqcr | RXQCR_SDA | RXQCR_ADRFE);
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/* start DMA access */
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ks8851_wrreg16(ks, KS_RXQCR, ks->rc_rxqcr | RXQCR_SDA);
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if (rxlen > 4) {
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unsigned int rxalign;
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@ -568,7 +573,8 @@ static void ks8851_rx_pkts(struct ks8851_net *ks)
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}
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}
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ks8851_wrreg16(ks, KS_RXQCR, ks->rc_rxqcr);
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/* end DMA access and dequeue packet */
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ks8851_wrreg16(ks, KS_RXQCR, ks->rc_rxqcr | RXQCR_RRXEF);
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}
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}
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@ -785,6 +791,15 @@ static void ks8851_tx_work(struct work_struct *work)
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static int ks8851_net_open(struct net_device *dev)
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{
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struct ks8851_net *ks = netdev_priv(dev);
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int ret;
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ret = request_threaded_irq(dev->irq, NULL, ks8851_irq,
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IRQF_TRIGGER_LOW | IRQF_ONESHOT,
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dev->name, ks);
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if (ret < 0) {
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netdev_err(dev, "failed to get irq\n");
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return ret;
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}
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/* lock the card, even if we may not actually be doing anything
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* else at the moment */
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@ -849,6 +864,7 @@ static int ks8851_net_open(struct net_device *dev)
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netif_dbg(ks, ifup, ks->netdev, "network device up\n");
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mutex_unlock(&ks->lock);
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mii_check_link(&ks->mii);
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return 0;
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}
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@ -899,6 +915,8 @@ static int ks8851_net_stop(struct net_device *dev)
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dev_kfree_skb(txb);
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}
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free_irq(dev->irq, ks);
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return 0;
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}
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@ -1508,6 +1526,7 @@ static int ks8851_probe(struct spi_device *spi)
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spi_set_drvdata(spi, ks);
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netif_carrier_off(ks->netdev);
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ndev->if_port = IF_PORT_100BASET;
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ndev->netdev_ops = &ks8851_netdev_ops;
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ndev->irq = spi->irq;
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@ -1529,14 +1548,6 @@ static int ks8851_probe(struct spi_device *spi)
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ks8851_read_selftest(ks);
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ks8851_init_mac(ks);
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ret = request_threaded_irq(spi->irq, NULL, ks8851_irq,
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IRQF_TRIGGER_LOW | IRQF_ONESHOT,
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ndev->name, ks);
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if (ret < 0) {
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dev_err(&spi->dev, "failed to get irq\n");
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goto err_irq;
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}
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ret = register_netdev(ndev);
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if (ret) {
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dev_err(&spi->dev, "failed to register network device\n");
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@ -1549,14 +1560,10 @@ static int ks8851_probe(struct spi_device *spi)
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return 0;
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err_netdev:
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free_irq(ndev->irq, ks);
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err_irq:
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err_id:
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if (gpio_is_valid(gpio))
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gpio_set_value(gpio, 0);
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err_id:
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regulator_disable(ks->vdd_reg);
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err_reg:
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regulator_disable(ks->vdd_io);
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@ -1574,7 +1581,6 @@ static int ks8851_remove(struct spi_device *spi)
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dev_info(&spi->dev, "remove\n");
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unregister_netdev(priv->netdev);
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free_irq(spi->irq, priv);
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if (gpio_is_valid(priv->gpio))
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gpio_set_value(priv->gpio, 0);
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regulator_disable(priv->vdd_reg);
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@ -11,9 +11,15 @@
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*/
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#define KS_CCR 0x08
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#define CCR_LE (1 << 10) /* KSZ8851-16MLL */
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#define CCR_EEPROM (1 << 9)
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#define CCR_SPI (1 << 8)
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#define CCR_32PIN (1 << 0)
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#define CCR_SPI (1 << 8) /* KSZ8851SNL */
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#define CCR_8BIT (1 << 7) /* KSZ8851-16MLL */
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#define CCR_16BIT (1 << 6) /* KSZ8851-16MLL */
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#define CCR_32BIT (1 << 5) /* KSZ8851-16MLL */
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#define CCR_SHARED (1 << 4) /* KSZ8851-16MLL */
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#define CCR_48PIN (1 << 1) /* KSZ8851-16MLL */
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#define CCR_32PIN (1 << 0) /* KSZ8851SNL */
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/* MAC address registers */
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#define KS_MAR(_m) (0x15 - (_m))
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@ -112,13 +118,13 @@
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#define RXCR1_RXE (1 << 0)
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#define KS_RXCR2 0x76
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#define RXCR2_SRDBL_MASK (0x7 << 5)
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#define RXCR2_SRDBL_SHIFT (5)
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#define RXCR2_SRDBL_4B (0x0 << 5)
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#define RXCR2_SRDBL_8B (0x1 << 5)
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#define RXCR2_SRDBL_16B (0x2 << 5)
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#define RXCR2_SRDBL_32B (0x3 << 5)
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#define RXCR2_SRDBL_FRAME (0x4 << 5)
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#define RXCR2_SRDBL_MASK (0x7 << 5) /* KSZ8851SNL */
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#define RXCR2_SRDBL_SHIFT (5) /* KSZ8851SNL */
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#define RXCR2_SRDBL_4B (0x0 << 5) /* KSZ8851SNL */
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#define RXCR2_SRDBL_8B (0x1 << 5) /* KSZ8851SNL */
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#define RXCR2_SRDBL_16B (0x2 << 5) /* KSZ8851SNL */
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#define RXCR2_SRDBL_32B (0x3 << 5) /* KSZ8851SNL */
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#define RXCR2_SRDBL_FRAME (0x4 << 5) /* KSZ8851SNL */
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#define RXCR2_IUFFP (1 << 4)
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#define RXCR2_RXIUFCEZ (1 << 3)
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#define RXCR2_UDPLFE (1 << 2)
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@ -143,8 +149,10 @@
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#define RXFSHR_RXCE (1 << 0)
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#define KS_RXFHBCR 0x7E
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#define RXFHBCR_CNT_MASK (0xfff << 0)
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#define KS_TXQCR 0x80
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#define TXQCR_AETFE (1 << 2)
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#define TXQCR_AETFE (1 << 2) /* KSZ8851SNL */
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#define TXQCR_TXQMAM (1 << 1)
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#define TXQCR_METFE (1 << 0)
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@ -167,6 +175,10 @@
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#define KS_RXFDPR 0x86
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#define RXFDPR_RXFPAI (1 << 14)
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#define RXFDPR_WST (1 << 12) /* KSZ8851-16MLL */
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#define RXFDPR_EMS (1 << 11) /* KSZ8851-16MLL */
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#define RXFDPR_RXFP_MASK (0x7ff << 0)
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#define RXFDPR_RXFP_SHIFT (0)
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#define KS_RXDTTR 0x8C
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#define KS_RXDBCTR 0x8E
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@ -184,7 +196,7 @@
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#define IRQ_RXMPDI (1 << 4)
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#define IRQ_LDI (1 << 3)
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#define IRQ_EDI (1 << 2)
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#define IRQ_SPIBEI (1 << 1)
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#define IRQ_SPIBEI (1 << 1) /* KSZ8851SNL */
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#define IRQ_DEDI (1 << 0)
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#define KS_RXFCTR 0x9C
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@ -257,42 +269,37 @@
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#define KS_P1ANLPR 0xEE
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#define KS_P1SCLMD 0xF4
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#define P1SCLMD_LEDOFF (1 << 15)
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#define P1SCLMD_TXIDS (1 << 14)
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#define P1SCLMD_RESTARTAN (1 << 13)
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#define P1SCLMD_DISAUTOMDIX (1 << 10)
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#define P1SCLMD_FORCEMDIX (1 << 9)
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#define P1SCLMD_AUTONEGEN (1 << 7)
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#define P1SCLMD_FORCE100 (1 << 6)
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#define P1SCLMD_FORCEFDX (1 << 5)
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#define P1SCLMD_ADV_FLOW (1 << 4)
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#define P1SCLMD_ADV_100BT_FDX (1 << 3)
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#define P1SCLMD_ADV_100BT_HDX (1 << 2)
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#define P1SCLMD_ADV_10BT_FDX (1 << 1)
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#define P1SCLMD_ADV_10BT_HDX (1 << 0)
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#define KS_P1CR 0xF6
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#define P1CR_HP_MDIX (1 << 15)
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#define P1CR_REV_POL (1 << 13)
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#define P1CR_OP_100M (1 << 10)
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#define P1CR_OP_FDX (1 << 9)
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#define P1CR_OP_MDI (1 << 7)
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#define P1CR_AN_DONE (1 << 6)
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#define P1CR_LINK_GOOD (1 << 5)
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#define P1CR_PNTR_FLOW (1 << 4)
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#define P1CR_PNTR_100BT_FDX (1 << 3)
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#define P1CR_PNTR_100BT_HDX (1 << 2)
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#define P1CR_PNTR_10BT_FDX (1 << 1)
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#define P1CR_PNTR_10BT_HDX (1 << 0)
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#define P1CR_LEDOFF (1 << 15)
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#define P1CR_TXIDS (1 << 14)
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#define P1CR_RESTARTAN (1 << 13)
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#define P1CR_DISAUTOMDIX (1 << 10)
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#define P1CR_FORCEMDIX (1 << 9)
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#define P1CR_AUTONEGEN (1 << 7)
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#define P1CR_FORCE100 (1 << 6)
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#define P1CR_FORCEFDX (1 << 5)
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#define P1CR_ADV_FLOW (1 << 4)
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#define P1CR_ADV_100BT_FDX (1 << 3)
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#define P1CR_ADV_100BT_HDX (1 << 2)
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#define P1CR_ADV_10BT_FDX (1 << 1)
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#define P1CR_ADV_10BT_HDX (1 << 0)
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#define KS_P1SR 0xF8
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#define P1SR_HP_MDIX (1 << 15)
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#define P1SR_REV_POL (1 << 13)
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#define P1SR_OP_100M (1 << 10)
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#define P1SR_OP_FDX (1 << 9)
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#define P1SR_OP_MDI (1 << 7)
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#define P1SR_AN_DONE (1 << 6)
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#define P1SR_LINK_GOOD (1 << 5)
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#define P1SR_PNTR_FLOW (1 << 4)
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#define P1SR_PNTR_100BT_FDX (1 << 3)
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#define P1SR_PNTR_100BT_HDX (1 << 2)
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#define P1SR_PNTR_10BT_FDX (1 << 1)
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#define P1SR_PNTR_10BT_HDX (1 << 0)
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/* TX Frame control */
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#define TXFR_TXIC (1 << 15)
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#define TXFR_TXFID_MASK (0x3f << 0)
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#define TXFR_TXFID_SHIFT (0)
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/* SPI frame opcodes */
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#define KS_SPIOP_RD (0x00)
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#define KS_SPIOP_WR (0x40)
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#define KS_SPIOP_RXFIFO (0x80)
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#define KS_SPIOP_TXFIFO (0xC0)
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@ -40,6 +40,8 @@
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#include <linux/of_device.h>
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#include <linux/of_net.h>
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#include "ks8851.h"
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#define DRV_NAME "ks8851_mll"
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static u8 KS_DEFAULT_MAC_ADDRESS[] = { 0x00, 0x10, 0xA1, 0x86, 0x95, 0x11 };
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@ -48,319 +50,10 @@ static u8 KS_DEFAULT_MAC_ADDRESS[] = { 0x00, 0x10, 0xA1, 0x86, 0x95, 0x11 };
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#define TX_BUF_SIZE 2000
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#define RX_BUF_SIZE 2000
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#define KS_CCR 0x08
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#define CCR_EEPROM (1 << 9)
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#define CCR_SPI (1 << 8)
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#define CCR_8BIT (1 << 7)
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#define CCR_16BIT (1 << 6)
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#define CCR_32BIT (1 << 5)
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#define CCR_SHARED (1 << 4)
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#define CCR_32PIN (1 << 0)
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/* MAC address registers */
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#define KS_MARL 0x10
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#define KS_MARM 0x12
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#define KS_MARH 0x14
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#define KS_OBCR 0x20
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#define OBCR_ODS_16MA (1 << 6)
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#define KS_EEPCR 0x22
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#define EEPCR_EESA (1 << 4)
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#define EEPCR_EESB (1 << 3)
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#define EEPCR_EEDO (1 << 2)
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#define EEPCR_EESCK (1 << 1)
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#define EEPCR_EECS (1 << 0)
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#define KS_MBIR 0x24
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#define MBIR_TXMBF (1 << 12)
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#define MBIR_TXMBFA (1 << 11)
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#define MBIR_RXMBF (1 << 4)
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#define MBIR_RXMBFA (1 << 3)
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#define KS_GRR 0x26
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#define GRR_QMU (1 << 1)
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#define GRR_GSR (1 << 0)
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#define KS_WFCR 0x2A
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#define WFCR_MPRXE (1 << 7)
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#define WFCR_WF3E (1 << 3)
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#define WFCR_WF2E (1 << 2)
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#define WFCR_WF1E (1 << 1)
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#define WFCR_WF0E (1 << 0)
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#define KS_WF0CRC0 0x30
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#define KS_WF0CRC1 0x32
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#define KS_WF0BM0 0x34
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#define KS_WF0BM1 0x36
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#define KS_WF0BM2 0x38
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#define KS_WF0BM3 0x3A
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#define KS_WF1CRC0 0x40
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#define KS_WF1CRC1 0x42
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#define KS_WF1BM0 0x44
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#define KS_WF1BM1 0x46
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#define KS_WF1BM2 0x48
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#define KS_WF1BM3 0x4A
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#define KS_WF2CRC0 0x50
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#define KS_WF2CRC1 0x52
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#define KS_WF2BM0 0x54
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#define KS_WF2BM1 0x56
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#define KS_WF2BM2 0x58
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#define KS_WF2BM3 0x5A
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#define KS_WF3CRC0 0x60
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#define KS_WF3CRC1 0x62
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#define KS_WF3BM0 0x64
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#define KS_WF3BM1 0x66
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#define KS_WF3BM2 0x68
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#define KS_WF3BM3 0x6A
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#define KS_TXCR 0x70
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#define TXCR_TCGICMP (1 << 8)
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#define TXCR_TCGUDP (1 << 7)
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#define TXCR_TCGTCP (1 << 6)
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#define TXCR_TCGIP (1 << 5)
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#define TXCR_FTXQ (1 << 4)
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#define TXCR_TXFCE (1 << 3)
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#define TXCR_TXPE (1 << 2)
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#define TXCR_TXCRC (1 << 1)
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#define TXCR_TXE (1 << 0)
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#define KS_TXSR 0x72
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#define TXSR_TXLC (1 << 13)
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#define TXSR_TXMC (1 << 12)
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#define TXSR_TXFID_MASK (0x3f << 0)
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#define TXSR_TXFID_SHIFT (0)
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#define TXSR_TXFID_GET(_v) (((_v) >> 0) & 0x3f)
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#define KS_RXCR1 0x74
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#define RXCR1_FRXQ (1 << 15)
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#define RXCR1_RXUDPFCC (1 << 14)
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#define RXCR1_RXTCPFCC (1 << 13)
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#define RXCR1_RXIPFCC (1 << 12)
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#define RXCR1_RXPAFMA (1 << 11)
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#define RXCR1_RXFCE (1 << 10)
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#define RXCR1_RXEFE (1 << 9)
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#define RXCR1_RXMAFMA (1 << 8)
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#define RXCR1_RXBE (1 << 7)
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#define RXCR1_RXME (1 << 6)
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#define RXCR1_RXUE (1 << 5)
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#define RXCR1_RXAE (1 << 4)
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#define RXCR1_RXINVF (1 << 1)
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#define RXCR1_RXE (1 << 0)
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#define RXCR1_FILTER_MASK (RXCR1_RXINVF | RXCR1_RXAE | \
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RXCR1_RXMAFMA | RXCR1_RXPAFMA)
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#define KS_RXCR2 0x76
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#define RXCR2_SRDBL_MASK (0x7 << 5)
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#define RXCR2_SRDBL_SHIFT (5)
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#define RXCR2_SRDBL_4B (0x0 << 5)
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#define RXCR2_SRDBL_8B (0x1 << 5)
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#define RXCR2_SRDBL_16B (0x2 << 5)
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#define RXCR2_SRDBL_32B (0x3 << 5)
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/* #define RXCR2_SRDBL_FRAME (0x4 << 5) */
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#define RXCR2_IUFFP (1 << 4)
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#define RXCR2_RXIUFCEZ (1 << 3)
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#define RXCR2_UDPLFE (1 << 2)
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#define RXCR2_RXICMPFCC (1 << 1)
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#define RXCR2_RXSAF (1 << 0)
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|
||||
#define KS_TXMIR 0x78
|
||||
|
||||
#define KS_RXFHSR 0x7C
|
||||
#define RXFSHR_RXFV (1 << 15)
|
||||
#define RXFSHR_RXICMPFCS (1 << 13)
|
||||
#define RXFSHR_RXIPFCS (1 << 12)
|
||||
#define RXFSHR_RXTCPFCS (1 << 11)
|
||||
#define RXFSHR_RXUDPFCS (1 << 10)
|
||||
#define RXFSHR_RXBF (1 << 7)
|
||||
#define RXFSHR_RXMF (1 << 6)
|
||||
#define RXFSHR_RXUF (1 << 5)
|
||||
#define RXFSHR_RXMR (1 << 4)
|
||||
#define RXFSHR_RXFT (1 << 3)
|
||||
#define RXFSHR_RXFTL (1 << 2)
|
||||
#define RXFSHR_RXRF (1 << 1)
|
||||
#define RXFSHR_RXCE (1 << 0)
|
||||
#define RXFSHR_ERR (RXFSHR_RXCE | RXFSHR_RXRF |\
|
||||
RXFSHR_RXFTL | RXFSHR_RXMR |\
|
||||
RXFSHR_RXICMPFCS | RXFSHR_RXIPFCS |\
|
||||
RXFSHR_RXTCPFCS)
|
||||
#define KS_RXFHBCR 0x7E
|
||||
#define RXFHBCR_CNT_MASK 0x0FFF
|
||||
|
||||
#define KS_TXQCR 0x80
|
||||
#define TXQCR_AETFE (1 << 2)
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||||
#define TXQCR_TXQMAM (1 << 1)
|
||||
#define TXQCR_METFE (1 << 0)
|
||||
|
||||
#define KS_RXQCR 0x82
|
||||
#define RXQCR_RXDTTS (1 << 12)
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||||
#define RXQCR_RXDBCTS (1 << 11)
|
||||
#define RXQCR_RXFCTS (1 << 10)
|
||||
#define RXQCR_RXIPHTOE (1 << 9)
|
||||
#define RXQCR_RXDTTE (1 << 7)
|
||||
#define RXQCR_RXDBCTE (1 << 6)
|
||||
#define RXQCR_RXFCTE (1 << 5)
|
||||
#define RXQCR_ADRFE (1 << 4)
|
||||
#define RXQCR_SDA (1 << 3)
|
||||
#define RXQCR_RRXEF (1 << 0)
|
||||
#define RXQCR_CMD_CNTL (RXQCR_RXFCTE|RXQCR_ADRFE)
|
||||
|
||||
#define KS_TXFDPR 0x84
|
||||
#define TXFDPR_TXFPAI (1 << 14)
|
||||
#define TXFDPR_TXFP_MASK (0x7ff << 0)
|
||||
#define TXFDPR_TXFP_SHIFT (0)
|
||||
|
||||
#define KS_RXFDPR 0x86
|
||||
#define RXFDPR_RXFPAI (1 << 14)
|
||||
|
||||
#define KS_RXDTTR 0x8C
|
||||
#define KS_RXDBCTR 0x8E
|
||||
|
||||
#define KS_IER 0x90
|
||||
#define KS_ISR 0x92
|
||||
#define IRQ_LCI (1 << 15)
|
||||
#define IRQ_TXI (1 << 14)
|
||||
#define IRQ_RXI (1 << 13)
|
||||
#define IRQ_RXOI (1 << 11)
|
||||
#define IRQ_TXPSI (1 << 9)
|
||||
#define IRQ_RXPSI (1 << 8)
|
||||
#define IRQ_TXSAI (1 << 6)
|
||||
#define IRQ_RXWFDI (1 << 5)
|
||||
#define IRQ_RXMPDI (1 << 4)
|
||||
#define IRQ_LDI (1 << 3)
|
||||
#define IRQ_EDI (1 << 2)
|
||||
#define IRQ_SPIBEI (1 << 1)
|
||||
#define IRQ_DEDI (1 << 0)
|
||||
|
||||
#define KS_RXFCTR 0x9C
|
||||
#define RXFCTR_THRESHOLD_MASK 0x00FF
|
||||
|
||||
#define KS_RXFC 0x9D
|
||||
#define RXFCTR_RXFC_MASK (0xff << 8)
|
||||
#define RXFCTR_RXFC_SHIFT (8)
|
||||
#define RXFCTR_RXFC_GET(_v) (((_v) >> 8) & 0xff)
|
||||
#define RXFCTR_RXFCT_MASK (0xff << 0)
|
||||
#define RXFCTR_RXFCT_SHIFT (0)
|
||||
|
||||
#define KS_TXNTFSR 0x9E
|
||||
|
||||
#define KS_MAHTR0 0xA0
|
||||
#define KS_MAHTR1 0xA2
|
||||
#define KS_MAHTR2 0xA4
|
||||
#define KS_MAHTR3 0xA6
|
||||
|
||||
#define KS_FCLWR 0xB0
|
||||
#define KS_FCHWR 0xB2
|
||||
#define KS_FCOWR 0xB4
|
||||
|
||||
#define KS_CIDER 0xC0
|
||||
#define CIDER_ID 0x8870
|
||||
#define CIDER_REV_MASK (0x7 << 1)
|
||||
#define CIDER_REV_SHIFT (1)
|
||||
#define CIDER_REV_GET(_v) (((_v) >> 1) & 0x7)
|
||||
|
||||
#define KS_CGCR 0xC6
|
||||
#define KS_IACR 0xC8
|
||||
#define IACR_RDEN (1 << 12)
|
||||
#define IACR_TSEL_MASK (0x3 << 10)
|
||||
#define IACR_TSEL_SHIFT (10)
|
||||
#define IACR_TSEL_MIB (0x3 << 10)
|
||||
#define IACR_ADDR_MASK (0x1f << 0)
|
||||
#define IACR_ADDR_SHIFT (0)
|
||||
|
||||
#define KS_IADLR 0xD0
|
||||
#define KS_IAHDR 0xD2
|
||||
|
||||
#define KS_PMECR 0xD4
|
||||
#define PMECR_PME_DELAY (1 << 14)
|
||||
#define PMECR_PME_POL (1 << 12)
|
||||
#define PMECR_WOL_WAKEUP (1 << 11)
|
||||
#define PMECR_WOL_MAGICPKT (1 << 10)
|
||||
#define PMECR_WOL_LINKUP (1 << 9)
|
||||
#define PMECR_WOL_ENERGY (1 << 8)
|
||||
#define PMECR_AUTO_WAKE_EN (1 << 7)
|
||||
#define PMECR_WAKEUP_NORMAL (1 << 6)
|
||||
#define PMECR_WKEVT_MASK (0xf << 2)
|
||||
#define PMECR_WKEVT_SHIFT (2)
|
||||
#define PMECR_WKEVT_GET(_v) (((_v) >> 2) & 0xf)
|
||||
#define PMECR_WKEVT_ENERGY (0x1 << 2)
|
||||
#define PMECR_WKEVT_LINK (0x2 << 2)
|
||||
#define PMECR_WKEVT_MAGICPKT (0x4 << 2)
|
||||
#define PMECR_WKEVT_FRAME (0x8 << 2)
|
||||
#define PMECR_PM_MASK (0x3 << 0)
|
||||
#define PMECR_PM_SHIFT (0)
|
||||
#define PMECR_PM_NORMAL (0x0 << 0)
|
||||
#define PMECR_PM_ENERGY (0x1 << 0)
|
||||
#define PMECR_PM_SOFTDOWN (0x2 << 0)
|
||||
#define PMECR_PM_POWERSAVE (0x3 << 0)
|
||||
|
||||
/* Standard MII PHY data */
|
||||
#define KS_P1MBCR 0xE4
|
||||
#define P1MBCR_FORCE_FDX (1 << 8)
|
||||
|
||||
#define KS_P1MBSR 0xE6
|
||||
#define P1MBSR_AN_COMPLETE (1 << 5)
|
||||
#define P1MBSR_AN_CAPABLE (1 << 3)
|
||||
#define P1MBSR_LINK_UP (1 << 2)
|
||||
|
||||
#define KS_PHY1ILR 0xE8
|
||||
#define KS_PHY1IHR 0xEA
|
||||
#define KS_P1ANAR 0xEC
|
||||
#define KS_P1ANLPR 0xEE
|
||||
|
||||
#define KS_P1SCLMD 0xF4
|
||||
#define P1SCLMD_LEDOFF (1 << 15)
|
||||
#define P1SCLMD_TXIDS (1 << 14)
|
||||
#define P1SCLMD_RESTARTAN (1 << 13)
|
||||
#define P1SCLMD_DISAUTOMDIX (1 << 10)
|
||||
#define P1SCLMD_FORCEMDIX (1 << 9)
|
||||
#define P1SCLMD_AUTONEGEN (1 << 7)
|
||||
#define P1SCLMD_FORCE100 (1 << 6)
|
||||
#define P1SCLMD_FORCEFDX (1 << 5)
|
||||
#define P1SCLMD_ADV_FLOW (1 << 4)
|
||||
#define P1SCLMD_ADV_100BT_FDX (1 << 3)
|
||||
#define P1SCLMD_ADV_100BT_HDX (1 << 2)
|
||||
#define P1SCLMD_ADV_10BT_FDX (1 << 1)
|
||||
#define P1SCLMD_ADV_10BT_HDX (1 << 0)
|
||||
|
||||
#define KS_P1CR 0xF6
|
||||
#define P1CR_HP_MDIX (1 << 15)
|
||||
#define P1CR_REV_POL (1 << 13)
|
||||
#define P1CR_OP_100M (1 << 10)
|
||||
#define P1CR_OP_FDX (1 << 9)
|
||||
#define P1CR_OP_MDI (1 << 7)
|
||||
#define P1CR_AN_DONE (1 << 6)
|
||||
#define P1CR_LINK_GOOD (1 << 5)
|
||||
#define P1CR_PNTR_FLOW (1 << 4)
|
||||
#define P1CR_PNTR_100BT_FDX (1 << 3)
|
||||
#define P1CR_PNTR_100BT_HDX (1 << 2)
|
||||
#define P1CR_PNTR_10BT_FDX (1 << 1)
|
||||
#define P1CR_PNTR_10BT_HDX (1 << 0)
|
||||
|
||||
/* TX Frame control */
|
||||
|
||||
#define TXFR_TXIC (1 << 15)
|
||||
#define TXFR_TXFID_MASK (0x3f << 0)
|
||||
#define TXFR_TXFID_SHIFT (0)
|
||||
|
||||
#define KS_P1SR 0xF8
|
||||
#define P1SR_HP_MDIX (1 << 15)
|
||||
#define P1SR_REV_POL (1 << 13)
|
||||
#define P1SR_OP_100M (1 << 10)
|
||||
#define P1SR_OP_FDX (1 << 9)
|
||||
#define P1SR_OP_MDI (1 << 7)
|
||||
#define P1SR_AN_DONE (1 << 6)
|
||||
#define P1SR_LINK_GOOD (1 << 5)
|
||||
#define P1SR_PNTR_FLOW (1 << 4)
|
||||
#define P1SR_PNTR_100BT_FDX (1 << 3)
|
||||
#define P1SR_PNTR_100BT_HDX (1 << 2)
|
||||
#define P1SR_PNTR_10BT_FDX (1 << 1)
|
||||
#define P1SR_PNTR_10BT_HDX (1 << 0)
|
||||
|
||||
#define ENUM_BUS_NONE 0
|
||||
#define ENUM_BUS_8BIT 1
|
||||
#define ENUM_BUS_16BIT 2
|
||||
@ -1475,7 +1168,7 @@ static void ks_setup(struct ks_net *ks)
|
||||
ks_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI);
|
||||
|
||||
/* Setup Receive Frame Threshold - 1 frame (RXFCTFC) */
|
||||
ks_wrreg16(ks, KS_RXFCTR, 1 & RXFCTR_THRESHOLD_MASK);
|
||||
ks_wrreg16(ks, KS_RXFCTR, 1 & RXFCTR_RXFCT_MASK);
|
||||
|
||||
/* Setup RxQ Command Control (RXQCR) */
|
||||
ks->rc_rxqcr = RXQCR_CMD_CNTL;
|
||||
@ -1488,7 +1181,7 @@ static void ks_setup(struct ks_net *ks)
|
||||
*/
|
||||
|
||||
w = ks_rdreg16(ks, KS_P1MBCR);
|
||||
w &= ~P1MBCR_FORCE_FDX;
|
||||
w &= ~BMCR_FULLDPLX;
|
||||
ks_wrreg16(ks, KS_P1MBCR, w);
|
||||
|
||||
w = TXCR_TXFCE | TXCR_TXPE | TXCR_TXCRC | TXCR_TCGIP;
|
||||
@ -1629,7 +1322,7 @@ static int ks8851_probe(struct platform_device *pdev)
|
||||
ks_setup_int(ks);
|
||||
|
||||
data = ks_rdreg16(ks, KS_OBCR);
|
||||
ks_wrreg16(ks, KS_OBCR, data | OBCR_ODS_16MA);
|
||||
ks_wrreg16(ks, KS_OBCR, data | OBCR_ODS_16mA);
|
||||
|
||||
/* overwriting the default MAC address */
|
||||
if (pdev->dev.of_node) {
|
||||
|
Loading…
Reference in New Issue
Block a user