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Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

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Pull irq fixes from Thomas Gleixner:
 "Three patches addressing shortcomings in the ARM gic interrupt chip
  driver"

* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip: gic: Fix core ID calculation when topology is read from DT
  irqchip: gic: Add binding probe for ARM GIC400
  irqchip: gic: Add support for cortex a7 compatible string
This commit is contained in:
Linus Torvalds 2014-07-19 06:26:01 -10:00
commit cb20fd0779
1 changed files with 6 additions and 1 deletions
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7
drivers/irqchip/irq-gic.c
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@ -42,6 +42,7 @@
#include <linux/irqchip/chained_irq.h> #include <linux/irqchip/chained_irq.h>
#include <linux/irqchip/arm-gic.h> #include <linux/irqchip/arm-gic.h>
#include <asm/cputype.h>
#include <asm/irq.h> #include <asm/irq.h>
#include <asm/exception.h> #include <asm/exception.h>
#include <asm/smp_plat.h> #include <asm/smp_plat.h>
@ -954,7 +955,9 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
} }
for_each_possible_cpu(cpu) { for_each_possible_cpu(cpu) {
unsigned long offset = percpu_offset * cpu_logical_map(cpu); u32 mpidr = cpu_logical_map(cpu);
u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
unsigned long offset = percpu_offset * core_id;
*per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset; *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset;
*per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset; *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset;
} }
@ -1071,8 +1074,10 @@ gic_of_init(struct device_node *node, struct device_node *parent)
gic_cnt++; gic_cnt++;
return 0; return 0;
} }
IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);