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ath5k: Reset Tx interrupt bits also on PISR

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Some cards don't update the PISR properly when all SISR bits
for Tx interrupts are being cleared and as a result we get
interrupt storm. Since we handle all tx queues all together
(so we don't really use the SISR bits to do per-queue interrupt
handling), we can manualy update PISR by doing a write-to-clear
on its Tx interrupt bits.

Signed-off-by: Nick Kossifidis <mickflemm@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Nick Kossifidis 2013-12-07 02:17:40 +00:00 committed by John W. Linville
parent 98b32decc8
commit cb161cda63
1 changed files with 10 additions and 1 deletions
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11
drivers/net/wireless/ath/ath5k/dma.c
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@ -616,7 +616,16 @@ ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
* SISRs will also clear PISR so no need to worry here. * SISRs will also clear PISR so no need to worry here.
*/ */
pisr_clear = pisr & ~AR5K_ISR_BITS_FROM_SISRS; /* XXX: There seems to be an issue on some cards
* with tx interrupt flags not being updated
* on PISR despite that all Tx interrupt bits
* are cleared on SISRs. Since we handle all
* Tx queues all together it shouldn't be an
* issue if we clear Tx interrupt flags also
* on PISR to avoid that.
*/
pisr_clear = (pisr & ~AR5K_ISR_BITS_FROM_SISRS) |
(pisr & AR5K_INT_TX_ALL);
/* /*
* Write to clear them... * Write to clear them...