ARM: dts: STi: Update clocks node location
Move: _ arm_periph_clk node as child of clockgen-a9@92b0000 node _ clk_m_a9_ext2f_div2 node as child of clk_s_c0_flexgen node _ clk-tmdsout-hdmi node outiside soc node This allows to fix the following warnings when compiling dtb with W=1 option : arch/arm/boot/dts/stih410-b2120.dtb: Warning (simple_bus_reg): Node /clocks/clk-m-a9-periphs missing or empty reg/ranges property arch/arm/boot/dts/stih410-b2120.dtb: Warning (simple_bus_reg): Node /clocks/clk-m-a9-ext2f-div2s missing or empty reg/ranges property arch/arm/boot/dts/stih410-b2120.dtb: Warning (simple_bus_reg): Node /clocks/clk-tmdsout-hdmi missing or empty reg/ranges property arch/arm/boot/dts/stih410-b2120.dtb: Warning (simple_bus_reg): Node /clocks/clk-tmdsout-hdmi missing or empty reg/ranges property arch/arm/boot/dts/stih410-b2260.dtb: Warning (simple_bus_reg): Node /clocks/clk-m-a9-periphs missing or empty reg/ranges property arch/arm/boot/dts/stih410-b2260.dtb: Warning (simple_bus_reg): Node /clocks/clk-m-a9-ext2f-div2s missing or empty reg/ranges property arch/arm/boot/dts/stih410-b2260.dtb: Warning (simple_bus_reg): Node /clocks/clk-tmdsout-hdmi missing or empty reg/ranges property arch/arm/boot/dts/stih410-b2260.dtb: Warning (simple_bus_reg): Node /clocks/clk-tmdsout-hdmi missing or empty reg/ranges property arch/arm/boot/dts/stih418-b2199.dtb: Warning (simple_bus_reg): Node /clocks/clk-m-a9-periphs missing or empty reg/ranges property arch/arm/boot/dts/stih418-b2199.dtb: Warning (simple_bus_reg): Node /clocks/clk-m-a9-ext2f-div2s missing or empty reg/ranges property arch/arm/boot/dts/stih418-b2199.dtb: Warning (simple_bus_reg): Node /clocks/clk-tmdsout-hdmi missing or empty reg/ranges property arch/arm/boot/dts/stih418-b2199.dtb: Warning (simple_bus_reg): Node /clocks/clk-tmdsout-hdmi missing or empty reg/ranges property Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This commit is contained in:
parent
5d16b9e338
commit
cb10ca8107
@ -7,32 +7,26 @@
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*/
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*/
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#include <dt-bindings/clock/stih407-clks.h>
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#include <dt-bindings/clock/stih407-clks.h>
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/ {
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/ {
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/*
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* Fixed 30MHz oscillator inputs to SoC
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*/
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clk_sysin: clk-sysin {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <30000000>;
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};
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clk_tmdsout_hdmi: clk-tmdsout-hdmi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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clocks {
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clocks {
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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#size-cells = <1>;
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ranges;
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ranges;
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/*
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* Fixed 30MHz oscillator inputs to SoC
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*/
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clk_sysin: clk-sysin {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <30000000>;
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};
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/*
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* ARM Peripheral clock for timers
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*/
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arm_periph_clk: clk-m-a9-periphs {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&clk_m_a9>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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/*
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/*
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* A9 PLL.
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* A9 PLL.
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*/
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*/
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@ -62,21 +56,19 @@
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<&clockgen_a9_pll 0>,
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<&clockgen_a9_pll 0>,
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<&clk_s_c0_flexgen 13>,
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<&clk_s_c0_flexgen 13>,
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<&clk_m_a9_ext2f_div2>;
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<&clk_m_a9_ext2f_div2>;
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};
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/*
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* ARM Peripheral clock for timers
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*/
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clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&clk_s_c0_flexgen 13>;
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/*
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* ARM Peripheral clock for timers
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*/
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arm_periph_clk: clk-m-a9-periphs {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-output-names = "clk-m-a9-ext2f-div2";
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clocks = <&clk_m_a9>;
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clock-div = <2>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-mult = <1>;
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};
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};
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};
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/*
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/*
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@ -204,6 +196,21 @@
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<CLK_EXT2F_A9>,
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<CLK_EXT2F_A9>,
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<CLK_ICN_LMI>,
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<CLK_ICN_LMI>,
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<CLK_ICN_SBC>;
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<CLK_ICN_SBC>;
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/*
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* ARM Peripheral clock for timers
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*/
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clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&clk_s_c0_flexgen 13>;
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clock-output-names = "clk-m-a9-ext2f-div2";
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clock-div = <2>;
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clock-mult = <1>;
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};
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};
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};
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};
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};
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@ -254,12 +261,6 @@
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"clk-s-d2-fs0-ch3";
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"clk-s-d2-fs0-ch3";
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};
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};
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clk_tmdsout_hdmi: clk-tmdsout-hdmi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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clockgen-d2@9106000 {
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clockgen-d2@9106000 {
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compatible = "st,clkgen-c32";
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compatible = "st,clkgen-c32";
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reg = <0x9106000 0x1000>;
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reg = <0x9106000 0x1000>;
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@ -7,6 +7,22 @@
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*/
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*/
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#include <dt-bindings/clock/stih410-clks.h>
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#include <dt-bindings/clock/stih410-clks.h>
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/ {
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/ {
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/*
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* Fixed 30MHz oscillator inputs to SoC
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*/
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clk_sysin: clk-sysin {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <30000000>;
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clock-output-names = "CLK_SYSIN";
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};
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clk_tmdsout_hdmi: clk-tmdsout-hdmi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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clocks {
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clocks {
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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#size-cells = <1>;
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@ -14,27 +30,6 @@
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compatible = "st,stih410-clk", "simple-bus";
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compatible = "st,stih410-clk", "simple-bus";
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/*
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* Fixed 30MHz oscillator inputs to SoC
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*/
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clk_sysin: clk-sysin {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <30000000>;
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clock-output-names = "CLK_SYSIN";
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};
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/*
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* ARM Peripheral clock for timers
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*/
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arm_periph_clk: clk-m-a9-periphs {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&clk_m_a9>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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/*
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/*
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* A9 PLL.
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* A9 PLL.
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*/
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*/
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@ -64,21 +59,16 @@
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<&clockgen_a9_pll 0>,
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<&clockgen_a9_pll 0>,
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<&clk_s_c0_flexgen 13>,
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<&clk_s_c0_flexgen 13>,
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<&clk_m_a9_ext2f_div2>;
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<&clk_m_a9_ext2f_div2>;
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};
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/*
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* ARM Peripheral clock for timers
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/*
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*/
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* ARM Peripheral clock for timers
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arm_periph_clk: clk-m-a9-periphs {
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*/
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#clock-cells = <0>;
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clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clocks = <&clk_m_a9>;
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compatible = "fixed-factor-clock";
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clock-div = <2>;
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clock-mult = <1>;
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clocks = <&clk_s_c0_flexgen 13>;
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};
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clock-output-names = "clk-m-a9-ext2f-div2";
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clock-div = <2>;
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clock-mult = <1>;
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};
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};
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/*
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/*
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@ -214,6 +204,21 @@
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<CLK_EXT2F_A9>,
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<CLK_EXT2F_A9>,
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<CLK_ICN_LMI>,
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<CLK_ICN_LMI>,
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<CLK_ICN_SBC>;
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<CLK_ICN_SBC>;
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/*
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* ARM Peripheral clock for timers
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*/
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clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&clk_s_c0_flexgen 13>;
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clock-output-names = "clk-m-a9-ext2f-div2";
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clock-div = <2>;
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clock-mult = <1>;
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};
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};
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};
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};
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};
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@ -266,12 +271,6 @@
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"clk-s-d2-fs0-ch3";
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"clk-s-d2-fs0-ch3";
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};
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};
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clk_tmdsout_hdmi: clk-tmdsout-hdmi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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clockgen-d2@9106000 {
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clockgen-d2@9106000 {
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compatible = "st,clkgen-c32";
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compatible = "st,clkgen-c32";
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reg = <0x9106000 0x1000>;
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reg = <0x9106000 0x1000>;
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@ -7,6 +7,22 @@
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*/
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*/
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#include <dt-bindings/clock/stih418-clks.h>
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#include <dt-bindings/clock/stih418-clks.h>
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/ {
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/ {
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/*
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* Fixed 30MHz oscillator inputs to SoC
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*/
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clk_sysin: clk-sysin {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <30000000>;
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clock-output-names = "CLK_SYSIN";
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};
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clk_tmdsout_hdmi: clk-tmdsout-hdmi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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clocks {
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clocks {
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stih418-clk", "simple-bus";
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compatible = "st,stih418-clk", "simple-bus";
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/*
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* Fixed 30MHz oscillator inputs to SoC
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*/
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clk_sysin: clk-sysin {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <30000000>;
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clock-output-names = "CLK_SYSIN";
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};
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/*
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* ARM Peripheral clock for timers
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*/
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arm_periph_clk: clk-m-a9-periphs {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&clk_m_a9>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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/*
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/*
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* A9 PLL.
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* A9 PLL.
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*/
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*/
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<&clockgen_a9_pll 0>,
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<&clockgen_a9_pll 0>,
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<&clk_s_c0_flexgen 13>,
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<&clk_s_c0_flexgen 13>,
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<&clk_m_a9_ext2f_div2>;
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<&clk_m_a9_ext2f_div2>;
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};
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/*
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/*
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* ARM Peripheral clock for timers
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* ARM Peripheral clock for timers
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*/
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*/
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clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
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arm_periph_clk: clk-m-a9-periphs {
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#clock-cells = <0>;
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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compatible = "fixed-factor-clock";
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clocks = <&clk_m_a9>;
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clocks = <&clk_s_c0_flexgen 13>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "clk-m-a9-ext2f-div2";
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};
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clock-div = <2>;
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clock-mult = <1>;
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};
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};
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/*
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/*
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"clk-proc-mixer",
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"clk-proc-mixer",
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"clk-proc-sc",
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"clk-proc-sc",
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"clk-avsp-hevc";
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"clk-avsp-hevc";
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/*
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* ARM Peripheral clock for timers
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*/
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clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&clk_s_c0_flexgen 13>;
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clock-output-names = "clk-m-a9-ext2f-div2";
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clock-div = <2>;
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clock-mult = <1>;
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};
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};
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};
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};
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};
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"clk-s-d2-fs0-ch3";
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"clk-s-d2-fs0-ch3";
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};
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};
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clk_tmdsout_hdmi: clk-tmdsout-hdmi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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clockgen-d2@9106000 {
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clockgen-d2@9106000 {
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compatible = "st,clkgen-c32";
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compatible = "st,clkgen-c32";
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reg = <0x9106000 0x1000>;
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reg = <0x9106000 0x1000>;
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Block a user