ARM: dts: STi: Update clocks node location

Move:
 _ arm_periph_clk node as child of clockgen-a9@92b0000 node
 _ clk_m_a9_ext2f_div2 node as child of clk_s_c0_flexgen node
 _ clk-tmdsout-hdmi node outiside soc node

This allows to fix the following warnings when compiling
dtb with W=1 option :

arch/arm/boot/dts/stih410-b2120.dtb: Warning (simple_bus_reg):
Node /clocks/clk-m-a9-periphs missing or empty reg/ranges property
arch/arm/boot/dts/stih410-b2120.dtb: Warning (simple_bus_reg):
Node /clocks/clk-m-a9-ext2f-div2s missing or empty reg/ranges property
arch/arm/boot/dts/stih410-b2120.dtb: Warning (simple_bus_reg):
Node /clocks/clk-tmdsout-hdmi missing or empty reg/ranges property
arch/arm/boot/dts/stih410-b2120.dtb: Warning (simple_bus_reg):
Node /clocks/clk-tmdsout-hdmi missing or empty reg/ranges property

arch/arm/boot/dts/stih410-b2260.dtb: Warning (simple_bus_reg):
Node /clocks/clk-m-a9-periphs missing or empty reg/ranges property
arch/arm/boot/dts/stih410-b2260.dtb: Warning (simple_bus_reg):
Node /clocks/clk-m-a9-ext2f-div2s missing or empty reg/ranges property
arch/arm/boot/dts/stih410-b2260.dtb: Warning (simple_bus_reg):
Node /clocks/clk-tmdsout-hdmi missing or empty reg/ranges property
arch/arm/boot/dts/stih410-b2260.dtb: Warning (simple_bus_reg):
Node /clocks/clk-tmdsout-hdmi missing or empty reg/ranges property

arch/arm/boot/dts/stih418-b2199.dtb: Warning (simple_bus_reg):
Node /clocks/clk-m-a9-periphs missing or empty reg/ranges property
arch/arm/boot/dts/stih418-b2199.dtb: Warning (simple_bus_reg):
Node /clocks/clk-m-a9-ext2f-div2s missing or empty reg/ranges property
arch/arm/boot/dts/stih418-b2199.dtb: Warning (simple_bus_reg):
Node /clocks/clk-tmdsout-hdmi missing or empty reg/ranges property
arch/arm/boot/dts/stih418-b2199.dtb: Warning (simple_bus_reg):
Node /clocks/clk-tmdsout-hdmi missing or empty reg/ranges property

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

arch/arm/boot/dts/stih407-clock.dtsi

@@ -7,11 +7,6 @@
  */
 #include <dt-bindings/clock/stih407-clks.h>
 / {
-	clocks {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
 	/*
 	 * Fixed 30MHz oscillator inputs to SoC
 	 */
@@ -21,18 +16,17 @@
 		clock-frequency = <30000000>;
 	};
 
-		/*
+	clk_tmdsout_hdmi: clk-tmdsout-hdmi {
-		 * ARM Peripheral clock for timers
-		 */
-		arm_periph_clk: clk-m-a9-periphs {
 		#clock-cells = <0>;
-			compatible = "fixed-factor-clock";
+		compatible = "fixed-clock";
-
+		clock-frequency = <0>;
-			clocks = <&clk_m_a9>;
-			clock-div = <2>;
-			clock-mult = <1>;
 	};
 
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
 		/*
 		 * A9 PLL.
 		 */
@@ -62,22 +56,20 @@
 				 <&clockgen_a9_pll 0>,
 				 <&clk_s_c0_flexgen 13>,
 				 <&clk_m_a9_ext2f_div2>;
-		};
+
 
 			/*
 			 * ARM Peripheral clock for timers
 			 */
-		clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
+			arm_periph_clk: clk-m-a9-periphs {
 				#clock-cells = <0>;
 				compatible = "fixed-factor-clock";
 
-			clocks = <&clk_s_c0_flexgen 13>;
+				clocks = <&clk_m_a9>;
-
-			clock-output-names = "clk-m-a9-ext2f-div2";
-
 				clock-div = <2>;
 				clock-mult = <1>;
 			};
+		};
 
 		/*
 		 * Bootloader initialized system infrastructure clock for
@@ -204,6 +196,21 @@
 						 <CLK_EXT2F_A9>,
 						 <CLK_ICN_LMI>,
 						 <CLK_ICN_SBC>;
+
+				/*
+				 * ARM Peripheral clock for timers
+				 */
+				clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
+					#clock-cells = <0>;
+					compatible = "fixed-factor-clock";
+
+					clocks = <&clk_s_c0_flexgen 13>;
+
+					clock-output-names = "clk-m-a9-ext2f-div2";
+
+					clock-div = <2>;
+					clock-mult = <1>;
+				};
 			};
 		};
 
@@ -254,12 +261,6 @@
 					     "clk-s-d2-fs0-ch3";
 		};
 
-		clk_tmdsout_hdmi: clk-tmdsout-hdmi {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <0>;
-		};
-
 		clockgen-d2@9106000 {
 			compatible = "st,clkgen-c32";
 			reg = <0x9106000 0x1000>;

arch/arm/boot/dts/stih410-clock.dtsi

@@ -7,13 +7,6 @@
  */
 #include <dt-bindings/clock/stih410-clks.h>
 / {
-	clocks {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		compatible = "st,stih410-clk", "simple-bus";
-
 	/*
 	 * Fixed 30MHz oscillator inputs to SoC
 	 */
@@ -24,17 +17,19 @@
 		clock-output-names = "CLK_SYSIN";
 	};
 
-		/*
+	clk_tmdsout_hdmi: clk-tmdsout-hdmi {
-		 * ARM Peripheral clock for timers
-		 */
-		arm_periph_clk: clk-m-a9-periphs {
 		#clock-cells = <0>;
-			compatible = "fixed-factor-clock";
+		compatible = "fixed-clock";
-			clocks = <&clk_m_a9>;
+		clock-frequency = <0>;
-			clock-div = <2>;
-			clock-mult = <1>;
 	};
 
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		compatible = "st,stih410-clk", "simple-bus";
+
 		/*
 		 * A9 PLL.
 		 */
@@ -64,22 +59,17 @@
 				 <&clockgen_a9_pll 0>,
 				 <&clk_s_c0_flexgen 13>,
 				 <&clk_m_a9_ext2f_div2>;
-		};
-
 			/*
 			 * ARM Peripheral clock for timers
 			 */
-		clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
+			arm_periph_clk: clk-m-a9-periphs {
 				#clock-cells = <0>;
 				compatible = "fixed-factor-clock";
-
+				clocks = <&clk_m_a9>;
-			clocks = <&clk_s_c0_flexgen 13>;
-
-			clock-output-names = "clk-m-a9-ext2f-div2";
-
 				clock-div = <2>;
 				clock-mult = <1>;
 			};
+		};
 
 		/*
 		 * Bootloader initialized system infrastructure clock for
@@ -214,6 +204,21 @@
 						 <CLK_EXT2F_A9>,
 						 <CLK_ICN_LMI>,
 						 <CLK_ICN_SBC>;
+
+				/*
+				 * ARM Peripheral clock for timers
+				 */
+				clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
+					#clock-cells = <0>;
+					compatible = "fixed-factor-clock";
+
+					clocks = <&clk_s_c0_flexgen 13>;
+
+					clock-output-names = "clk-m-a9-ext2f-div2";
+
+					clock-div = <2>;
+					clock-mult = <1>;
+				};
 			};
 		};
 
@@ -266,12 +271,6 @@
 					     "clk-s-d2-fs0-ch3";
 		};
 
-		clk_tmdsout_hdmi: clk-tmdsout-hdmi {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <0>;
-		};
-
 		clockgen-d2@9106000 {
 			compatible = "st,clkgen-c32";
 			reg = <0x9106000 0x1000>;

arch/arm/boot/dts/stih418-clock.dtsi

@@ -7,13 +7,6 @@
  */
 #include <dt-bindings/clock/stih418-clks.h>
 / {
-	clocks {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		compatible = "st,stih418-clk", "simple-bus";
-
 	/*
 	 * Fixed 30MHz oscillator inputs to SoC
 	 */
@@ -24,17 +17,19 @@
 		clock-output-names = "CLK_SYSIN";
 	};
 
-		/*
+	clk_tmdsout_hdmi: clk-tmdsout-hdmi {
-		 * ARM Peripheral clock for timers
-		 */
-		arm_periph_clk: clk-m-a9-periphs {
 		#clock-cells = <0>;
-			compatible = "fixed-factor-clock";
+		compatible = "fixed-clock";
-			clocks = <&clk_m_a9>;
+		clock-frequency = <0>;
-			clock-div = <2>;
-			clock-mult = <1>;
 	};
 
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		compatible = "st,stih418-clk", "simple-bus";
+
 		/*
 		 * A9 PLL.
 		 */
@@ -64,22 +59,18 @@
 				 <&clockgen_a9_pll 0>,
 				 <&clk_s_c0_flexgen 13>,
 				 <&clk_m_a9_ext2f_div2>;
-		};
 
 			/*
 			 * ARM Peripheral clock for timers
 			 */
-		clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
+			arm_periph_clk: clk-m-a9-periphs {
 				#clock-cells = <0>;
 				compatible = "fixed-factor-clock";
-
+				clocks = <&clk_m_a9>;
-			clocks = <&clk_s_c0_flexgen 13>;
-
-			clock-output-names = "clk-m-a9-ext2f-div2";
-
 				clock-div = <2>;
 				clock-mult = <1>;
 			};
+		};
 
 		/*
 		 * Bootloader initialized system infrastructure clock for
@@ -207,6 +198,21 @@
 						     "clk-proc-mixer",
 						     "clk-proc-sc",
 						     "clk-avsp-hevc";
+
+				/*
+				 * ARM Peripheral clock for timers
+				 */
+				clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
+					#clock-cells = <0>;
+					compatible = "fixed-factor-clock";
+
+					clocks = <&clk_s_c0_flexgen 13>;
+
+					clock-output-names = "clk-m-a9-ext2f-div2";
+
+					clock-div = <2>;
+					clock-mult = <1>;
+				};
 			};
 		};
 
@@ -259,12 +265,6 @@
 					     "clk-s-d2-fs0-ch3";
 		};
 
-		clk_tmdsout_hdmi: clk-tmdsout-hdmi {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <0>;
-		};
-
 		clockgen-d2@9106000 {
 			compatible = "st,clkgen-c32";
 			reg = <0x9106000 0x1000>;