forked from Minki/linux
OMAP2xxx OPP: clean up comments in OPP data
Revise some of the comments in the OMAP2xxx OPP data for clarity. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Richard Woodruff <r-woodruff2@ti.com>
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Paul Walmsley
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19fe458310
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ca6eccb31e
@ -9,45 +9,47 @@
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* The OMAP2 processor can be run at several discrete 'PRCM configurations'.
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* These configurations are characterized by voltage and speed for clocks.
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* The device is only validated for certain combinations. One way to express
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* these combinations is via the 'ratio's' which the clocks operate with
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* these combinations is via the 'ratios' which the clocks operate with
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* respect to each other. These ratio sets are for a given voltage/DPLL
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* setting. All configurations can be described by a DPLL setting and a ratio
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* There are 3 ratio sets for the 2430 and X ratio sets for 2420.
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*
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* 2430 differs from 2420 in that there are no more phase synchronizers used.
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* They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
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* 2430 (iva2.1, NOdsp, mdm)
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* setting. All configurations can be described by a DPLL setting and a ratio.
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*
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* XXX Missing voltage data.
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* XXX Missing 19.2MHz sys_clk rate sets (needed for N800/N810)
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*
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* THe format described in this file is deprecated. Once a reasonable
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* OPP API exists, the data in this file should be converted to use it.
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*
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* This is technically part of the OMAP2xxx clock code.
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*
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* Considerable work is still needed to fully support dynamic frequency
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* changes on OMAP2xxx-series chips. Readers interested in such a
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* project are encouraged to review the Maemo Diablo RX-34 and RX-44
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* kernel source at:
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* http://repository.maemo.org/pool/diablo/free/k/kernel-source-diablo/
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*/
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#include "opp2xxx.h"
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#include "sdrc.h"
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#include "clock.h"
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/*-------------------------------------------------------------------------
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* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
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/*
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* Key dividers which make up a PRCM set. Ratios for a PRCM are mandated.
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* xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
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* CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
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* CM_CLKSEL2_PLL, CM_CLKSEL_MDM
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*
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* Filling in table based on H4 boards and 2430-SDPs variants available.
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* There are quite a few more rates combinations which could be defined.
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* Filling in table based on H4 boards available. There are quite a
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* few more rate combinations which could be defined.
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*
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* When multiple values are defined the start up will try and choose the
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* fastest one. If a 'fast' value is defined, then automatically, the /2
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* one should be included as it can be used. Generally having more that
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* one fast set does not make sense, as static timings need to be changed
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* to change the set. The exception is the bypass setting which is
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* availble for low power bypass.
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* When multiple values are defined the start up will try and choose
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* the fastest one. If a 'fast' value is defined, then automatically,
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* the /2 one should be included as it can be used. Generally having
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* more than one fast set does not make sense, as static timings need
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* to be changed to change the set. The exception is the bypass
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* setting which is available for low power bypass.
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*
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* Note: This table needs to be sorted, fastest to slowest.
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*-------------------------------------------------------------------------*/
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**/
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const struct prcm_config omap2420_rate_table[] = {
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/* PRCM I - FAST */
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{S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
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@ -1,5 +1,5 @@
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/*
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* opp2420_data.c - old-style "OPP" table for OMAP2420
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* opp2430_data.c - old-style "OPP" table for OMAP2430
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*
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* Copyright (C) 2005-2009 Texas Instruments, Inc.
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* Copyright (C) 2004-2009 Nokia Corporation
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@ -9,16 +9,16 @@
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* The OMAP2 processor can be run at several discrete 'PRCM configurations'.
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* These configurations are characterized by voltage and speed for clocks.
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* The device is only validated for certain combinations. One way to express
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* these combinations is via the 'ratio's' which the clocks operate with
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* these combinations is via the 'ratios' which the clocks operate with
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* respect to each other. These ratio sets are for a given voltage/DPLL
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* setting. All configurations can be described by a DPLL setting and a ratio
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* There are 3 ratio sets for the 2430 and X ratio sets for 2420.
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* setting. All configurations can be described by a DPLL setting and a ratio.
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*
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* 2430 differs from 2420 in that there are no more phase synchronizers used.
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* They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
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* 2430 (iva2.1, NOdsp, mdm)
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*
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* XXX Missing voltage data.
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* XXX Missing 19.2MHz sys_clk rate sets.
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*
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* THe format described in this file is deprecated. Once a reasonable
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* OPP API exists, the data in this file should be converted to use it.
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@ -30,24 +30,24 @@
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#include "sdrc.h"
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#include "clock.h"
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/*-------------------------------------------------------------------------
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* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
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/*
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* Key dividers which make up a PRCM set. Ratios for a PRCM are mandated.
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* xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
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* CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
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* CM_CLKSEL2_PLL, CM_CLKSEL_MDM
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*
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* Filling in table based on H4 boards and 2430-SDPs variants available.
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* There are quite a few more rates combinations which could be defined.
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* Filling in table based on 2430-SDPs variants available. There are
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* quite a few more rate combinations which could be defined.
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*
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* When multiple values are defined the start up will try and choose the
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* fastest one. If a 'fast' value is defined, then automatically, the /2
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* one should be included as it can be used. Generally having more that
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* one fast set does not make sense, as static timings need to be changed
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* to change the set. The exception is the bypass setting which is
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* availble for low power bypass.
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* When multiple values are defined the start up will try and choose
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* the fastest one. If a 'fast' value is defined, then automatically,
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* the /2 one should be included as it can be used. Generally having
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* more than one fast set does not make sense, as static timings need
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* to be changed to change the set. The exception is the bypass
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* setting which is available for low power bypass.
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*
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* Note: This table needs to be sorted, fastest to slowest.
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*-------------------------------------------------------------------------*/
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*/
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const struct prcm_config omap2430_rate_table[] = {
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/* PRCM #4 - ratio2 (ES2.1) - FAST */
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{S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */
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