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dt-bindings: memory: tegra: Document #reset-cells property of the Tegra30 MC

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Memory Controller has a memory client "hot reset" functionality, which
resets the DMA interface of a memory client. So MC is a reset controller
in addition to IOMMU.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Dmitry Osipenko 2018-04-09 22:28:24 +03:00 committed by Thierry Reding
parent cce5819ba3
commit ca545e6c80
1 changed files with 5 additions and 0 deletions
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Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt
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@ -12,6 +12,9 @@ Required properties:
- clock-names: Must include the following entries: - clock-names: Must include the following entries:
- mc: the module's clock input - mc: the module's clock input
- interrupts: The interrupt outputs from the controller. - interrupts: The interrupt outputs from the controller.
- #reset-cells : Should be 1. This cell represents memory client module ID.
The assignments may be found in header file <dt-bindings/memory/tegra30-mc.h>
or in the TRM documentation.
Required properties for Tegra30, Tegra114, Tegra124, Tegra132 and Tegra210: Required properties for Tegra30, Tegra114, Tegra124, Tegra132 and Tegra210:
- #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines - #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines
@ -72,12 +75,14 @@ Example SoC include file:
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>; #iommu-cells = <1>;
#reset-cells = <1>;
}; };
sdhci@700b0000 { sdhci@700b0000 {
compatible = "nvidia,tegra124-sdhci"; compatible = "nvidia,tegra124-sdhci";
... ...
iommus = <&mc TEGRA_SWGROUP_SDMMC1A>; iommus = <&mc TEGRA_SWGROUP_SDMMC1A>;
resets = <&mc TEGRA124_MC_RESET_SDMMC1>;
}; };
}; };