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drm/tegra: sor - Change power down ordering

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Lanes are powered up in decreasing order. Power them down in increasing
order for consistency.

Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Stéphane Marchesin 2014-05-22 20:32:48 -07:00 committed by Thierry Reding
parent 143b1df23e
commit ca185c68ed
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/tegra/sor.c
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@ -748,7 +748,7 @@ static int tegra_sor_power_down(struct tegra_sor *sor)
tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
/* stop lane sequencer */ /* stop lane sequencer */
value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
SOR_LANE_SEQ_CTL_POWER_STATE_DOWN; SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);