V4L/DVB (13983): [STV6110x] add clk_div member to stv6110x_config structure
Using clk_div member of stv6110x_config structure the tuner's clock output divider can be configured. It is set in stv6110x_attach. Signed-off-by: Andreas Regel <andreas.regel@gmx.de> Signed-off-by: Manu Abraham <manu@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
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@ -362,6 +362,7 @@ struct stv6110x_devctl *stv6110x_attach(struct dvb_frontend *fe,
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{
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{
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struct stv6110x_state *stv6110x;
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struct stv6110x_state *stv6110x;
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u8 default_regs[] = {0x07, 0x11, 0xdc, 0x85, 0x17, 0x01, 0xe6, 0x1e};
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u8 default_regs[] = {0x07, 0x11, 0xdc, 0x85, 0x17, 0x01, 0xe6, 0x1e};
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int ret;
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stv6110x = kzalloc(sizeof (struct stv6110x_state), GFP_KERNEL);
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stv6110x = kzalloc(sizeof (struct stv6110x_state), GFP_KERNEL);
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if (stv6110x == NULL)
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if (stv6110x == NULL)
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@ -372,6 +373,43 @@ struct stv6110x_devctl *stv6110x_attach(struct dvb_frontend *fe,
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stv6110x->devctl = &stv6110x_ctl;
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stv6110x->devctl = &stv6110x_ctl;
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memcpy(stv6110x->regs, default_regs, 8);
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memcpy(stv6110x->regs, default_regs, 8);
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/* setup divider */
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switch (stv6110x->config->clk_div) {
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default:
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case 1:
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STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 0);
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break;
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case 2:
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STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 1);
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break;
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case 4:
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STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 2);
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break;
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case 8:
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case 0:
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STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 3);
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break;
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}
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if (fe->ops.i2c_gate_ctrl) {
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ret = fe->ops.i2c_gate_ctrl(fe, 1);
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if (ret < 0)
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goto error;
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}
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ret = stv6110x_write_regs(stv6110x, 0, stv6110x->regs,
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ARRAY_SIZE(stv6110x->regs));
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if (ret < 0) {
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dprintk(FE_ERROR, 1, "Initialization failed");
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goto error;
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}
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if (fe->ops.i2c_gate_ctrl) {
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ret = fe->ops.i2c_gate_ctrl(fe, 0);
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if (ret < 0)
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goto error;
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}
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fe->tuner_priv = stv6110x;
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fe->tuner_priv = stv6110x;
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fe->ops.tuner_ops = stv6110x_ops;
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fe->ops.tuner_ops = stv6110x_ops;
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@ -26,6 +26,7 @@
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struct stv6110x_config {
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struct stv6110x_config {
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u8 addr;
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u8 addr;
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u32 refclk;
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u32 refclk;
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u8 clk_div; /* divisor value for the output clock */
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};
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};
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enum tuner_mode {
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enum tuner_mode {
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