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drm/amd/pm: Add support for reset completion on aldebaran

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v1: On aldebaran, after hardware context restore, another handshake
needs to happen with PMFW so that reset recovery is complete from
PMFW side. Treat this as RESET_COMPLETE event for aldebaran.

v2: Cleanup coding style, info logs

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Lijo Lazar 2021-03-16 19:47:51 +08:00 committed by Alex Deucher
parent 6d77dd9f75
commit c941e9fe9c
5 changed files with 36 additions and 2 deletions
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3
drivers/gpu/drm/amd/pm/inc/aldebaran_ppsmc.h
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@ -100,7 +100,8 @@
#define PPSMC_MSG_SetSystemVirtualSTBtoDramAddrHigh 0x40
#define PPSMC_MSG_SetSystemVirtualSTBtoDramAddrLow 0x41
#define PPSMC_Message_Count 0x42
#define PPSMC_MSG_GfxDriverResetRecovery 0x42
#define PPSMC_Message_Count 0x43
//PPSMC Reset Types
#define PPSMC_RESET_TYPE_WARM_RESET 0x00

1
drivers/gpu/drm/amd/pm/inc/smu_types.h
View File

@ -225,6 +225,7 @@
__SMU_DUMMY_MAP(DisableDeterminism), \
__SMU_DUMMY_MAP(SetUclkDpmMode), \
__SMU_DUMMY_MAP(LightSBR), \
__SMU_DUMMY_MAP(GfxDriverResetRecovery),
#undef __SMU_DUMMY_MAP
#define __SMU_DUMMY_MAP(type) SMU_MSG_##type

3
drivers/gpu/drm/amd/pm/inc/smu_v13_0.h
View File

@ -268,5 +268,8 @@ int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu);
int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
bool enablement);
int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
uint64_t event_arg);
#endif
#endif

4
drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
View File

@ -126,7 +126,8 @@ static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT
MSG_MAP(SetExecuteDMATest, PPSMC_MSG_SetExecuteDMATest, 0),
MSG_MAP(EnableDeterminism, PPSMC_MSG_EnableDeterminism, 0),
MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0),
MSG_MAP(SetUclkDpmMode, PPSMC_MSG_SetUclkDpmMode, 0),
MSG_MAP(SetUclkDpmMode, PPSMC_MSG_SetUclkDpmMode, 0),
MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0),
};
static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = {
@ -1583,6 +1584,7 @@ static const struct pptable_funcs aldebaran_ppt_funcs = {
.mode1_reset = smu_v13_0_mode1_reset,
.set_mp1_state = aldebaran_set_mp1_state,
.mode2_reset = aldebaran_mode2_reset,
.wait_for_event = smu_v13_0_wait_for_event,
};
void aldebaran_set_ppt_funcs(struct smu_context *smu)

27
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
View File

@ -1374,6 +1374,33 @@ int smu_v13_0_mode1_reset(struct smu_context *smu)
return ret;
}
static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu,
uint64_t event_arg)
{
int ret = 0;
dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
return ret;
}
int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
uint64_t event_arg)
{
int ret = -EINVAL;
switch (event) {
case SMU_EVENT_RESET_COMPLETE:
ret = smu_v13_0_wait_for_reset_complete(smu, event_arg);
break;
default:
break;
}
return ret;
}
int smu_v13_0_mode2_reset(struct smu_context *smu)
{
int ret;