forked from Minki/linux
Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: [POWERPC] Move serial_dev_init to device_initcall() [POWERPC] Enable GENERIC_ISA_DMA if FSL_ULI1575 to fix compile issue [POWERPC] cpm2: Fix off-by-one error in setbrg(). [PPC] 8xx: Fix r3 trashing due to 8MB TLB page instantiation [POWERPC] 8{5,6}xx: Fix build issue with !CONFIG_PCI
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commit
c87ce65868
@ -493,7 +493,7 @@ static int __init serial_dev_init(void)
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return platform_device_register(&serial_device);
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}
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arch_initcall(serial_dev_init);
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device_initcall(serial_dev_init);
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/*
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@ -178,7 +178,9 @@ define_machine(mpc8544_ds) {
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.probe = mpc8544_ds_probe,
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.setup_arch = mpc8544_ds_setup_arch,
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.init_IRQ = mpc8544_ds_pic_init,
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#ifdef CONFIG_PCI
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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#endif
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.get_irq = mpic_get_irq,
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.restart = mpc85xx_restart,
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.calibrate_decr = generic_calibrate_decr,
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@ -351,10 +351,10 @@ define_machine(mpc85xx_cds) {
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.get_irq = mpic_get_irq,
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#ifdef CONFIG_PCI
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.restart = mpc85xx_cds_restart,
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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#else
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.restart = mpc85xx_restart,
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#endif
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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};
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@ -207,5 +207,7 @@ define_machine(mpc85xx_mds) {
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.restart = mpc85xx_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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#ifdef CONFIG_PCI
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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#endif
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};
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@ -250,5 +250,7 @@ define_machine(mpc86xx_hpcn) {
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.time_init = mpc86xx_time_init,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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#ifdef CONFIG_PCI
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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#endif
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};
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@ -285,6 +285,7 @@ config AXON_RAM
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config FSL_ULI1575
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bool
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default n
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select GENERIC_ISA_DMA
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help
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Supports for the ULI1575 PCIe south bridge that exists on some
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Freescale reference boards. The boards all use the ULI in pretty
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@ -102,7 +102,7 @@ cpm_setbrg(uint brg, uint rate)
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brg -= 4;
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}
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bp += brg;
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*bp = ((BRG_UART_CLK / rate) << 1) | CPM_BRG_EN;
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out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN);
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cpm2_unmap(bp);
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}
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@ -495,9 +495,7 @@ LoadLargeDTLB:
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lwz r11, 4(r0)
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lwz r12, 16(r0)
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#ifdef CONFIG_8xx_CPU6
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lwz r3, 8(r0)
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#endif
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rfi
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/* This is the data TLB error on the MPC8xx. This could be due to
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