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Merge branch 'topic/xehp-dg2-definitions-2021-07-21' into drm-intel-next

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As we begin applying XeHP and DG2 patches, the basic platform
definitions and macros (like IS_DG2()) will be needed in both
drm-intel-next and drm-intel-gt-next.  Those initial definition patches
are applied to a topic branch and merged to both trees.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
This commit is contained in:
Matt Roper
2021-07-22 09:23:00 -07:00
parent 46b0d7091c 9e22cfc5e9
commit c86fc48a24
5 changed files with 129 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

33
drivers/gpu/drm/i915/i915_drv.h
View File

@@ -1243,6 +1243,8 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
#define IP_VER(ver, rel) ((ver) << 8 | (rel))
#define IP_VER(ver, rel) ((ver) << 8 | (rel))
#define GRAPHICS_VER(i915) (INTEL_INFO(i915)->graphics_ver)
#define GRAPHICS_VER_FULL(i915) IP_VER(INTEL_INFO(i915)->graphics_ver, \
INTEL_INFO(i915)->graphics_rel)
@@ -1380,6 +1382,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
#define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV)
#define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG2)
#define IS_DG2_G10(dev_priv) \
IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
#define IS_DG2_G11(dev_priv) \
IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv) \
@@ -1490,6 +1498,31 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
(IS_ALDERLAKE_P(__i915) && \
IS_GT_STEP(__i915, since, until))
#define IS_XEHPSDV_GT_STEP(p, since, until) \
(IS_XEHPSDV(p) && IS_GT_STEP(__i915, since, until))
/*
* DG2 hardware steppings are a bit unusual. The hardware design was forked
* to create two variants (G10 and G11) which have distinct workaround sets.
* The G11 fork of the DG2 design resets the GT stepping back to "A0" for its
* first iteration, even though it's more similar to a G10 B0 stepping in terms
* of functionality and workarounds. However the display stepping does not
* reset in the same manner --- a specific stepping like "B0" has a consistent
* meaning regardless of whether it belongs to a G10 or G11 DG2.
*
* TLDR: All GT workarounds and stepping-specific logic must be applied in
* relation to a specific subplatform (G10 or G11), whereas display workarounds
* and stepping-specific logic will be applied with a general DG2-wide stepping
* number.
*/
#define IS_DG2_GT_STEP(__i915, variant, since, until) \
(IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \
IS_GT_STEP(__i915, since, until))
#define IS_DG2_DISP_STEP(__i915, since, until) \
(IS_DG2(__i915) && \
IS_DISPLAY_STEP(__i915, since, until))
#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
#define IS_GEN9_LP(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv))

59
drivers/gpu/drm/i915/i915_pci.c
View File

@@ -995,6 +995,65 @@ static const struct intel_device_info adl_p_info = {
};
#undef GEN
#define XE_HP_PAGE_SIZES \
.page_sizes = I915_GTT_PAGE_SIZE_4K | \
I915_GTT_PAGE_SIZE_64K | \
I915_GTT_PAGE_SIZE_2M
#define XE_HP_FEATURES \
.graphics_ver = 12, \
.graphics_rel = 50, \
XE_HP_PAGE_SIZES, \
.dma_mask_size = 46, \
.has_64bit_reloc = 1, \
.has_global_mocs = 1, \
.has_gt_uc = 1, \
.has_llc = 1, \
.has_logical_ring_contexts = 1, \
.has_logical_ring_elsq = 1, \
.has_rc6 = 1, \
.has_reset_engine = 1, \
.has_rps = 1, \
.has_runtime_pm = 1, \
.ppgtt_size = 48, \
.ppgtt_type = INTEL_PPGTT_FULL
#define XE_HPM_FEATURES \
.media_ver = 12, \
.media_rel = 50
__maybe_unused
static const struct intel_device_info xehpsdv_info = {
XE_HP_FEATURES,
XE_HPM_FEATURES,
DGFX_FEATURES,
PLATFORM(INTEL_XEHPSDV),
.display = { },
.pipe_mask = 0,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
BIT(VECS0) | BIT(VECS1) |
BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3),
.require_force_probe = 1,
};
__maybe_unused
static const struct intel_device_info dg2_info = {
XE_HP_FEATURES,
XE_HPM_FEATURES,
XE_LPD_FEATURES,
DGFX_FEATURES,
.graphics_rel = 55,
.media_rel = 55,
PLATFORM(INTEL_DG2),
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
BIT(VECS0) | BIT(VECS1) |
BIT(VCS0) | BIT(VCS2),
.require_force_probe = 1,
};
#undef PLATFORM
/*

2
drivers/gpu/drm/i915/intel_device_info.c
View File

@@ -68,6 +68,8 @@ static const char * const platform_names[] = {
PLATFORM_NAME(DG1),
PLATFORM_NAME(ALDERLAKE_S),
PLATFORM_NAME(ALDERLAKE_P),
PLATFORM_NAME(XEHPSDV),
PLATFORM_NAME(DG2),
};
#undef PLATFORM_NAME

6
drivers/gpu/drm/i915/intel_device_info.h
View File

@@ -88,6 +88,8 @@ enum intel_platform {
INTEL_DG1,
INTEL_ALDERLAKE_S,
INTEL_ALDERLAKE_P,
INTEL_XEHPSDV,
INTEL_DG2,
INTEL_MAX_PLATFORMS
};
@@ -106,6 +108,10 @@ enum intel_platform {
/* CNL/ICL */
#define INTEL_SUBPLATFORM_PORTF (0)
/* DG2 */
#define INTEL_SUBPLATFORM_G10 0
#define INTEL_SUBPLATFORM_G11 1
enum intel_ppgtt_type {
INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,

30
drivers/gpu/drm/i915/intel_step.c
View File

@@ -101,6 +101,25 @@ static const struct intel_step_info adlp_revids[] = {
[0xC] = { .gt_step = STEP_C0, .display_step = STEP_D0 },
};
static const struct intel_step_info xehpsdv_revids[] = {
[0x0] = { .gt_step = STEP_A0 },
[0x1] = { .gt_step = STEP_A1 },
[0x4] = { .gt_step = STEP_B0 },
[0x8] = { .gt_step = STEP_C0 },
};
static const struct intel_step_info dg2_g10_revid_step_tbl[] = {
[0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
[0x1] = { .gt_step = STEP_A1, .display_step = STEP_A0 },
[0x4] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
[0x8] = { .gt_step = STEP_C0, .display_step = STEP_C0 },
};
static const struct intel_step_info dg2_g11_revid_step_tbl[] = {
[0x0] = { .gt_step = STEP_A0, .display_step = STEP_B0 },
[0x4] = { .gt_step = STEP_B0, .display_step = STEP_C0 },
};
void intel_step_init(struct drm_i915_private *i915)
{
const struct intel_step_info *revids = NULL;
@@ -108,7 +127,16 @@ void intel_step_init(struct drm_i915_private *i915)
int revid = INTEL_REVID(i915);
struct intel_step_info step = {};
if (IS_ALDERLAKE_P(i915)) {
if (IS_DG2_G10(i915)) {
revids = dg2_g10_revid_step_tbl;
size = ARRAY_SIZE(dg2_g10_revid_step_tbl);
} else if (IS_DG2_G11(i915)) {
revids = dg2_g11_revid_step_tbl;
size = ARRAY_SIZE(dg2_g11_revid_step_tbl);
} else if (IS_XEHPSDV(i915)) {
revids = xehpsdv_revids;
size = ARRAY_SIZE(xehpsdv_revids);
} else if (IS_ALDERLAKE_P(i915)) {
revids = adlp_revids;
size = ARRAY_SIZE(adlp_revids);
} else if (IS_ALDERLAKE_S(i915)) {