forked from Minki/linux
drm/amdgpu: bind GTT on demand
We don't really need the GTT table any more most of the time. So bind it only on demand. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
71c76a086f
commit
c855e25090
drivers/gpu/drm/amd/amdgpu
@ -2521,6 +2521,7 @@ static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
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struct amdgpu_bo_va_mapping *
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amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
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uint64_t addr, struct amdgpu_bo **bo);
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int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser);
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#include "amdgpu_object.h"
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#endif
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@ -639,8 +639,12 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
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}
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}
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if (p->uf_entry.robj)
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p->job->uf_addr += amdgpu_bo_gpu_offset(p->uf_entry.robj);
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if (!r && p->uf_entry.robj) {
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struct amdgpu_bo *uf = p->uf_entry.robj;
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r = amdgpu_ttm_bind(uf->tbo.ttm, &uf->tbo.mem);
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p->job->uf_addr += amdgpu_bo_gpu_offset(uf);
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}
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error_validate:
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if (r) {
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@ -1163,3 +1167,29 @@ amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
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return NULL;
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}
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/**
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* amdgpu_cs_sysvm_access_required - make BOs accessible by the system VM
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*
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* @parser: command submission parser context
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*
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* Helper for UVD/VCE VM emulation, make sure BOs are accessible by the system VM.
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*/
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int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser)
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{
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unsigned i;
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int r;
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if (!parser->bo_list)
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return 0;
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for (i = 0; i < parser->bo_list->num_entries; i++) {
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struct amdgpu_bo *bo = parser->bo_list->array[i].robj;
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r = amdgpu_ttm_bind(bo->tbo.ttm, &bo->tbo.mem);
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if (unlikely(r))
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return r;
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}
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return 0;
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}
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@ -675,6 +675,11 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
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dev_err(bo->adev->dev, "%p pin failed\n", bo);
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goto error;
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}
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r = amdgpu_ttm_bind(bo->tbo.ttm, &bo->tbo.mem);
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if (unlikely(r)) {
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dev_err(bo->adev->dev, "%p bind failed\n", bo);
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goto error;
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}
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bo->pin_count = 1;
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if (gpu_addr != NULL)
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@ -947,6 +952,8 @@ void amdgpu_bo_fence(struct amdgpu_bo *bo, struct fence *fence,
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u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
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{
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WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
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WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT &&
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!amdgpu_ttm_is_bound(bo->tbo.ttm));
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WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) &&
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!bo->pin_count);
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@ -256,8 +256,12 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo,
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new_start = new_mem->start << PAGE_SHIFT;
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switch (old_mem->mem_type) {
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case TTM_PL_VRAM:
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case TTM_PL_TT:
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r = amdgpu_ttm_bind(bo->ttm, old_mem);
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if (r)
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return r;
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case TTM_PL_VRAM:
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old_start += bo->bdev->man[old_mem->mem_type].gpu_offset;
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break;
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default:
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@ -265,8 +269,12 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo,
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return -EINVAL;
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}
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switch (new_mem->mem_type) {
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case TTM_PL_VRAM:
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case TTM_PL_TT:
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r = amdgpu_ttm_bind(bo->ttm, new_mem);
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if (r)
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return r;
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case TTM_PL_VRAM:
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new_start += bo->bdev->man[new_mem->mem_type].gpu_offset;
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break;
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default:
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@ -638,7 +646,6 @@ static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
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struct ttm_mem_reg *bo_mem)
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{
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struct amdgpu_ttm_tt *gtt = (void*)ttm;
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uint32_t flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
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int r;
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if (gtt->userptr) {
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@ -659,6 +666,26 @@ static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
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bo_mem->mem_type == AMDGPU_PL_OA)
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return -EINVAL;
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return 0;
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}
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bool amdgpu_ttm_is_bound(struct ttm_tt *ttm)
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{
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struct amdgpu_ttm_tt *gtt = (void *)ttm;
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return gtt && !list_empty(>t->list);
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}
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int amdgpu_ttm_bind(struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem)
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{
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struct amdgpu_ttm_tt *gtt = (void *)ttm;
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uint32_t flags;
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int r;
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if (!ttm || amdgpu_ttm_is_bound(ttm))
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return 0;
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flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
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r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
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ttm->pages, gtt->ttm.dma_address, flags);
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@ -77,4 +77,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
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struct fence **fence);
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int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
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bool amdgpu_ttm_is_bound(struct ttm_tt *ttm);
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int amdgpu_ttm_bind(struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem);
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#endif
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@ -882,6 +882,10 @@ int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
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return -EINVAL;
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}
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r = amdgpu_cs_sysvm_access_required(parser);
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if (r)
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return r;
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ctx.parser = parser;
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ctx.buf_sizes = buf_sizes;
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ctx.ib_idx = ib_idx;
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@ -634,7 +634,11 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
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uint32_t allocated = 0;
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uint32_t tmp, handle = 0;
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uint32_t *size = &tmp;
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int i, r = 0, idx = 0;
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int i, r, idx = 0;
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r = amdgpu_cs_sysvm_access_required(p);
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if (r)
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return r;
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while (idx < ib->length_dw) {
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uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
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@ -1163,7 +1163,8 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
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}
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flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem);
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gtt_flags = (adev == bo_va->bo->adev) ? flags : 0;
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gtt_flags = (amdgpu_ttm_is_bound(bo_va->bo->tbo.ttm) &&
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adev == bo_va->bo->adev) ? flags : 0;
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spin_lock(&vm->status_lock);
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if (!list_empty(&bo_va->vm_status))
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