arm64: dts: qcom: msm8992: Fix SDHCI1
This commit ensures the correct IRQ type is set and disables the device by default. The mmc-hs400-1_8v property is also moved to Bullhead as it might not be present on all boards. The node has been renamed to sdhci@ instead of mmc@ and the phandle was changed to sdhc_1 to comply with the newer DTS style. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-3-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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@ -271,3 +271,9 @@
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&sdhc_1 {
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status = "okay";
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mmc-hs400-1_8v;
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};
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@ -158,18 +158,19 @@
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sdhci1: mmc@f9824900 {
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sdhc_1: sdhci@f9824900 {
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compatible = "qcom,sdhci-msm-v4";
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compatible = "qcom,sdhci-msm-v4";
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reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
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reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
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reg-names = "hc_mem", "core_mem";
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reg-names = "hc_mem", "core_mem";
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interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>,
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 138 IRQ_TYPE_NONE>;
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hc_irq", "pwr_irq";
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC1_APPS_CLK>,
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clocks = <&gcc GCC_SDCC1_APPS_CLK>,
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<&gcc GCC_SDCC1_AHB_CLK>;
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<&gcc GCC_SDCC1_AHB_CLK>,
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clock-names = "core", "iface";
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<&xo_board>;
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clock-names = "core", "iface", "xo";
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pinctrl-names = "default", "sleep";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
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pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
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@ -179,8 +180,9 @@
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regulator-always-on;
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regulator-always-on;
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bus-width = <8>;
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bus-width = <8>;
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mmc-hs400-1_8v;
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non-removable;
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status = "okay";
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status = "disabled";
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};
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};
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blsp1_uart2: serial@f991e000 {
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blsp1_uart2: serial@f991e000 {
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