forked from Minki/linux
brcm80211: smac: use bcma core access functions in aiutils.c
The code in aiutils.c now uses the BCMA function for control the registers in the device cores. Reviewed-by: Pieter-Paul Giesberts <pieterpg@broadcom.com> Reviewed-by: Alwin Beukers <alwin@broadcom.com> Signed-off-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: Franky Lin <frankyl@broadcom.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Arend van Spriel
John W. Linville
parent
8d30b708b8
commit
c808674521
@ -558,28 +558,26 @@ static bool ai_buscore_prep(struct si_info *sii)
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}
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static bool
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ai_buscore_setup(struct si_info *sii, u32 savewin, uint *origidx)
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ai_buscore_setup(struct si_info *sii, struct bcma_device *cc)
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{
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bool pci, pcie;
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uint i;
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uint pciidx, pcieidx, pcirev, pcierev;
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struct chipcregs __iomem *cc;
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cc = ai_setcoreidx(&sii->pub, SI_CC_IDX);
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/* get chipcommon rev */
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sii->pub.ccrev = (int)ai_corerev(&sii->pub);
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sii->pub.ccrev = cc->id.rev;
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/* get chipcommon chipstatus */
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if (ai_get_ccrev(&sii->pub) >= 11)
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sii->chipst = R_REG(&cc->chipstatus);
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sii->chipst = bcma_read32(cc, CHIPCREGOFFS(chipstatus));
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/* get chipcommon capabilites */
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sii->pub.cccaps = R_REG(&cc->capabilities);
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sii->pub.cccaps = bcma_read32(cc, CHIPCREGOFFS(capabilities));
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/* get pmu rev and caps */
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if (ai_get_cccaps(&sii->pub) & CC_CAP_PMU) {
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sii->pub.pmucaps = R_REG(&cc->pmucapabilities);
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sii->pub.pmucaps = bcma_read32(cc,
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CHIPCREGOFFS(pmucapabilities));
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sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK;
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}
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@ -608,11 +606,6 @@ ai_buscore_setup(struct si_info *sii, u32 savewin, uint *origidx)
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pcierev = crev;
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pcie = true;
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}
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/* find the core idx before entering this func. */
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if ((savewin && (savewin == sii->coresba[i])) ||
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(cc == sii->regs[i]))
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*origidx = i;
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}
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if (pci && pcie) {
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@ -642,9 +635,6 @@ ai_buscore_setup(struct si_info *sii, u32 savewin, uint *origidx)
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return false;
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}
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/* return to the original core */
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ai_setcoreidx(&sii->pub, *origidx);
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return true;
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}
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@ -668,9 +658,8 @@ static struct si_info *ai_doattach(struct si_info *sii,
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void __iomem *regs = pbus->mmio;
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struct si_pub *sih = &sii->pub;
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u32 w, savewin;
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struct chipcregs __iomem *cc;
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struct bcma_device *cc;
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uint socitype;
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uint origidx;
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memset((unsigned char *) sii, 0, sizeof(struct si_info));
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@ -683,10 +672,7 @@ static struct si_info *ai_doattach(struct si_info *sii,
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sii->curwrap = sii->curmap + SI_CORE_SIZE;
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/* switch to Chipcommon core */
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bcma_read32(pbus->drv_cc.core, 0);
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savewin = SI_ENUM_BASE;
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cc = (struct chipcregs __iomem *) regs;
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cc = pbus->drv_cc.core;
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/* bus/core/clk setup for register access */
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if (!ai_buscore_prep(sii))
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@ -699,7 +685,7 @@ static struct si_info *ai_doattach(struct si_info *sii,
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* hosts w/o chipcommon), some way of recognizing them needs to
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* be added here.
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*/
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w = R_REG(&cc->chipid);
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w = bcma_read32(cc, CHIPCREGOFFS(chipid));
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socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
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/* Might as wll fill in chip id rev & pkg */
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sih->chip = w & CID_ID_MASK;
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@ -720,8 +706,7 @@ static struct si_info *ai_doattach(struct si_info *sii,
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return NULL;
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/* bus/core/clk setup */
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origidx = SI_CC_IDX;
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if (!ai_buscore_setup(sii, savewin, &origidx))
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if (!ai_buscore_setup(sii, cc))
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goto exit;
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/* Init nvram from sprom/otp if they exist */
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@ -731,10 +716,8 @@ static struct si_info *ai_doattach(struct si_info *sii,
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ai_nvram_process(sii);
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/* === NVRAM, clock is ready === */
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cc = (struct chipcregs __iomem *) ai_setcore(sih, CC_CORE_ID, 0);
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W_REG(&cc->gpiopullup, 0);
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W_REG(&cc->gpiopulldown, 0);
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ai_setcoreidx(sih, origidx);
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bcma_write32(cc, CHIPCREGOFFS(gpiopullup), 0);
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bcma_write32(cc, CHIPCREGOFFS(gpiopulldown), 0);
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/* PMU specific initializations */
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if (ai_get_cccaps(sih) & CC_CAP_PMU) {
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@ -990,11 +973,12 @@ uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val)
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}
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/* return the slow clock source - LPO, XTAL, or PCI */
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static uint ai_slowclk_src(struct si_info *sii)
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static uint ai_slowclk_src(struct si_pub *sih, struct bcma_device *cc)
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{
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struct chipcregs __iomem *cc;
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struct si_info *sii;
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u32 val;
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sii = (struct si_info *)sih;
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if (ai_get_ccrev(&sii->pub) < 6) {
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pci_read_config_dword(sii->pcibus, PCI_GPIO_OUT,
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&val);
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@ -1002,9 +986,8 @@ static uint ai_slowclk_src(struct si_info *sii)
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return SCC_SS_PCI;
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return SCC_SS_XTAL;
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} else if (ai_get_ccrev(&sii->pub) < 10) {
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cc = (struct chipcregs __iomem *)
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ai_setcoreidx(&sii->pub, sii->curidx);
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return R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK;
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return bcma_read32(cc, CHIPCREGOFFS(slow_clk_ctl)) &
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SCC_SS_MASK;
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} else /* Insta-clock */
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return SCC_SS_XTAL;
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}
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@ -1013,24 +996,24 @@ static uint ai_slowclk_src(struct si_info *sii)
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* return the ILP (slowclock) min or max frequency
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* precondition: we've established the chip has dynamic clk control
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*/
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static uint ai_slowclk_freq(struct si_info *sii, bool max_freq,
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struct chipcregs __iomem *cc)
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static uint ai_slowclk_freq(struct si_pub *sih, bool max_freq,
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struct bcma_device *cc)
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{
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u32 slowclk;
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uint div;
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slowclk = ai_slowclk_src(sii);
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if (ai_get_ccrev(&sii->pub) < 6) {
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slowclk = ai_slowclk_src(sih, cc);
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if (ai_get_ccrev(sih) < 6) {
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if (slowclk == SCC_SS_PCI)
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return max_freq ? (PCIMAXFREQ / 64)
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: (PCIMINFREQ / 64);
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else
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return max_freq ? (XTALMAXFREQ / 32)
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: (XTALMINFREQ / 32);
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} else if (ai_get_ccrev(&sii->pub) < 10) {
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} else if (ai_get_ccrev(sih) < 10) {
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div = 4 *
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(((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >>
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SCC_CD_SHIFT) + 1);
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(((bcma_read32(cc, CHIPCREGOFFS(slow_clk_ctl)) &
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SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
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if (slowclk == SCC_SS_LPO)
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return max_freq ? LPOMAXFREQ : LPOMINFREQ;
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else if (slowclk == SCC_SS_XTAL)
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@ -1041,15 +1024,15 @@ static uint ai_slowclk_freq(struct si_info *sii, bool max_freq,
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: (PCIMINFREQ / div);
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} else {
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/* Chipc rev 10 is InstaClock */
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div = R_REG(&cc->system_clk_ctl) >> SYCC_CD_SHIFT;
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div = 4 * (div + 1);
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div = bcma_read32(cc, CHIPCREGOFFS(system_clk_ctl));
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div = 4 * ((div >> SYCC_CD_SHIFT) + 1);
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return max_freq ? XTALMAXFREQ : (XTALMINFREQ / div);
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}
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return 0;
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}
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static void
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ai_clkctl_setdelay(struct si_info *sii, struct chipcregs __iomem *cc)
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ai_clkctl_setdelay(struct si_pub *sih, struct bcma_device *cc)
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{
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uint slowmaxfreq, pll_delay, slowclk;
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uint pll_on_delay, fref_sel_delay;
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@ -1062,47 +1045,40 @@ ai_clkctl_setdelay(struct si_info *sii, struct chipcregs __iomem *cc)
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* powered down by dynamic clk control logic.
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*/
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slowclk = ai_slowclk_src(sii);
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slowclk = ai_slowclk_src(sih, cc);
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if (slowclk != SCC_SS_XTAL)
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pll_delay += XTAL_ON_DELAY;
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/* Starting with 4318 it is ILP that is used for the delays */
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slowmaxfreq =
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ai_slowclk_freq(sii,
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(ai_get_ccrev(&sii->pub) >= 10) ? false : true, cc);
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ai_slowclk_freq(sih,
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(ai_get_ccrev(sih) >= 10) ? false : true, cc);
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pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
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fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
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W_REG(&cc->pll_on_delay, pll_on_delay);
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W_REG(&cc->fref_sel_delay, fref_sel_delay);
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bcma_write32(cc, CHIPCREGOFFS(pll_on_delay), pll_on_delay);
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bcma_write32(cc, CHIPCREGOFFS(fref_sel_delay), fref_sel_delay);
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}
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/* initialize power control delay registers */
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void ai_clkctl_init(struct si_pub *sih)
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{
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struct si_info *sii;
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uint origidx = 0;
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struct chipcregs __iomem *cc;
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struct bcma_device *cc;
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if (!(ai_get_cccaps(sih) & CC_CAP_PWR_CTL))
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return;
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sii = (struct si_info *)sih;
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origidx = sii->curidx;
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cc = (struct chipcregs __iomem *)
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ai_setcore(sih, CC_CORE_ID, 0);
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cc = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
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if (cc == NULL)
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return;
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/* set all Instaclk chip ILP to 1 MHz */
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if (ai_get_ccrev(sih) >= 10)
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SET_REG(&cc->system_clk_ctl, SYCC_CD_MASK,
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bcma_maskset32(cc, CHIPCREGOFFS(system_clk_ctl), SYCC_CD_MASK,
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(ILP_DIV_1MHZ << SYCC_CD_SHIFT));
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ai_clkctl_setdelay(sii, cc);
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ai_setcoreidx(sih, origidx);
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ai_clkctl_setdelay(sih, cc);
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}
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/*
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@ -1112,8 +1088,7 @@ void ai_clkctl_init(struct si_pub *sih)
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u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih)
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{
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struct si_info *sii;
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uint origidx = 0;
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struct chipcregs __iomem *cc;
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struct bcma_device *cc;
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uint slowminfreq;
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u16 fpdelay;
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uint intr_val = 0;
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@ -1130,19 +1105,17 @@ u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih)
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return 0;
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fpdelay = 0;
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origidx = sii->curidx;
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INTR_OFF(sii, intr_val);
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cc = (struct chipcregs __iomem *)
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ai_setcore(sih, CC_CORE_ID, 0);
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cc = ai_findcore(sih, CC_CORE_ID, 0);
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if (cc == NULL)
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goto done;
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slowminfreq = ai_slowclk_freq(sii, false, cc);
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fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) +
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(slowminfreq - 1)) / slowminfreq;
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slowminfreq = ai_slowclk_freq(sih, false, cc);
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fpdelay = (((bcma_read32(cc, CHIPCREGOFFS(pll_on_delay)) + 2) * 1000000)
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+ (slowminfreq - 1)) / slowminfreq;
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done:
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ai_setcoreidx(sih, origidx);
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INTR_RESTORE(sii, intr_val);
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return fpdelay;
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}
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@ -1213,8 +1186,7 @@ int ai_clkctl_xtal(struct si_pub *sih, uint what, bool on)
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/* clk control mechanism through chipcommon, no policy checking */
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static bool _ai_clkctl_cc(struct si_info *sii, uint mode)
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{
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uint origidx = 0;
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struct chipcregs __iomem *cc;
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struct bcma_device *cc;
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u32 scc;
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uint intr_val = 0;
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@ -1223,9 +1195,7 @@ static bool _ai_clkctl_cc(struct si_info *sii, uint mode)
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return false;
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INTR_OFF(sii, intr_val);
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origidx = sii->curidx;
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cc = (struct chipcregs __iomem *)
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ai_setcore(&sii->pub, CC_CORE_ID, 0);
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cc = ai_findcore(&sii->pub, BCMA_CORE_CHIPCOMMON, 0);
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if (!(ai_get_cccaps(&sii->pub) & CC_CAP_PWR_CTL) &&
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(ai_get_ccrev(&sii->pub) < 20))
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@ -1239,19 +1209,19 @@ static bool _ai_clkctl_cc(struct si_info *sii, uint mode)
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* on before we clear SCC_DYN_XTAL..
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*/
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ai_clkctl_xtal(&sii->pub, XTAL, ON);
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SET_REG(&cc->slow_clk_ctl,
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bcma_maskset32(cc, CHIPCREGOFFS(slow_clk_ctl),
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(SCC_XC | SCC_FS | SCC_IP), SCC_IP);
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} else if (ai_get_ccrev(&sii->pub) < 20) {
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OR_REG(&cc->system_clk_ctl, SYCC_HR);
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bcma_set32(cc, CHIPCREGOFFS(system_clk_ctl), SYCC_HR);
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} else {
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OR_REG(&cc->clk_ctl_st, CCS_FORCEHT);
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bcma_set32(cc, CHIPCREGOFFS(clk_ctl_st), CCS_FORCEHT);
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}
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/* wait for the PLL */
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if (ai_get_cccaps(&sii->pub) & CC_CAP_PMU) {
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u32 htavail = CCS_HTAVAIL;
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SPINWAIT(((R_REG(&cc->clk_ctl_st) & htavail)
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== 0), PMU_MAX_TRANSITION_DLY);
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SPINWAIT(((bcma_read32(cc, CHIPCREGOFFS(clk_ctl_st)) &
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htavail) == 0), PMU_MAX_TRANSITION_DLY);
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} else {
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udelay(PLL_DELAY);
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}
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@ -1259,11 +1229,11 @@ static bool _ai_clkctl_cc(struct si_info *sii, uint mode)
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case CLK_DYNAMIC: /* enable dynamic clock control */
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if (ai_get_ccrev(&sii->pub) < 10) {
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scc = R_REG(&cc->slow_clk_ctl);
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scc = bcma_read32(cc, CHIPCREGOFFS(slow_clk_ctl));
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scc &= ~(SCC_FS | SCC_IP | SCC_XC);
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if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
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scc |= SCC_XC;
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W_REG(&cc->slow_clk_ctl, scc);
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bcma_write32(cc, CHIPCREGOFFS(slow_clk_ctl), scc);
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/*
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* for dynamic control, we have to
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@ -1273,9 +1243,9 @@ static bool _ai_clkctl_cc(struct si_info *sii, uint mode)
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ai_clkctl_xtal(&sii->pub, XTAL, OFF);
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} else if (ai_get_ccrev(&sii->pub) < 20) {
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/* Instaclock */
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AND_REG(&cc->system_clk_ctl, ~SYCC_HR);
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bcma_mask32(cc, CHIPCREGOFFS(system_clk_ctl), ~SYCC_HR);
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} else {
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AND_REG(&cc->clk_ctl_st, ~CCS_FORCEHT);
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bcma_mask32(cc, CHIPCREGOFFS(clk_ctl_st), ~CCS_FORCEHT);
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}
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break;
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@ -1284,7 +1254,6 @@ static bool _ai_clkctl_cc(struct si_info *sii, uint mode)
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}
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done:
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ai_setcoreidx(&sii->pub, origidx);
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INTR_RESTORE(sii, intr_val);
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return mode == CLK_FAST;
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}
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@ -1427,53 +1396,37 @@ u32 ai_gpiocontrol(struct si_pub *sih, u32 mask, u32 val, u8 priority)
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void ai_chipcontrl_epa4331(struct si_pub *sih, bool on)
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{
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struct si_info *sii;
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struct chipcregs __iomem *cc;
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uint origidx;
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struct bcma_device *cc;
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u32 val;
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sii = (struct si_info *)sih;
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origidx = ai_coreidx(sih);
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cc = (struct chipcregs __iomem *) ai_setcore(sih, CC_CORE_ID, 0);
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val = R_REG(&cc->chipcontrol);
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cc = ai_findcore(sih, CC_CORE_ID, 0);
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if (on) {
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if (ai_get_chippkg(sih) == 9 || ai_get_chippkg(sih) == 0xb)
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/* Ext PA Controls for 4331 12x9 Package */
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W_REG(&cc->chipcontrol, val |
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bcma_set32(cc, CHIPCREGOFFS(chipcontrol),
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CCTRL4331_EXTPA_EN |
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CCTRL4331_EXTPA_ON_GPIO2_5);
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else
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/* Ext PA Controls for 4331 12x12 Package */
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W_REG(&cc->chipcontrol,
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val | CCTRL4331_EXTPA_EN);
|
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bcma_set32(cc, CHIPCREGOFFS(chipcontrol),
|
||||
CCTRL4331_EXTPA_EN);
|
||||
} else {
|
||||
val &= ~(CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_ON_GPIO2_5);
|
||||
W_REG(&cc->chipcontrol, val);
|
||||
bcma_mask32(cc, CHIPCREGOFFS(chipcontrol),
|
||||
~(CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_ON_GPIO2_5));
|
||||
}
|
||||
|
||||
ai_setcoreidx(sih, origidx);
|
||||
}
|
||||
|
||||
/* Enable BT-COEX & Ex-PA for 4313 */
|
||||
void ai_epa_4313war(struct si_pub *sih)
|
||||
{
|
||||
struct si_info *sii;
|
||||
struct chipcregs __iomem *cc;
|
||||
uint origidx;
|
||||
struct bcma_device *cc;
|
||||
|
||||
sii = (struct si_info *)sih;
|
||||
origidx = ai_coreidx(sih);
|
||||
|
||||
cc = ai_setcore(sih, CC_CORE_ID, 0);
|
||||
cc = ai_findcore(sih, CC_CORE_ID, 0);
|
||||
|
||||
/* EPA Fix */
|
||||
W_REG(&cc->gpiocontrol,
|
||||
R_REG(&cc->gpiocontrol) | GPIO_CTRL_EPA_EN_MASK);
|
||||
|
||||
ai_setcoreidx(sih, origidx);
|
||||
bcma_set32(cc, CHIPCREGOFFS(gpiocontrol), GPIO_CTRL_EPA_EN_MASK);
|
||||
}
|
||||
|
||||
/* check if the device is removed */
|
||||
@ -1496,17 +1449,14 @@ bool ai_is_sprom_available(struct si_pub *sih)
|
||||
struct si_info *sii = (struct si_info *)sih;
|
||||
|
||||
if (ai_get_ccrev(sih) >= 31) {
|
||||
uint origidx;
|
||||
struct chipcregs __iomem *cc;
|
||||
struct bcma_device *cc;
|
||||
u32 sromctrl;
|
||||
|
||||
if ((ai_get_cccaps(sih) & CC_CAP_SROM) == 0)
|
||||
return false;
|
||||
|
||||
origidx = sii->curidx;
|
||||
cc = ai_setcoreidx(sih, SI_CC_IDX);
|
||||
sromctrl = R_REG(&cc->sromcontrol);
|
||||
ai_setcoreidx(sih, origidx);
|
||||
cc = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
|
||||
sromctrl = bcma_read32(cc, CHIPCREGOFFS(sromcontrol));
|
||||
return sromctrl & SRC_PRESENT;
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user