Merge branch 'x86/urgent' into core/efi, to pick up a pending EFI fix
Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Ingo Molnar
@@ -16,6 +16,7 @@
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#ifndef __ASM_PGTABLE_H
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#define __ASM_PGTABLE_H
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#include <asm/bug.h>
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#include <asm/proc-fns.h>
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#include <asm/memory.h>
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@@ -25,9 +26,9 @@
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* Software defined PTE bits definition.
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*/
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#define PTE_VALID (_AT(pteval_t, 1) << 0)
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#define PTE_WRITE (PTE_DBM) /* same as DBM (51) */
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#define PTE_DIRTY (_AT(pteval_t, 1) << 55)
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#define PTE_SPECIAL (_AT(pteval_t, 1) << 56)
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#define PTE_WRITE (_AT(pteval_t, 1) << 57)
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#define PTE_PROT_NONE (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */
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/*
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@@ -48,18 +49,16 @@
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#define FIRST_USER_ADDRESS 0UL
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#ifndef __ASSEMBLY__
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#include <linux/mmdebug.h>
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extern void __pte_error(const char *file, int line, unsigned long val);
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extern void __pmd_error(const char *file, int line, unsigned long val);
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extern void __pud_error(const char *file, int line, unsigned long val);
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extern void __pgd_error(const char *file, int line, unsigned long val);
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#ifdef CONFIG_SMP
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#define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
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#define PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)
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#else
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#define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF)
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#define PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF)
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#endif
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#define PROT_DEVICE_nGnRnE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRnE))
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#define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE))
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@@ -82,7 +81,7 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
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#define PAGE_S2 __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY)
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#define PAGE_S2_DEVICE __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_UXN)
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#define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_TYPE_MASK) | PTE_PROT_NONE | PTE_PXN | PTE_UXN)
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#define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_PXN | PTE_UXN)
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#define PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
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#define PAGE_SHARED_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE)
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#define PAGE_COPY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
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@@ -139,12 +138,20 @@ extern struct page *empty_zero_page;
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* The following only work if pte_present(). Undefined behaviour otherwise.
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*/
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#define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
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#define pte_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY))
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#define pte_young(pte) (!!(pte_val(pte) & PTE_AF))
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#define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL))
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#define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE))
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#define pte_exec(pte) (!(pte_val(pte) & PTE_UXN))
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#ifdef CONFIG_ARM64_HW_AFDBM
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#define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY))
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#else
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#define pte_hw_dirty(pte) (0)
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#endif
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#define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY))
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#define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte))
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#define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID))
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#define pte_valid_user(pte) \
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((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER))
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#define pte_valid_not_user(pte) \
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@@ -211,20 +218,49 @@ static inline void set_pte(pte_t *ptep, pte_t pte)
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}
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}
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struct mm_struct;
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struct vm_area_struct;
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extern void __sync_icache_dcache(pte_t pteval, unsigned long addr);
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/*
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* PTE bits configuration in the presence of hardware Dirty Bit Management
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* (PTE_WRITE == PTE_DBM):
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*
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* Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw)
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* 0 0 | 1 0 0
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* 0 1 | 1 1 0
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* 1 0 | 1 0 1
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* 1 1 | 0 1 x
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*
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* When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via
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* the page fault mechanism. Checking the dirty status of a pte becomes:
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*
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* PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY)
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*/
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static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep, pte_t pte)
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{
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if (pte_valid_user(pte)) {
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if (!pte_special(pte) && pte_exec(pte))
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__sync_icache_dcache(pte, addr);
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if (pte_dirty(pte) && pte_write(pte))
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if (pte_sw_dirty(pte) && pte_write(pte))
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pte_val(pte) &= ~PTE_RDONLY;
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else
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pte_val(pte) |= PTE_RDONLY;
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}
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/*
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* If the existing pte is valid, check for potential race with
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* hardware updates of the pte (ptep_set_access_flags safely changes
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* valid ptes without going through an invalid entry).
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*/
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if (IS_ENABLED(CONFIG_DEBUG_VM) && IS_ENABLED(CONFIG_ARM64_HW_AFDBM) &&
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pte_valid(*ptep)) {
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BUG_ON(!pte_young(pte));
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BUG_ON(pte_write(*ptep) && !pte_dirty(pte));
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}
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set_pte(ptep, pte);
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}
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@@ -462,7 +498,10 @@ static inline pud_t *pud_offset(pgd_t *pgd, unsigned long addr)
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static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
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{
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const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
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PTE_PROT_NONE | PTE_WRITE | PTE_TYPE_MASK;
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PTE_PROT_NONE | PTE_VALID | PTE_WRITE;
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/* preserve the hardware dirty information */
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if (pte_hw_dirty(pte))
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pte = pte_mkdirty(pte);
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pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
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return pte;
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}
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@@ -472,6 +511,101 @@ static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
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return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
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}
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#ifdef CONFIG_ARM64_HW_AFDBM
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/*
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* Atomic pte/pmd modifications.
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*/
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#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
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static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
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unsigned long address,
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pte_t *ptep)
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{
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pteval_t pteval;
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unsigned int tmp, res;
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asm volatile("// ptep_test_and_clear_young\n"
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" prfm pstl1strm, %2\n"
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"1: ldxr %0, %2\n"
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" ubfx %w3, %w0, %5, #1 // extract PTE_AF (young)\n"
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" and %0, %0, %4 // clear PTE_AF\n"
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" stxr %w1, %0, %2\n"
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" cbnz %w1, 1b\n"
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: "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)), "=&r" (res)
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: "L" (~PTE_AF), "I" (ilog2(PTE_AF)));
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return res;
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}
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
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static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
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unsigned long address,
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pmd_t *pmdp)
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{
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return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp);
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}
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#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
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#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
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static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
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unsigned long address, pte_t *ptep)
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{
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pteval_t old_pteval;
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unsigned int tmp;
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asm volatile("// ptep_get_and_clear\n"
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" prfm pstl1strm, %2\n"
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"1: ldxr %0, %2\n"
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" stxr %w1, xzr, %2\n"
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" cbnz %w1, 1b\n"
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: "=&r" (old_pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)));
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return __pte(old_pteval);
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}
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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#define __HAVE_ARCH_PMDP_GET_AND_CLEAR
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static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm,
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unsigned long address, pmd_t *pmdp)
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{
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return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp));
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}
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#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
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/*
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* ptep_set_wrprotect - mark read-only while trasferring potential hardware
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* dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit.
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*/
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#define __HAVE_ARCH_PTEP_SET_WRPROTECT
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static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
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{
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pteval_t pteval;
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unsigned long tmp;
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asm volatile("// ptep_set_wrprotect\n"
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" prfm pstl1strm, %2\n"
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"1: ldxr %0, %2\n"
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" tst %0, %4 // check for hw dirty (!PTE_RDONLY)\n"
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" csel %1, %3, xzr, eq // set PTE_DIRTY|PTE_RDONLY if dirty\n"
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" orr %0, %0, %1 // if !dirty, PTE_RDONLY is already set\n"
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" and %0, %0, %5 // clear PTE_WRITE/PTE_DBM\n"
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" stxr %w1, %0, %2\n"
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" cbnz %w1, 1b\n"
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: "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep))
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: "r" (PTE_DIRTY|PTE_RDONLY), "L" (PTE_RDONLY), "L" (~PTE_WRITE)
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: "cc");
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}
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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#define __HAVE_ARCH_PMDP_SET_WRPROTECT
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static inline void pmdp_set_wrprotect(struct mm_struct *mm,
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unsigned long address, pmd_t *pmdp)
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{
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ptep_set_wrprotect(mm, address, (pte_t *)pmdp);
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}
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#endif
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#endif /* CONFIG_ARM64_HW_AFDBM */
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extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
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extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
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@@ -507,6 +641,21 @@ extern int kern_addr_valid(unsigned long addr);
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#define pgtable_cache_init() do { } while (0)
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/*
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* On AArch64, the cache coherency is handled via the set_pte_at() function.
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*/
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static inline void update_mmu_cache(struct vm_area_struct *vma,
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unsigned long addr, pte_t *ptep)
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{
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/*
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* set_pte() does not have a DSB for user mappings, so make sure that
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* the page table write is visible.
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*/
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dsb(ishst);
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}
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#define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
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#endif /* !__ASSEMBLY__ */
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#endif /* __ASM_PGTABLE_H */
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