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ARM: imx: add low-level debug for vybrid

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Add low-level debug support for vybrid, so that earlyprintk can be
enabled for debugging early boot issue.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
Shawn Guo
2013-05-12 17:22:17 +08:00
parent 4c1dd3e5ed
commit c7c3eac627
2 changed files with 34 additions and 0 deletions
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8
arch/arm/Kconfig.debug
View File

@@ -386,6 +386,13 @@ choice
when u-boot hands over to the kernel, the system when u-boot hands over to the kernel, the system
silently crashes, with no serial output at all. silently crashes, with no serial output at all.
config DEBUG_VF_UART
bool "Vybrid UART"
depends on SOC_VF610
help
Say Y here if you want kernel low-level debugging support
on Vybrid based platforms.
config DEBUG_NOMADIK_UART config DEBUG_NOMADIK_UART
bool "Kernel low-level debugging messages via NOMADIK UART" bool "Kernel low-level debugging messages via NOMADIK UART"
depends on ARCH_NOMADIK depends on ARCH_NOMADIK
@@ -906,6 +913,7 @@ config DEBUG_LL_INCLUDE
default "debug/tegra.S" if DEBUG_TEGRA_UART default "debug/tegra.S" if DEBUG_TEGRA_UART
default "debug/ux500.S" if DEBUG_UX500_UART default "debug/ux500.S" if DEBUG_UX500_UART
default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT
default "debug/vf.S" if DEBUG_VF_UART
default "debug/vt8500.S" if DEBUG_VT8500_UART0 default "debug/vt8500.S" if DEBUG_VT8500_UART0
default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1 default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1
default "mach/debug-macro.S" default "mach/debug-macro.S"

26
arch/arm/include/debug/vf.S Normal file
View File

@@ -0,0 +1,26 @@
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
.macro addruart, rp, rv, tmp
ldr \rp, =0x40028000 @ physical
ldr \rv, =0xfe028000 @ virtual
.endm
.macro senduart, rd, rx
strb \rd, [\rx, #0x7] @ Data Register
.endm
.macro busyuart, rd, rx
1001: ldrb \rd, [\rx, #0x4] @ Status Register 1
tst \rd, #1 << 6 @ TC
beq 1001b @ wait until transmit done
.endm
.macro waituart,rd,rx
.endm