forked from Minki/linux
mfd: max14577: Add MAX14577 prefix to IRQ defines
This patch prepares for adding support for MAX77836 device to existing max14577 driver by adding MAX14577 prefix to defines of interrupts. This is only a rename-like patch, new code is not added. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
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@ -66,20 +66,20 @@ static const struct regmap_config max14577_muic_regmap_config = {
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static const struct regmap_irq max14577_irqs[] = {
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/* INT1 interrupts */
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{ .reg_offset = 0, .mask = INT1_ADC_MASK, },
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{ .reg_offset = 0, .mask = INT1_ADCLOW_MASK, },
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{ .reg_offset = 0, .mask = INT1_ADCERR_MASK, },
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{ .reg_offset = 0, .mask = MAX14577_INT1_ADC_MASK, },
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{ .reg_offset = 0, .mask = MAX14577_INT1_ADCLOW_MASK, },
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{ .reg_offset = 0, .mask = MAX14577_INT1_ADCERR_MASK, },
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/* INT2 interrupts */
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{ .reg_offset = 1, .mask = INT2_CHGTYP_MASK, },
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{ .reg_offset = 1, .mask = INT2_CHGDETRUN_MASK, },
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{ .reg_offset = 1, .mask = INT2_DCDTMR_MASK, },
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{ .reg_offset = 1, .mask = INT2_DBCHG_MASK, },
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{ .reg_offset = 1, .mask = INT2_VBVOLT_MASK, },
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{ .reg_offset = 1, .mask = MAX14577_INT2_CHGTYP_MASK, },
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{ .reg_offset = 1, .mask = MAX14577_INT2_CHGDETRUN_MASK, },
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{ .reg_offset = 1, .mask = MAX14577_INT2_DCDTMR_MASK, },
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{ .reg_offset = 1, .mask = MAX14577_INT2_DBCHG_MASK, },
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{ .reg_offset = 1, .mask = MAX14577_INT2_VBVOLT_MASK, },
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/* INT3 interrupts */
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{ .reg_offset = 2, .mask = INT3_EOC_MASK, },
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{ .reg_offset = 2, .mask = INT3_CGMBC_MASK, },
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{ .reg_offset = 2, .mask = INT3_OVP_MASK, },
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{ .reg_offset = 2, .mask = INT3_MBCCHGERR_MASK, },
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{ .reg_offset = 2, .mask = MAX14577_INT3_EOC_MASK, },
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{ .reg_offset = 2, .mask = MAX14577_INT3_CGMBC_MASK, },
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{ .reg_offset = 2, .mask = MAX14577_INT3_OVP_MASK, },
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{ .reg_offset = 2, .mask = MAX14577_INT3_MBCCHGERR_MASK, },
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};
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static const struct regmap_irq_chip max14577_irq_chip = {
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@ -79,20 +79,20 @@ enum max14577_muic_charger_type {
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};
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/* MAX14577 interrupts */
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#define INT1_ADC_MASK (0x1 << 0)
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#define INT1_ADCLOW_MASK (0x1 << 1)
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#define INT1_ADCERR_MASK (0x1 << 2)
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#define MAX14577_INT1_ADC_MASK BIT(0)
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#define MAX14577_INT1_ADCLOW_MASK BIT(1)
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#define MAX14577_INT1_ADCERR_MASK BIT(2)
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#define INT2_CHGTYP_MASK (0x1 << 0)
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#define INT2_CHGDETRUN_MASK (0x1 << 1)
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#define INT2_DCDTMR_MASK (0x1 << 2)
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#define INT2_DBCHG_MASK (0x1 << 3)
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#define INT2_VBVOLT_MASK (0x1 << 4)
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#define MAX14577_INT2_CHGTYP_MASK BIT(0)
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#define MAX14577_INT2_CHGDETRUN_MASK BIT(1)
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#define MAX14577_INT2_DCDTMR_MASK BIT(2)
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#define MAX14577_INT2_DBCHG_MASK BIT(3)
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#define MAX14577_INT2_VBVOLT_MASK BIT(4)
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#define INT3_EOC_MASK (0x1 << 0)
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#define INT3_CGMBC_MASK (0x1 << 1)
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#define INT3_OVP_MASK (0x1 << 2)
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#define INT3_MBCCHGERR_MASK (0x1 << 3)
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#define MAX14577_INT3_EOC_MASK BIT(0)
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#define MAX14577_INT3_CGMBC_MASK BIT(1)
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#define MAX14577_INT3_OVP_MASK BIT(2)
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#define MAX14577_INT3_MBCCHGERR_MASK BIT(3)
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/* MAX14577 DEVICE ID register */
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#define DEVID_VENDORID_SHIFT 0
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