ath9k: add dynamic ACK timeout estimation
Add dynamic ACK timeout estimation algorithm based on ACK frame RX timestamp, TX frame timestamp and frame duration. Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi83@gmail.com> Tested-by: Philippe Duchein <wireless-dev@duchein.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Lorenzo Bianconi
John W. Linville
parent
36678b2b67
commit
c774d57fd4
@ -234,6 +234,7 @@ void ath_printk(const char *level, const struct ath_common *common,
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* AR9462.
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* AR9462.
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* @ATH_DBG_DFS: radar datection
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* @ATH_DBG_DFS: radar datection
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* @ATH_DBG_WOW: Wake on Wireless
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* @ATH_DBG_WOW: Wake on Wireless
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* @ATH_DBG_DYNACK: dynack handling
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* @ATH_DBG_ANY: enable all debugging
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* @ATH_DBG_ANY: enable all debugging
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*
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*
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* The debug level is used to control the amount and type of debugging output
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* The debug level is used to control the amount and type of debugging output
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@ -262,6 +263,7 @@ enum ATH_DEBUG {
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ATH_DBG_DFS = 0x00010000,
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ATH_DBG_DFS = 0x00010000,
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ATH_DBG_WOW = 0x00020000,
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ATH_DBG_WOW = 0x00020000,
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ATH_DBG_CHAN_CTX = 0x00040000,
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ATH_DBG_CHAN_CTX = 0x00040000,
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ATH_DBG_DYNACK = 0x00080000,
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ATH_DBG_ANY = 0xffffffff
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ATH_DBG_ANY = 0xffffffff
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};
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};
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@ -274,6 +274,9 @@ struct ath_node {
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struct ath_rx_rate_stats rx_rate_stats;
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struct ath_rx_rate_stats rx_rate_stats;
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#endif
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#endif
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u8 key_idx[4];
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u8 key_idx[4];
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u32 ackto;
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struct list_head list;
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};
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};
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struct ath_tx_control {
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struct ath_tx_control {
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351
drivers/net/wireless/ath/ath9k/dynack.c
Normal file
351
drivers/net/wireless/ath/ath9k/dynack.c
Normal file
@ -0,0 +1,351 @@
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/*
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* Copyright (c) 2014, Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "ath9k.h"
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#include "hw.h"
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#include "dynack.h"
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#define COMPUTE_TO (5 * HZ)
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#define LATEACK_DELAY (10 * HZ)
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#define LATEACK_TO 256
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#define MAX_DELAY 300
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#define EWMA_LEVEL 96
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#define EWMA_DIV 128
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/**
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* ath_dynack_ewma - EWMA (Exponentially Weighted Moving Average) calculation
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*
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*/
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static inline u32 ath_dynack_ewma(u32 old, u32 new)
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{
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return (new * (EWMA_DIV - EWMA_LEVEL) + old * EWMA_LEVEL) / EWMA_DIV;
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}
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/**
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* ath_dynack_get_sifs - get sifs time based on phy used
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* @ah: ath hw
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* @phy: phy used
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*
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*/
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static inline u32 ath_dynack_get_sifs(struct ath_hw *ah, int phy)
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{
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u32 sifs = CCK_SIFS_TIME;
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if (phy == WLAN_RC_PHY_OFDM) {
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if (IS_CHAN_QUARTER_RATE(ah->curchan))
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sifs = OFDM_SIFS_TIME_QUARTER;
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else if (IS_CHAN_HALF_RATE(ah->curchan))
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sifs = OFDM_SIFS_TIME_HALF;
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else
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sifs = OFDM_SIFS_TIME;
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}
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return sifs;
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}
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/**
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* ath_dynack_bssidmask - filter out ACK frames based on BSSID mask
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* @ah: ath hw
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* @mac: receiver address
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*/
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static inline bool ath_dynack_bssidmask(struct ath_hw *ah, const u8 *mac)
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{
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int i;
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struct ath_common *common = ath9k_hw_common(ah);
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for (i = 0; i < ETH_ALEN; i++) {
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if ((common->macaddr[i] & common->bssidmask[i]) !=
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(mac[i] & common->bssidmask[i]))
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return false;
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}
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return true;
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}
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/**
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* ath_dynack_compute_ackto - compute ACK timeout as the maximum STA timeout
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* @ah: ath hw
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*
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* should be called while holding qlock
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*/
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static void ath_dynack_compute_ackto(struct ath_hw *ah)
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{
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struct ath_node *an;
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u32 to = 0;
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struct ath_dynack *da = &ah->dynack;
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struct ath_common *common = ath9k_hw_common(ah);
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list_for_each_entry(an, &da->nodes, list)
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if (an->ackto > to)
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to = an->ackto;
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if (to && da->ackto != to) {
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u32 slottime;
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slottime = (to - 3) / 2;
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da->ackto = to;
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ath_dbg(common, DYNACK, "ACK timeout %u slottime %u\n",
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da->ackto, slottime);
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ath9k_hw_setslottime(ah, slottime);
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ath9k_hw_set_ack_timeout(ah, da->ackto);
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ath9k_hw_set_cts_timeout(ah, da->ackto);
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}
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}
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/**
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* ath_dynack_compute_to - compute STA ACK timeout
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* @ah: ath hw
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*
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* should be called while holding qlock
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*/
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static void ath_dynack_compute_to(struct ath_hw *ah)
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{
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u32 ackto, ack_ts;
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u8 *dst, *src;
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struct ieee80211_sta *sta;
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struct ath_node *an;
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struct ts_info *st_ts;
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struct ath_dynack *da = &ah->dynack;
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rcu_read_lock();
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while (da->st_rbf.h_rb != da->st_rbf.t_rb &&
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da->ack_rbf.h_rb != da->ack_rbf.t_rb) {
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ack_ts = da->ack_rbf.tstamp[da->ack_rbf.h_rb];
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st_ts = &da->st_rbf.ts[da->st_rbf.h_rb];
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dst = da->st_rbf.addr[da->st_rbf.h_rb].h_dest;
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src = da->st_rbf.addr[da->st_rbf.h_rb].h_src;
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ath_dbg(ath9k_hw_common(ah), DYNACK,
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"ack_ts %u st_ts %u st_dur %u [%u-%u]\n",
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ack_ts, st_ts->tstamp, st_ts->dur,
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da->ack_rbf.h_rb, da->st_rbf.h_rb);
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if (ack_ts > st_ts->tstamp + st_ts->dur) {
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ackto = ack_ts - st_ts->tstamp - st_ts->dur;
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if (ackto < MAX_DELAY) {
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sta = ieee80211_find_sta_by_ifaddr(ah->hw, dst,
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src);
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if (sta) {
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an = (struct ath_node *)sta->drv_priv;
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an->ackto = ath_dynack_ewma(an->ackto,
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ackto);
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ath_dbg(ath9k_hw_common(ah), DYNACK,
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"%pM to %u\n", dst, an->ackto);
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if (time_is_before_jiffies(da->lto)) {
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ath_dynack_compute_ackto(ah);
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da->lto = jiffies + COMPUTE_TO;
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}
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}
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INCR(da->ack_rbf.h_rb, ATH_DYN_BUF);
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}
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INCR(da->st_rbf.h_rb, ATH_DYN_BUF);
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} else {
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INCR(da->ack_rbf.h_rb, ATH_DYN_BUF);
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}
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}
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rcu_read_unlock();
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}
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/**
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* ath_dynack_sample_tx_ts - status timestamp sampling method
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* @ah: ath hw
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* @skb: socket buffer
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* @ts: tx status info
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*
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*/
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void ath_dynack_sample_tx_ts(struct ath_hw *ah, struct sk_buff *skb,
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struct ath_tx_status *ts)
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{
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u8 ridx;
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struct ieee80211_hdr *hdr;
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struct ath_dynack *da = &ah->dynack;
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struct ath_common *common = ath9k_hw_common(ah);
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struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
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if ((info->flags & IEEE80211_TX_CTL_NO_ACK) || !da->enabled)
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return;
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spin_lock_bh(&da->qlock);
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hdr = (struct ieee80211_hdr *)skb->data;
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/* late ACK */
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if (ts->ts_status & ATH9K_TXERR_XRETRY) {
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if (ieee80211_is_assoc_req(hdr->frame_control) ||
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ieee80211_is_assoc_resp(hdr->frame_control)) {
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ath_dbg(common, DYNACK, "late ack\n");
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ath9k_hw_setslottime(ah, (LATEACK_TO - 3) / 2);
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ath9k_hw_set_ack_timeout(ah, LATEACK_TO);
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ath9k_hw_set_cts_timeout(ah, LATEACK_TO);
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da->lto = jiffies + LATEACK_DELAY;
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}
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spin_unlock_bh(&da->qlock);
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return;
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}
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ridx = ts->ts_rateindex;
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da->st_rbf.ts[da->st_rbf.t_rb].tstamp = ts->ts_tstamp;
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da->st_rbf.ts[da->st_rbf.t_rb].dur = ts->duration[ts->ts_rateindex];
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ether_addr_copy(da->st_rbf.addr[da->st_rbf.t_rb].h_dest, hdr->addr1);
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ether_addr_copy(da->st_rbf.addr[da->st_rbf.t_rb].h_src, hdr->addr2);
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if (!(info->status.rates[ridx].flags & IEEE80211_TX_RC_MCS)) {
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u32 phy, sifs;
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const struct ieee80211_rate *rate;
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struct ieee80211_tx_rate *rates = info->status.rates;
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rate = &common->sbands[info->band].bitrates[rates[ridx].idx];
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if (info->band == IEEE80211_BAND_2GHZ &&
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!(rate->flags & IEEE80211_RATE_ERP_G))
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phy = WLAN_RC_PHY_CCK;
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else
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phy = WLAN_RC_PHY_OFDM;
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sifs = ath_dynack_get_sifs(ah, phy);
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da->st_rbf.ts[da->st_rbf.t_rb].dur -= sifs;
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}
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ath_dbg(common, DYNACK, "{%pM} tx sample %u [dur %u][h %u-t %u]\n",
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hdr->addr1, da->st_rbf.ts[da->st_rbf.t_rb].tstamp,
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da->st_rbf.ts[da->st_rbf.t_rb].dur, da->st_rbf.h_rb,
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(da->st_rbf.t_rb + 1) % ATH_DYN_BUF);
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INCR(da->st_rbf.t_rb, ATH_DYN_BUF);
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if (da->st_rbf.t_rb == da->st_rbf.h_rb)
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INCR(da->st_rbf.h_rb, ATH_DYN_BUF);
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ath_dynack_compute_to(ah);
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spin_unlock_bh(&da->qlock);
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}
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EXPORT_SYMBOL(ath_dynack_sample_tx_ts);
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/**
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* ath_dynack_sample_ack_ts - ACK timestamp sampling method
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* @ah: ath hw
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* @skb: socket buffer
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* @ts: rx timestamp
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*
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*/
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void ath_dynack_sample_ack_ts(struct ath_hw *ah, struct sk_buff *skb,
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u32 ts)
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{
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struct ath_dynack *da = &ah->dynack;
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struct ath_common *common = ath9k_hw_common(ah);
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struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
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if (!ath_dynack_bssidmask(ah, hdr->addr1) || !da->enabled)
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return;
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spin_lock_bh(&da->qlock);
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da->ack_rbf.tstamp[da->ack_rbf.t_rb] = ts;
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ath_dbg(common, DYNACK, "rx sample %u [h %u-t %u]\n",
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da->ack_rbf.tstamp[da->ack_rbf.t_rb],
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da->ack_rbf.h_rb, (da->ack_rbf.t_rb + 1) % ATH_DYN_BUF);
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INCR(da->ack_rbf.t_rb, ATH_DYN_BUF);
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if (da->ack_rbf.t_rb == da->ack_rbf.h_rb)
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INCR(da->ack_rbf.h_rb, ATH_DYN_BUF);
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ath_dynack_compute_to(ah);
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spin_unlock_bh(&da->qlock);
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}
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EXPORT_SYMBOL(ath_dynack_sample_ack_ts);
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/**
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* ath_dynack_node_init - init ath_node related info
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* @ah: ath hw
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* @an: ath node
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*
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*/
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void ath_dynack_node_init(struct ath_hw *ah, struct ath_node *an)
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{
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/* ackto = slottime + sifs + air delay */
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u32 ackto = ATH9K_SLOT_TIME_9 + 16 + 64;
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struct ath_dynack *da = &ah->dynack;
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an->ackto = ackto;
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spin_lock(&da->qlock);
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list_add_tail(&an->list, &da->nodes);
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spin_unlock(&da->qlock);
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}
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EXPORT_SYMBOL(ath_dynack_node_init);
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/**
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* ath_dynack_node_deinit - deinit ath_node related info
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* @ah: ath hw
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* @an: ath node
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*
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*/
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void ath_dynack_node_deinit(struct ath_hw *ah, struct ath_node *an)
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{
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struct ath_dynack *da = &ah->dynack;
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spin_lock(&da->qlock);
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list_del(&an->list);
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spin_unlock(&da->qlock);
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}
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EXPORT_SYMBOL(ath_dynack_node_deinit);
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/**
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* ath_dynack_reset - reset dynack processing
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* @ah: ath hw
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*
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*/
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void ath_dynack_reset(struct ath_hw *ah)
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{
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/* ackto = slottime + sifs + air delay */
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u32 ackto = ATH9K_SLOT_TIME_9 + 16 + 64;
|
||||||
|
struct ath_dynack *da = &ah->dynack;
|
||||||
|
|
||||||
|
da->lto = jiffies;
|
||||||
|
da->ackto = ackto;
|
||||||
|
|
||||||
|
da->st_rbf.t_rb = 0;
|
||||||
|
da->st_rbf.h_rb = 0;
|
||||||
|
da->ack_rbf.t_rb = 0;
|
||||||
|
da->ack_rbf.h_rb = 0;
|
||||||
|
|
||||||
|
/* init acktimeout */
|
||||||
|
ath9k_hw_setslottime(ah, (ackto - 3) / 2);
|
||||||
|
ath9k_hw_set_ack_timeout(ah, ackto);
|
||||||
|
ath9k_hw_set_cts_timeout(ah, ackto);
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL(ath_dynack_reset);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* ath_dynack_init - init dynack data structure
|
||||||
|
* @ah: ath hw
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void ath_dynack_init(struct ath_hw *ah)
|
||||||
|
{
|
||||||
|
struct ath_dynack *da = &ah->dynack;
|
||||||
|
|
||||||
|
memset(da, 0, sizeof(struct ath_dynack));
|
||||||
|
|
||||||
|
spin_lock_init(&da->qlock);
|
||||||
|
INIT_LIST_HEAD(&da->nodes);
|
||||||
|
|
||||||
|
ah->hw->wiphy->features |= NL80211_FEATURE_ACKTO_ESTIMATION;
|
||||||
|
}
|
||||||
103
drivers/net/wireless/ath/ath9k/dynack.h
Normal file
103
drivers/net/wireless/ath/ath9k/dynack.h
Normal file
@ -0,0 +1,103 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2014, Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
|
||||||
|
*
|
||||||
|
* Permission to use, copy, modify, and/or distribute this software for any
|
||||||
|
* purpose with or without fee is hereby granted, provided that the above
|
||||||
|
* copyright notice and this permission notice appear in all copies.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||||
|
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||||
|
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||||
|
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||||
|
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||||
|
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||||
|
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef DYNACK_H
|
||||||
|
#define DYNACK_H
|
||||||
|
|
||||||
|
#define ATH_DYN_BUF 64
|
||||||
|
|
||||||
|
struct ath_hw;
|
||||||
|
struct ath_node;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* struct ath_dyn_rxbuf - ACK frame ring buffer
|
||||||
|
* @h_rb: ring buffer head
|
||||||
|
* @t_rb: ring buffer tail
|
||||||
|
* @tstamp: ACK RX timestamp buffer
|
||||||
|
*/
|
||||||
|
struct ath_dyn_rxbuf {
|
||||||
|
u16 h_rb, t_rb;
|
||||||
|
u32 tstamp[ATH_DYN_BUF];
|
||||||
|
};
|
||||||
|
|
||||||
|
struct ts_info {
|
||||||
|
u32 tstamp;
|
||||||
|
u32 dur;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct haddr_pair {
|
||||||
|
u8 h_dest[ETH_ALEN];
|
||||||
|
u8 h_src[ETH_ALEN];
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* struct ath_dyn_txbuf - tx frame ring buffer
|
||||||
|
* @h_rb: ring buffer head
|
||||||
|
* @t_rb: ring buffer tail
|
||||||
|
* @addr: dest/src address pair for a given TX frame
|
||||||
|
* @ts: TX frame timestamp buffer
|
||||||
|
*/
|
||||||
|
struct ath_dyn_txbuf {
|
||||||
|
u16 h_rb, t_rb;
|
||||||
|
struct haddr_pair addr[ATH_DYN_BUF];
|
||||||
|
struct ts_info ts[ATH_DYN_BUF];
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* struct ath_dynack - dynack processing info
|
||||||
|
* @enabled: enable dyn ack processing
|
||||||
|
* @ackto: current ACK timeout
|
||||||
|
* @lto: last ACK timeout computation
|
||||||
|
* @nodes: ath_node linked list
|
||||||
|
* @qlock: ts queue spinlock
|
||||||
|
* @ack_rbf: ACK ts ring buffer
|
||||||
|
* @st_rbf: status ts ring buffer
|
||||||
|
*/
|
||||||
|
struct ath_dynack {
|
||||||
|
bool enabled;
|
||||||
|
int ackto;
|
||||||
|
unsigned long lto;
|
||||||
|
|
||||||
|
struct list_head nodes;
|
||||||
|
|
||||||
|
/* protect timestamp queue access */
|
||||||
|
spinlock_t qlock;
|
||||||
|
struct ath_dyn_rxbuf ack_rbf;
|
||||||
|
struct ath_dyn_txbuf st_rbf;
|
||||||
|
};
|
||||||
|
|
||||||
|
#if defined(CONFIG_ATH9K_DYNACK)
|
||||||
|
void ath_dynack_reset(struct ath_hw *ah);
|
||||||
|
void ath_dynack_node_init(struct ath_hw *ah, struct ath_node *an);
|
||||||
|
void ath_dynack_node_deinit(struct ath_hw *ah, struct ath_node *an);
|
||||||
|
void ath_dynack_init(struct ath_hw *ah);
|
||||||
|
void ath_dynack_sample_ack_ts(struct ath_hw *ah, struct sk_buff *skb, u32 ts);
|
||||||
|
void ath_dynack_sample_tx_ts(struct ath_hw *ah, struct sk_buff *skb,
|
||||||
|
struct ath_tx_status *ts);
|
||||||
|
#else
|
||||||
|
static inline void ath_dynack_init(struct ath_hw *ah) {}
|
||||||
|
static inline void ath_dynack_node_init(struct ath_hw *ah,
|
||||||
|
struct ath_node *an) {}
|
||||||
|
static inline void ath_dynack_node_deinit(struct ath_hw *ah,
|
||||||
|
struct ath_node *an) {}
|
||||||
|
static inline void ath_dynack_sample_ack_ts(struct ath_hw *ah,
|
||||||
|
struct sk_buff *skb, u32 ts) {}
|
||||||
|
static inline void ath_dynack_sample_tx_ts(struct ath_hw *ah,
|
||||||
|
struct sk_buff *skb,
|
||||||
|
struct ath_tx_status *ts) {}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* DYNACK_H */
|
||||||
@ -647,6 +647,8 @@ int ath9k_hw_init(struct ath_hw *ah)
|
|||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
ath_dynack_init(ah);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
EXPORT_SYMBOL(ath9k_hw_init);
|
EXPORT_SYMBOL(ath9k_hw_init);
|
||||||
|
|||||||
@ -29,6 +29,7 @@
|
|||||||
#include "reg.h"
|
#include "reg.h"
|
||||||
#include "phy.h"
|
#include "phy.h"
|
||||||
#include "btcoex.h"
|
#include "btcoex.h"
|
||||||
|
#include "dynack.h"
|
||||||
|
|
||||||
#include "../regd.h"
|
#include "../regd.h"
|
||||||
|
|
||||||
@ -924,6 +925,8 @@ struct ath_hw {
|
|||||||
int (*external_reset)(void);
|
int (*external_reset)(void);
|
||||||
|
|
||||||
const struct firmware *eeprom_blob;
|
const struct firmware *eeprom_blob;
|
||||||
|
|
||||||
|
struct ath_dynack dynack;
|
||||||
};
|
};
|
||||||
|
|
||||||
struct ath_bus_ops {
|
struct ath_bus_ops {
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user