perf vendor events: Update events and metrics for cascadelakex
Update to v16, the metrics are based on TMA 4.4 full, update events and add new metrics “UNCORE_FREQ” for cascadelakex. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py to download and generate the latest events and metrics. Manually copy the cascadelakex files into perf. Signed-off-by: Xing Zhengjun <zhengjun.xing@linux.intel.com> Tested-by: Ian Rogers <irogers@google.com> Cc: Alexander Shishkin <alexander.shishkin@intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Ian Rogers <irogers@google.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Link: https://lore.kernel.org/r/20220812085239.3089231-4-zhengjun.xing@linux.intel.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Zhengjun Xing
Arnaldo Carvalho de Melo
parent
e349fa6cc8
commit
c6e9c04418
@ -715,6 +715,12 @@
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"MetricGroup": "SoC",
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"MetricName": "Socket_CLKS"
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},
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{
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"BriefDescription": "Uncore frequency per die [GHZ]",
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"MetricExpr": "cha_0@event\\=0x0@ / #num_dies / duration_time / 1000000000",
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"MetricGroup": "SoC",
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"MetricName": "UNCORE_FREQ"
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},
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{
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"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
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"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
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Load Diff
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Load Diff
201
tools/perf/pmu-events/arch/x86/cascadelakex/uncore-power.json
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201
tools/perf/pmu-events/arch/x86/cascadelakex/uncore-power.json
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@ -0,0 +1,201 @@
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[
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{
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"BriefDescription": "pclk Cycles",
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"Counter": "0,1,2,3",
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"EventName": "UNC_P_CLOCKTICKS",
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"PerPkg": "1",
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"Unit": "PCU"
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},
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{
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"BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES",
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"Counter": "0,1,2,3",
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"EventCode": "0x60",
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"EventName": "UNC_P_CORE_TRANSITION_CYCLES",
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"PerPkg": "1",
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"Unit": "PCU"
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},
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{
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"BriefDescription": "UNC_P_DEMOTIONS",
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"Counter": "0,1,2,3",
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"EventCode": "0x30",
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"EventName": "UNC_P_DEMOTIONS",
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"PerPkg": "1",
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"Unit": "PCU"
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},
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{
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"BriefDescription": "Phase Shed 0 Cycles",
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"Counter": "0,1,2,3",
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"EventCode": "0x75",
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"EventName": "UNC_P_FIVR_PS_PS0_CYCLES",
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"PerPkg": "1",
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"Unit": "PCU"
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},
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{
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"BriefDescription": "Phase Shed 1 Cycles",
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"Counter": "0,1,2,3",
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"EventCode": "0x76",
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"EventName": "UNC_P_FIVR_PS_PS1_CYCLES",
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"PerPkg": "1",
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"Unit": "PCU"
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},
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{
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"BriefDescription": "Phase Shed 2 Cycles",
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"Counter": "0,1,2,3",
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"EventCode": "0x77",
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"EventName": "UNC_P_FIVR_PS_PS2_CYCLES",
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"PerPkg": "1",
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"Unit": "PCU"
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},
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{
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"BriefDescription": "Phase Shed 3 Cycles",
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"Counter": "0,1,2,3",
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"EventCode": "0x78",
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"EventName": "UNC_P_FIVR_PS_PS3_CYCLES",
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"PerPkg": "1",
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"Unit": "PCU"
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},
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{
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"BriefDescription": "Thermal Strongest Upper Limit Cycles",
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"Counter": "0,1,2,3",
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"EventCode": "0x4",
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"EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
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"PerPkg": "1",
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"Unit": "PCU"
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},
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{
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"BriefDescription": "Power Strongest Upper Limit Cycles",
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"Counter": "0,1,2,3",
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"EventCode": "0x5",
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"EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
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"PerPkg": "1",
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"Unit": "PCU"
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},
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{
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"BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
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"Counter": "0,1,2,3",
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"EventCode": "0x73",
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"EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
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"PerPkg": "1",
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"Unit": "PCU"
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},
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{
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"BriefDescription": "Cycles spent changing Frequency",
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"Counter": "0,1,2,3",
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"EventCode": "0x74",
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"EventName": "UNC_P_FREQ_TRANS_CYCLES",
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"PerPkg": "1",
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"Unit": "PCU"
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},
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{
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"BriefDescription": "UNC_P_MCP_PROCHOT_CYCLES",
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"Counter": "0,1,2,3",
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"EventCode": "0x6",
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"EventName": "UNC_P_MCP_PROCHOT_CYCLES",
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"PerPkg": "1",
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"Unit": "PCU"
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},
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{
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"BriefDescription": "Memory Phase Shedding Cycles",
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"Counter": "0,1,2,3",
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"EventCode": "0x2F",
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"EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
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"PerPkg": "1",
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"Unit": "PCU"
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},
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{
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"BriefDescription": "Package C State Residency - C0",
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"Counter": "0,1,2,3",
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"EventCode": "0x2A",
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"EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
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"PerPkg": "1",
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"Unit": "PCU"
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},
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{
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"BriefDescription": "Package C State Residency - C2E",
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"Counter": "0,1,2,3",
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"EventCode": "0x2B",
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"EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
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"PerPkg": "1",
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"Unit": "PCU"
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},
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{
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"BriefDescription": "Package C State Residency - C3",
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"Counter": "0,1,2,3",
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"EventCode": "0x2C",
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"EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
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"PerPkg": "1",
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"Unit": "PCU"
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},
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{
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"BriefDescription": "Package C State Residency - C6",
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"Counter": "0,1,2,3",
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"EventCode": "0x2D",
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"EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
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"PerPkg": "1",
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"Unit": "PCU"
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},
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{
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"BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES",
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"Counter": "0,1,2,3",
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"EventCode": "0x7",
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"EventName": "UNC_P_PMAX_THROTTLED_CYCLES",
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"PerPkg": "1",
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"Unit": "PCU"
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},
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{
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"BriefDescription": "Number of cores in C-State; C0 and C1",
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"Counter": "0,1,2,3",
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"EventCode": "0x80",
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"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
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"PerPkg": "1",
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"Unit": "PCU"
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},
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{
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"BriefDescription": "Number of cores in C-State; C3",
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"Counter": "0,1,2,3",
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"EventCode": "0x80",
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"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
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"PerPkg": "1",
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"Unit": "PCU"
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},
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{
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"BriefDescription": "Number of cores in C-State; C6 and C7",
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"Counter": "0,1,2,3",
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"EventCode": "0x80",
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"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
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"PerPkg": "1",
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"Unit": "PCU"
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},
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{
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"BriefDescription": "External Prochot",
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"Counter": "0,1,2,3",
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"EventCode": "0xA",
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"EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
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"PerPkg": "1",
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"Unit": "PCU"
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},
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{
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"BriefDescription": "Internal Prochot",
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"Counter": "0,1,2,3",
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"EventCode": "0x9",
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"EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
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"PerPkg": "1",
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"Unit": "PCU"
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},
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{
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"BriefDescription": "Total Core C State Transition Cycles",
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"Counter": "0,1,2,3",
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"EventCode": "0x72",
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"EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
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"PerPkg": "1",
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"Unit": "PCU"
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},
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{
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"BriefDescription": "VR Hot",
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"Counter": "0,1,2,3",
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"EventCode": "0x42",
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"EventName": "UNC_P_VR_HOT_CYCLES",
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"PerPkg": "1",
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"Unit": "PCU"
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}
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]
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