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ARM: dts: Add wlcore wakeirq for omap3-evm

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With wlcore supporting optional wakeirqs, let's configure it for
omap3-evm and update the related pin muxing as some pins are left
unmuxed.

Let's configure a wakeirq both for the wlcore GPIO and the SDIO
dat1 pin in case wlcore starts supporting SDIO dat1 interrupt at
some point.

Note that for off-mode, the wlcore reset GPIO will have a glitch
meaning wlcore will reset. The only way to workaround for this
currently is to configure the reset pin with SAFE_MODE + PULL.

Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tony Lindgren 2018-12-13 15:02:45 -08:00
parent e3b382c107
commit c6e967ad5a
2 changed files with 14 additions and 3 deletions
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7
arch/arm/boot/dts/omap3-evm-common.dtsi
View File

@ -122,6 +122,7 @@
}; };
&mmc2 { &mmc2 {
interrupts-extended = <&intc 86 &omap3_pmx_core 0x12e>;
vmmc-supply = <&wl12xx_vmmc>; vmmc-supply = <&wl12xx_vmmc>;
non-removable; non-removable;
bus-width = <4>; bus-width = <4>;
@ -132,8 +133,10 @@
wlcore: wlcore@2 { wlcore: wlcore@2 {
compatible = "ti,wl1271"; compatible = "ti,wl1271";
reg = <2>; reg = <2>;
interrupt-parent = <&gpio5>; /* gpio_149 with uart1_rts pad as wakeirq */
interrupts = <21 IRQ_TYPE_EDGE_RISING>; /* gpio 149 */ interrupts-extended = <&gpio5 21 IRQ_TYPE_EDGE_RISING>,
<&omap3_pmx_core 0x14e>;
interrupt-names = "irq", "wakeup";
ref-clock-frequency = <38400000>; ref-clock-frequency = <38400000>;
}; };
}; };

10
arch/arm/boot/dts/omap3-evm-processor-common.dtsi
View File

@ -86,6 +86,10 @@
OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */
OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */
OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */
OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */
>; >;
}; };
@ -127,9 +131,13 @@
>; >;
}; };
/*
* Note that gpio_150 pulled high with internal pull to prevent wlcore
* reset on return from off mode in idle.
*/
wl12xx_gpio: pinmux_wl12xx_gpio { wl12xx_gpio: pinmux_wl12xx_gpio {
pinctrl-single,pins = < pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4) /* uart1_cts.gpio_150 */ OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_cts.gpio_150 */
OMAP3_CORE1_IOPAD(0x217e, PIN_INPUT | MUX_MODE4) /* uart1_rts.gpio_149 */ OMAP3_CORE1_IOPAD(0x217e, PIN_INPUT | MUX_MODE4) /* uart1_rts.gpio_149 */
>; >;
}; };