forked from Minki/linux
Qualcomm Device Tree Changes for v4.18 - Part 2
* Numerous updates for IPQ8074 and IPQ4019 based devices * Add support for Sony Xperia Z1 Compact -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJbCHjsAAoJEFKiBbHx2RXV5cIQANoHyPc/DKLQeuHRcYlfH9DD 3y5rH/TVqlAF9bos/oOdWSvTQKuBy9J8nKCLT7QJAzfufvo6LSGfOvQaUT+QYyvQ 9GBSSnyOxydiYCZn4uP3plEwmsMxIWQ+xEANdrVBookWfkOR/057UoCEmeQXDpYO qnyfxEvSqjIZhqLvoLYMsq7rt6tao3JhGfVR0wSeldojfOd8j+Ui7ykBHh/XuJal FW+pyUuJUitz/ChjW9AR/XysXI58cnp4gB9qP+4Qxdt796J7lbNv1pK4wFa3hdCt GoXd4pZUvNyFCFTeCXdQBc+l2hQzPWhAJJio7J+QSFKzb0FzEyDuDkufjFJoe+AA MA5iHfOh1c1AO8N6OoenQbUWpNfMmgAAo5sbFBYUCfdtgq6PI9y4s5gGxwvnvyk1 uvF4K6OzhrUDpdYZsVfo4D/ng9CMHU85dZNjnyc29ZuI64JcERKrZ9HZFmLIz4f6 T9DwrGPVhe++glw7LuywGJJDWuUIy0d0gAabJDTWIKyRxPPss/WeqQfpZ48j5tV3 +Q1SZYijMxtXKBRYzZIWZe7MmOjkuZnHL7kl7y3t182LXNq0ybTiF1s/PwmpsmOy GgQFCOFV9lHzSH0kRBNBc2VXKqTlgtpFbseOJRfzN3+XRVlBJ0qmixUBfmurBxZC uTn4h7wFW7/uqeNylqVJ =rcLr -----END PGP SIGNATURE----- Merge tag 'qcom-dts-for-4.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt Qualcomm Device Tree Changes for v4.18 - Part 2 * Numerous updates for IPQ8074 and IPQ4019 based devices * Add support for Sony Xperia Z1 Compact * tag 'qcom-dts-for-4.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: ARM: dts: ipq8074: Enable few peripherals for hk01 board ARM: dts: ipq8074: Add pcie nodes ARM: dts: ipq8074: Add peripheral nodes ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi ARM: dts: ipq4019: Change the max opp frequency ARM: dts: ipq4019: Add a few peripheral nodes ARM: dts: ipq4019: Add a default chosen node ARM: dts: qcom: msm8974: Add Sony Xperia Z1 Compact Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
c6a893f872
@ -767,12 +767,17 @@ dtb-$(CONFIG_ARCH_QCOM) += \
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qcom-apq8084-ifc6540.dtb \
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qcom-apq8084-mtp.dtb \
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qcom-ipq4019-ap.dk01.1-c1.dtb \
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qcom-ipq4019-ap.dk04.1-c1.dtb \
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qcom-ipq4019-ap.dk04.1-c3.dtb \
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qcom-ipq4019-ap.dk07.1-c1.dtb \
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qcom-ipq4019-ap.dk07.1-c2.dtb \
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qcom-ipq8064-ap148.dtb \
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qcom-msm8660-surf.dtb \
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qcom-msm8960-cdp.dtb \
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qcom-msm8974-fairphone-fp2.dtb \
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qcom-msm8974-lge-nexus5-hammerhead.dtb \
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qcom-msm8974-samsung-klte.dtb \
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qcom-msm8974-sony-xperia-amami.dtb \
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qcom-msm8974-sony-xperia-castor.dtb \
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qcom-msm8974-sony-xperia-honami.dtb \
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qcom-mdm9615-wp8548-mangoh-green.dtb
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@ -20,6 +20,14 @@
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model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
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compatible = "qcom,ipq4019";
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aliases {
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serial0 = &blsp1_uart1;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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soc {
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rng@22000 {
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status = "ok";
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@ -61,7 +69,7 @@
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status = "ok";
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};
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spi_0: spi@78b5000 {
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spi@78b5000 {
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pinctrl-0 = <&spi_0_pins>;
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pinctrl-names = "default";
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status = "ok";
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19
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
Normal file
19
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
Normal file
@ -0,0 +1,19 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018, The Linux Foundation. All rights reserved.
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#include "qcom-ipq4019-ap.dk04.1.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C1";
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compatible = "qcom,ipq4019-dk04.1-c1";
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soc {
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dma@7984000 {
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status = "ok";
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};
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qpic-nand@79b0000 {
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status = "ok";
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};
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};
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};
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9
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
Normal file
9
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
Normal file
@ -0,0 +1,9 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018, The Linux Foundation. All rights reserved.
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#include "qcom-ipq4019-ap.dk04.1.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C3";
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compatible = "qcom,ipq4019-ap-dk04.1-c3";
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};
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111
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
Normal file
111
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
Normal file
@ -0,0 +1,111 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018, The Linux Foundation. All rights reserved.
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#include "qcom-ipq4019.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
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aliases {
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serial0 = &blsp1_uart1;
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serial1 = &blsp1_uart2;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory {
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device_type = "memory";
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reg = <0x80000000 0x10000000>; /* 256MB */
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};
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soc {
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pinctrl@1000000 {
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serial_0_pins: serial0-pinmux {
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pins = "gpio16", "gpio17";
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function = "blsp_uart0";
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bias-disable;
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};
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serial_1_pins: serial1-pinmux {
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pins = "gpio8", "gpio9",
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"gpio10", "gpio11";
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function = "blsp_uart1";
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bias-disable;
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};
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spi_0_pins: spi-0-pinmux {
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pinmux {
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function = "blsp_spi0";
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pins = "gpio13", "gpio14", "gpio15";
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bias-disable;
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};
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pinmux_cs {
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function = "gpio";
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pins = "gpio12";
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bias-disable;
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output-high;
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};
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};
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i2c_0_pins: i2c-0-pinmux {
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pins = "gpio20", "gpio21";
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function = "blsp_i2c0";
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bias-disable;
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};
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nand_pins: nand-pins {
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pins = "gpio53", "gpio55", "gpio56",
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"gpio57", "gpio58", "gpio59",
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"gpio60", "gpio62", "gpio63",
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"gpio64", "gpio65", "gpio66",
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"gpio67", "gpio68", "gpio69";
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function = "qpic";
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};
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};
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serial@78af000 {
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pinctrl-0 = <&serial_0_pins>;
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pinctrl-names = "default";
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status = "ok";
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};
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serial@78b0000 {
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pinctrl-0 = <&serial_1_pins>;
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pinctrl-names = "default";
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status = "ok";
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};
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dma@7884000 {
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status = "ok";
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};
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spi@78b5000 { /* BLSP1 QUP1 */
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pinctrl-0 = <&spi_0_pins>;
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pinctrl-names = "default";
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status = "ok";
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cs-gpios = <&tlmm 12 0>;
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m25p80@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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compatible = "n25q128a11";
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spi-max-frequency = <24000000>;
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};
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};
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pci@40000000 {
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status = "ok";
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perst-gpio = <&tlmm 38 0x1>;
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};
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qpic-nand@79b0000 {
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pinctrl-0 = <&nand_pins>;
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pinctrl-names = "default";
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};
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};
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};
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64
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
Normal file
64
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
Normal file
@ -0,0 +1,64 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018, The Linux Foundation. All rights reserved.
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#include "qcom-ipq4019-ap.dk07.1.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C1";
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compatible = "qcom,ipq4019-ap-dk07.1-c1";
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soc {
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pci@40000000 {
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status = "ok";
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perst-gpio = <&tlmm 38 0x1>;
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};
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spi@78b6000 {
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status = "ok";
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};
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pinctrl@1000000 {
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serial_1_pins: serial1-pinmux {
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pins = "gpio8", "gpio9",
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"gpio10", "gpio11";
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function = "blsp_uart1";
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bias-disable;
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};
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spi_0_pins: spi-0-pinmux {
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pinmux {
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function = "blsp_spi0";
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pins = "gpio13", "gpio14", "gpio15";
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bias-disable;
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};
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pinmux_cs {
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function = "gpio";
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pins = "gpio12";
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bias-disable;
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output-high;
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};
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};
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};
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serial@78b0000 {
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pinctrl-0 = <&serial_1_pins>;
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pinctrl-names = "default";
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status = "ok";
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};
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spi@78b5000 {
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pinctrl-0 = <&spi_0_pins>;
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pinctrl-names = "default";
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status = "ok";
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cs-gpios = <&tlmm 12 0>;
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m25p80@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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compatible = "n25q128a11";
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spi-max-frequency = <24000000>;
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};
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};
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};
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};
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25
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
Normal file
25
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
Normal file
@ -0,0 +1,25 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018, The Linux Foundation. All rights reserved.
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#include "qcom-ipq4019-ap.dk07.1.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C2";
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compatible = "qcom,ipq4019-ap-dk07.1-c2";
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soc {
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pinctrl@1000000 {
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serial_1_pins: serial1-pinmux {
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pins = "gpio8", "gpio9";
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function = "blsp_uart1";
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bias-disable;
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};
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};
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serial@78b0000 {
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pinctrl-0 = <&serial_1_pins>;
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pinctrl-names = "default";
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status = "ok";
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};
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};
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};
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75
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
Normal file
75
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
Normal file
@ -0,0 +1,75 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018, The Linux Foundation. All rights reserved.
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#include "qcom-ipq4019.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1";
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memory {
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device_type = "memory";
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reg = <0x80000000 0x20000000>; /* 512MB */
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};
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aliases {
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serial0 = &blsp1_uart1;
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serial1 = &blsp1_uart2;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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soc {
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pinctrl@1000000 {
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serial_0_pins: serial0-pinmux {
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pins = "gpio16", "gpio17";
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function = "blsp_uart0";
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bias-disable;
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};
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i2c_0_pins: i2c-0-pinmux {
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pins = "gpio20", "gpio21";
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function = "blsp_i2c0";
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bias-disable;
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};
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nand_pins: nand-pins {
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pins = "gpio53", "gpio55", "gpio56",
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"gpio57", "gpio58", "gpio59",
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"gpio60", "gpio62", "gpio63",
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"gpio64", "gpio65", "gpio66",
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"gpio67", "gpio68", "gpio69";
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function = "qpic";
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};
|
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};
|
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|
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serial@78af000 {
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pinctrl-0 = <&serial_0_pins>;
|
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pinctrl-names = "default";
|
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status = "ok";
|
||||
};
|
||||
|
||||
dma@7884000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
i2c@78b7000 { /* BLSP1 QUP2 */
|
||||
pinctrl-0 = <&i2c_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
dma@7984000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
qpic-nand@79b0000 {
|
||||
pinctrl-0 = <&nand_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "ok";
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -40,8 +40,10 @@
|
||||
};
|
||||
|
||||
aliases {
|
||||
spi0 = &spi_0;
|
||||
i2c0 = &i2c_0;
|
||||
spi0 = &blsp1_spi1;
|
||||
spi1 = &blsp1_spi2;
|
||||
i2c0 = &blsp1_i2c3;
|
||||
i2c1 = &blsp1_i2c4;
|
||||
};
|
||||
|
||||
cpus {
|
||||
@ -61,7 +63,7 @@
|
||||
48000 1100000
|
||||
200000 1100000
|
||||
500000 1100000
|
||||
666000 1100000
|
||||
716000 1100000
|
||||
>;
|
||||
clock-latency = <256000>;
|
||||
};
|
||||
@ -120,6 +122,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
firmware {
|
||||
scm {
|
||||
compatible = "qcom,scm-ipq4019";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 2 0xf08>,
|
||||
@ -165,13 +173,13 @@
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0 208 0>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
blsp_dma: dma@7884000 {
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
reg = <0x07884000 0x23000>;
|
||||
interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
|
||||
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>;
|
||||
clock-names = "bam_clk";
|
||||
#dma-cells = <1>;
|
||||
@ -179,7 +187,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi_0: spi@78b5000 {
|
||||
blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
|
||||
compatible = "qcom,spi-qup-v2.2.1";
|
||||
reg = <0x78b5000 0x600>;
|
||||
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
||||
@ -188,10 +196,26 @@
|
||||
clock-names = "core", "iface";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
dmas = <&blsp_dma 5>, <&blsp_dma 4>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c_0: i2c@78b7000 {
|
||||
blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
|
||||
compatible = "qcom,spi-qup-v2.2.1";
|
||||
reg = <0x78b6000 0x600>;
|
||||
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
|
||||
<&gcc GCC_BLSP1_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
dmas = <&blsp_dma 7>, <&blsp_dma 6>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
|
||||
compatible = "qcom,i2c-qup-v2.2.1";
|
||||
reg = <0x78b7000 0x600>;
|
||||
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
@ -200,14 +224,29 @@
|
||||
clock-names = "iface", "core";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
dmas = <&blsp_dma 9>, <&blsp_dma 8>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
|
||||
compatible = "qcom,i2c-qup-v2.2.1";
|
||||
reg = <0x78b8000 0x600>;
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||||
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
|
||||
clock-names = "iface", "core";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
dmas = <&blsp_dma 11>, <&blsp_dma 10>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cryptobam: dma@8e04000 {
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
reg = <0x08e04000 0x20000>;
|
||||
interrupts = <GIC_SPI 207 0>;
|
||||
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
|
||||
clock-names = "bam_clk";
|
||||
#dma-cells = <1>;
|
||||
@ -272,10 +311,10 @@
|
||||
regulator;
|
||||
};
|
||||
|
||||
serial@78af000 {
|
||||
blsp1_uart1: serial@78af000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0x78af000 0x200>;
|
||||
interrupts = <0 107 0>;
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
|
||||
<&gcc GCC_BLSP1_AHB_CLK>;
|
||||
@ -284,10 +323,10 @@
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
|
||||
serial@78b0000 {
|
||||
blsp1_uart2: serial@78b0000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0x78b0000 0x200>;
|
||||
interrupts = <0 108 0>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
|
||||
<&gcc GCC_BLSP1_AHB_CLK>;
|
||||
@ -309,6 +348,101 @@
|
||||
reg = <0x4ab000 0x4>;
|
||||
};
|
||||
|
||||
pcie0: pci@40000000 {
|
||||
compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
|
||||
reg = <0x40000000 0xf1d
|
||||
0x40000f20 0xa8
|
||||
0x80000 0x2000
|
||||
0x40100000 0x1000>;
|
||||
reg-names = "dbi", "elbi", "parf", "config";
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
|
||||
0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
|
||||
|
||||
interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
clocks = <&gcc GCC_PCIE_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_AXI_M_CLK>,
|
||||
<&gcc GCC_PCIE_AXI_S_CLK>;
|
||||
clock-names = "aux",
|
||||
"master_bus",
|
||||
"slave_bus";
|
||||
|
||||
resets = <&gcc PCIE_AXI_M_ARES>,
|
||||
<&gcc PCIE_AXI_S_ARES>,
|
||||
<&gcc PCIE_PIPE_ARES>,
|
||||
<&gcc PCIE_AXI_M_VMIDMT_ARES>,
|
||||
<&gcc PCIE_AXI_S_XPU_ARES>,
|
||||
<&gcc PCIE_PARF_XPU_ARES>,
|
||||
<&gcc PCIE_PHY_ARES>,
|
||||
<&gcc PCIE_AXI_M_STICKY_ARES>,
|
||||
<&gcc PCIE_PIPE_STICKY_ARES>,
|
||||
<&gcc PCIE_PWR_ARES>,
|
||||
<&gcc PCIE_AHB_ARES>,
|
||||
<&gcc PCIE_PHY_AHB_ARES>;
|
||||
reset-names = "axi_m",
|
||||
"axi_s",
|
||||
"pipe",
|
||||
"axi_m_vmid",
|
||||
"axi_s_xpu",
|
||||
"parf",
|
||||
"phy",
|
||||
"axi_m_sticky",
|
||||
"pipe_sticky",
|
||||
"pwr",
|
||||
"ahb",
|
||||
"phy_ahb";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qpic_bam: dma@7984000 {
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
reg = <0x7984000 0x1a000>;
|
||||
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_QPIC_CLK>;
|
||||
clock-names = "bam_clk";
|
||||
#dma-cells = <1>;
|
||||
qcom,ee = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nand: qpic-nand@79b0000 {
|
||||
compatible = "qcom,ipq4019-nand";
|
||||
reg = <0x79b0000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&gcc GCC_QPIC_CLK>,
|
||||
<&gcc GCC_QPIC_AHB_CLK>;
|
||||
clock-names = "core", "aon";
|
||||
|
||||
dmas = <&qpic_bam 0>,
|
||||
<&qpic_bam 1>,
|
||||
<&qpic_bam 2>;
|
||||
dma-names = "tx", "rx", "cmd";
|
||||
status = "disabled";
|
||||
|
||||
nand@0 {
|
||||
reg = <0>;
|
||||
|
||||
nand-ecc-strength = <4>;
|
||||
nand-ecc-step-size = <512>;
|
||||
nand-bus-width = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
wifi0: wifi@a000000 {
|
||||
compatible = "qcom,ipq4019-wifi";
|
||||
reg = <0xa000000 0x200000>;
|
||||
@ -342,7 +476,7 @@
|
||||
<GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 168 IRQ_TYPE_NONE>;
|
||||
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi0", "msi1", "msi2", "msi3",
|
||||
"msi4", "msi5", "msi6", "msi7",
|
||||
"msi8", "msi9", "msi10", "msi11",
|
||||
@ -384,7 +518,7 @@
|
||||
<GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 169 IRQ_TYPE_NONE>;
|
||||
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi0", "msi1", "msi2", "msi3",
|
||||
"msi4", "msi5", "msi6", "msi7",
|
||||
"msi8", "msi9", "msi10", "msi11",
|
||||
|
||||
436
arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts
Normal file
436
arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts
Normal file
@ -0,0 +1,436 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
#include "qcom-msm8974.dtsi"
|
||||
#include "qcom-pm8841.dtsi"
|
||||
#include "qcom-pm8941.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Sony Xperia Z1 Compact";
|
||||
compatible = "sony,xperia-amami", "qcom,msm8974";
|
||||
|
||||
aliases {
|
||||
serial0 = &blsp1_uart2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
input-name = "gpio-keys";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gpio_keys_pin_a>;
|
||||
|
||||
volume-down {
|
||||
label = "volume_down";
|
||||
gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>;
|
||||
linux,input-type = <1>;
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
};
|
||||
|
||||
camera-snapshot {
|
||||
label = "camera_snapshot";
|
||||
gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>;
|
||||
linux,input-type = <1>;
|
||||
linux,code = <KEY_CAMERA>;
|
||||
};
|
||||
|
||||
camera-focus {
|
||||
label = "camera_focus";
|
||||
gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>;
|
||||
linux,input-type = <1>;
|
||||
linux,code = <KEY_CAMERA_FOCUS>;
|
||||
};
|
||||
|
||||
volume-up {
|
||||
label = "volume_up";
|
||||
gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>;
|
||||
linux,input-type = <1>;
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
};
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
reg = <0 0x40000000>, <0x40000000 0x40000000>;
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
smd {
|
||||
rpm {
|
||||
rpm_requests {
|
||||
pm8841-regulators {
|
||||
s1 {
|
||||
regulator-min-microvolt = <675000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
};
|
||||
|
||||
s2 {
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
};
|
||||
|
||||
s3 {
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
};
|
||||
|
||||
s4 {
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
};
|
||||
};
|
||||
|
||||
pm8941-regulators {
|
||||
vdd_l1_l3-supply = <&pm8941_s1>;
|
||||
vdd_l2_lvs1_2_3-supply = <&pm8941_s3>;
|
||||
vdd_l4_l11-supply = <&pm8941_s1>;
|
||||
vdd_l5_l7-supply = <&pm8941_s2>;
|
||||
vdd_l6_l12_l14_l15-supply = <&pm8941_s2>;
|
||||
vdd_l9_l10_l17_l22-supply = <&vreg_boost>;
|
||||
vdd_l13_l20_l23_l24-supply = <&vreg_boost>;
|
||||
vdd_l21-supply = <&vreg_boost>;
|
||||
|
||||
s1 {
|
||||
regulator-min-microvolt = <1300000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
s2 {
|
||||
regulator-min-microvolt = <2150000>;
|
||||
regulator-max-microvolt = <2150000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
s3 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
s4 {
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
l1 {
|
||||
regulator-min-microvolt = <1225000>;
|
||||
regulator-max-microvolt = <1225000>;
|
||||
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
l2 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
l3 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
l4 {
|
||||
regulator-min-microvolt = <1225000>;
|
||||
regulator-max-microvolt = <1225000>;
|
||||
};
|
||||
|
||||
l5 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
l6 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
l7 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
l8 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
l9 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2950000>;
|
||||
};
|
||||
|
||||
l11 {
|
||||
regulator-min-microvolt = <1300000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
};
|
||||
|
||||
l12 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
l13 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2950000>;
|
||||
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
l14 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
l15 {
|
||||
regulator-min-microvolt = <2050000>;
|
||||
regulator-max-microvolt = <2050000>;
|
||||
};
|
||||
|
||||
l16 {
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <2700000>;
|
||||
};
|
||||
|
||||
l17 {
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <2700000>;
|
||||
};
|
||||
|
||||
l18 {
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
};
|
||||
|
||||
l19 {
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
l20 {
|
||||
regulator-min-microvolt = <2950000>;
|
||||
regulator-max-microvolt = <2950000>;
|
||||
|
||||
regulator-allow-set-load;
|
||||
regulator-boot-on;
|
||||
regulator-system-load = <200000>;
|
||||
};
|
||||
|
||||
l21 {
|
||||
regulator-min-microvolt = <2950000>;
|
||||
regulator-max-microvolt = <2950000>;
|
||||
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
l22 {
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
|
||||
l23 {
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
};
|
||||
|
||||
l24 {
|
||||
regulator-min-microvolt = <3075000>;
|
||||
regulator-max-microvolt = <3075000>;
|
||||
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
sdhci@f9824900 {
|
||||
status = "ok";
|
||||
|
||||
vmmc-supply = <&pm8941_l20>;
|
||||
vqmmc-supply = <&pm8941_s3>;
|
||||
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdhc1_pin_a>;
|
||||
};
|
||||
|
||||
sdhci@f98a4900 {
|
||||
status = "ok";
|
||||
|
||||
bus-width = <4>;
|
||||
|
||||
vmmc-supply = <&pm8941_l21>;
|
||||
vqmmc-supply = <&pm8941_l13>;
|
||||
|
||||
cd-gpios = <&msmgpio 62 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>;
|
||||
};
|
||||
|
||||
serial@f991e000 {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&blsp1_uart2_pin_a>;
|
||||
};
|
||||
|
||||
|
||||
pinctrl@fd510000 {
|
||||
blsp1_uart2_pin_a: blsp1-uart2-pin-active {
|
||||
rx {
|
||||
pins = "gpio5";
|
||||
function = "blsp_uart2";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
tx {
|
||||
pins = "gpio4";
|
||||
function = "blsp_uart2";
|
||||
|
||||
drive-strength = <4>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2_pins: i2c2 {
|
||||
mux {
|
||||
pins = "gpio6", "gpio7";
|
||||
function = "blsp_i2c2";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
sdhc1_pin_a: sdhc1-pin-active {
|
||||
clk {
|
||||
pins = "sdc1_clk";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
cmd-data {
|
||||
pins = "sdc1_cmd", "sdc1_data";
|
||||
drive-strength = <10>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
sdhc2_cd_pin_a: sdhc2-cd-pin-active {
|
||||
pins = "gpio62";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
sdhc2_pin_a: sdhc2-pin-active {
|
||||
clk {
|
||||
pins = "sdc2_clk";
|
||||
drive-strength = <10>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
cmd-data {
|
||||
pins = "sdc2_cmd", "sdc2_data";
|
||||
drive-strength = <6>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dma-controller@f9944000 {
|
||||
qcom,controlled-remotely;
|
||||
};
|
||||
|
||||
usb@f9a55000 {
|
||||
status = "ok";
|
||||
|
||||
phys = <&usb_hs1_phy>;
|
||||
phy-select = <&tcsr 0xb000 0>;
|
||||
extcon = <&smbb>, <&usb_id>;
|
||||
vbus-supply = <&chg_otg>;
|
||||
|
||||
hnp-disable;
|
||||
srp-disable;
|
||||
adp-disable;
|
||||
|
||||
ulpi {
|
||||
phy@a {
|
||||
status = "ok";
|
||||
|
||||
v1p8-supply = <&pm8941_l6>;
|
||||
v3p3-supply = <&pm8941_l24>;
|
||||
|
||||
extcon = <&smbb>;
|
||||
qcom,init-seq = /bits/ 8 <0x1 0x64>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spmi_bus {
|
||||
pm8941@0 {
|
||||
charger@1000 {
|
||||
qcom,fast-charge-safe-current = <1300000>;
|
||||
qcom,fast-charge-current-limit = <1300000>;
|
||||
qcom,dc-current-limit = <1300000>;
|
||||
qcom,fast-charge-safe-voltage = <4400000>;
|
||||
qcom,fast-charge-high-threshold-voltage = <4350000>;
|
||||
qcom,fast-charge-low-threshold-voltage = <3400000>;
|
||||
qcom,auto-recharge-threshold-voltage = <4200000>;
|
||||
qcom,minimum-input-voltage = <4300000>;
|
||||
};
|
||||
|
||||
gpios@c000 {
|
||||
gpio_keys_pin_a: gpio-keys-active {
|
||||
pins = "gpio2", "gpio3", "gpio4", "gpio5";
|
||||
function = "normal";
|
||||
|
||||
bias-pull-up;
|
||||
power-source = <PM8941_GPIO_S3>;
|
||||
};
|
||||
};
|
||||
|
||||
coincell@2800 {
|
||||
status = "ok";
|
||||
qcom,rset-ohms = <2100>;
|
||||
qcom,vset-millivolts = <3000>;
|
||||
};
|
||||
};
|
||||
|
||||
pm8941@1 {
|
||||
wled@d800 {
|
||||
status = "ok";
|
||||
|
||||
qcom,cs-out;
|
||||
qcom,current-limit = <20>;
|
||||
qcom,current-boost-limit = <805>;
|
||||
qcom,switching-freq = <1600>;
|
||||
qcom,ovp = <29>;
|
||||
qcom,num-strings = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -21,6 +21,7 @@
|
||||
|
||||
aliases {
|
||||
serial0 = &blsp1_uart5;
|
||||
serial1 = &blsp1_uart3;
|
||||
};
|
||||
|
||||
chosen {
|
||||
@ -33,20 +34,61 @@
|
||||
};
|
||||
|
||||
soc {
|
||||
pinctrl@1000000 {
|
||||
serial_4_pins: serial4_pinmux {
|
||||
mux {
|
||||
pins = "gpio23", "gpio24";
|
||||
function = "blsp4_uart1";
|
||||
bias-disable;
|
||||
};
|
||||
serial@78b3000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
spi@78b5000 {
|
||||
status = "ok";
|
||||
|
||||
m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
|
||||
serial@78b3000 {
|
||||
pinctrl-0 = <&serial_4_pins>;
|
||||
pinctrl-names = "default";
|
||||
serial@78b1000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
i2c@78b6000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
dma@7984000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
nand@79b0000 {
|
||||
status = "ok";
|
||||
|
||||
nand@0 {
|
||||
reg = <0>;
|
||||
nand-ecc-strength = <4>;
|
||||
nand-ecc-step-size = <512>;
|
||||
nand-bus-width = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
phy@86000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@8e000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
pci@20000000 {
|
||||
status = "ok";
|
||||
perst-gpio = <&tlmm 58 0x1>;
|
||||
};
|
||||
|
||||
pci@10000000 {
|
||||
status = "ok";
|
||||
perst-gpio = <&tlmm 61 0x1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -24,7 +24,7 @@
|
||||
ranges = <0 0 0 0xffffffff>;
|
||||
compatible = "simple-bus";
|
||||
|
||||
pinctrl@1000000 {
|
||||
tlmm: pinctrl@1000000 {
|
||||
compatible = "qcom,ipq8074-pinctrl";
|
||||
reg = <0x1000000 0x300000>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
@ -32,6 +32,45 @@
|
||||
#gpio-cells = <0x2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <0x2>;
|
||||
|
||||
serial_4_pins: serial4-pinmux {
|
||||
pins = "gpio23", "gpio24";
|
||||
function = "blsp4_uart1";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
i2c_0_pins: i2c-0-pinmux {
|
||||
pins = "gpio42", "gpio43";
|
||||
function = "blsp1_i2c";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
spi_0_pins: spi-0-pins {
|
||||
pins = "gpio38", "gpio39", "gpio40", "gpio41";
|
||||
function = "blsp0_spi";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
hsuart_pins: hsuart-pins {
|
||||
pins = "gpio46", "gpio47", "gpio48", "gpio49";
|
||||
function = "blsp2_uart";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
qpic_pins: qpic-pins {
|
||||
pins = "gpio1", "gpio3", "gpio4",
|
||||
"gpio5", "gpio6", "gpio7",
|
||||
"gpio8", "gpio10", "gpio11",
|
||||
"gpio12", "gpio13", "gpio14",
|
||||
"gpio15", "gpio16", "gpio17";
|
||||
function = "qpic";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
intc: interrupt-controller@b000000 {
|
||||
@ -122,6 +161,276 @@
|
||||
clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
|
||||
<&gcc GCC_BLSP1_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
pinctrl-0 = <&serial_4_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp_dma: dma@7884000 {
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
reg = <0x7884000 0x2b000>;
|
||||
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>;
|
||||
clock-names = "bam_clk";
|
||||
#dma-cells = <1>;
|
||||
qcom,ee = <0>;
|
||||
};
|
||||
|
||||
blsp1_uart1: serial@78af000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0x78af000 0x200>;
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
|
||||
<&gcc GCC_BLSP1_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_uart3: serial@78b1000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0x78b1000 0x200>;
|
||||
interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
|
||||
<&gcc GCC_BLSP1_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
dmas = <&blsp_dma 4>,
|
||||
<&blsp_dma 5>;
|
||||
dma-names = "tx", "rx";
|
||||
pinctrl-0 = <&hsuart_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_spi1: spi@78b5000 {
|
||||
compatible = "qcom,spi-qup-v2.2.1";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x78b5000 0x600>;
|
||||
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
||||
spi-max-frequency = <50000000>;
|
||||
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
|
||||
<&gcc GCC_BLSP1_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
dmas = <&blsp_dma 12>, <&blsp_dma 13>;
|
||||
dma-names = "tx", "rx";
|
||||
pinctrl-0 = <&spi_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_i2c2: i2c@78b6000 {
|
||||
compatible = "qcom,i2c-qup-v2.2.1";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x78b6000 0x600>;
|
||||
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||||
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
|
||||
clock-names = "iface", "core";
|
||||
clock-frequency = <400000>;
|
||||
dmas = <&blsp_dma 15>, <&blsp_dma 14>;
|
||||
dma-names = "rx", "tx";
|
||||
pinctrl-0 = <&i2c_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_i2c3: i2c@78b7000 {
|
||||
compatible = "qcom,i2c-qup-v2.2.1";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x78b7000 0x600>;
|
||||
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||||
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
|
||||
clock-names = "iface", "core";
|
||||
clock-frequency = <100000>;
|
||||
dmas = <&blsp_dma 17>, <&blsp_dma 16>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qpic_bam: dma@7984000 {
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
reg = <0x7984000 0x1a000>;
|
||||
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_QPIC_AHB_CLK>;
|
||||
clock-names = "bam_clk";
|
||||
#dma-cells = <1>;
|
||||
qcom,ee = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qpic_nand: nand@79b0000 {
|
||||
compatible = "qcom,ipq8074-nand";
|
||||
reg = <0x79b0000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&gcc GCC_QPIC_CLK>,
|
||||
<&gcc GCC_QPIC_AHB_CLK>;
|
||||
clock-names = "core", "aon";
|
||||
|
||||
dmas = <&qpic_bam 0>,
|
||||
<&qpic_bam 1>,
|
||||
<&qpic_bam 2>;
|
||||
dma-names = "tx", "rx", "cmd";
|
||||
pinctrl-0 = <&qpic_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie_phy0: phy@86000 {
|
||||
compatible = "qcom,ipq8074-qmp-pcie-phy";
|
||||
reg = <0x86000 0x1000>;
|
||||
#phy-cells = <0>;
|
||||
clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
|
||||
clock-names = "pipe_clk";
|
||||
clock-output-names = "pcie20_phy0_pipe_clk";
|
||||
|
||||
resets = <&gcc GCC_PCIE0_PHY_BCR>,
|
||||
<&gcc GCC_PCIE0PHY_PHY_BCR>;
|
||||
reset-names = "phy",
|
||||
"common";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie0: pci@20000000 {
|
||||
compatible = "qcom,pcie-ipq8074";
|
||||
reg = <0x20000000 0xf1d
|
||||
0x20000f20 0xa8
|
||||
0x80000 0x2000
|
||||
0x20100000 0x1000>;
|
||||
reg-names = "dbi", "elbi", "parf", "config";
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
phys = <&pcie_phy0>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
ranges = <0x81000000 0 0x20200000 0x20200000
|
||||
0 0x100000 /* downstream I/O */
|
||||
0x82000000 0 0x20300000 0x20300000
|
||||
0 0xd00000>; /* non-prefetchable memory */
|
||||
|
||||
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 75
|
||||
IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
<0 0 0 2 &intc 0 78
|
||||
IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
<0 0 0 3 &intc 0 79
|
||||
IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
<0 0 0 4 &intc 0 83
|
||||
IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
|
||||
clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
|
||||
<&gcc GCC_PCIE0_AXI_M_CLK>,
|
||||
<&gcc GCC_PCIE0_AXI_S_CLK>,
|
||||
<&gcc GCC_PCIE0_AHB_CLK>,
|
||||
<&gcc GCC_PCIE0_AUX_CLK>;
|
||||
|
||||
clock-names = "iface",
|
||||
"axi_m",
|
||||
"axi_s",
|
||||
"ahb",
|
||||
"aux";
|
||||
resets = <&gcc GCC_PCIE0_PIPE_ARES>,
|
||||
<&gcc GCC_PCIE0_SLEEP_ARES>,
|
||||
<&gcc GCC_PCIE0_CORE_STICKY_ARES>,
|
||||
<&gcc GCC_PCIE0_AXI_MASTER_ARES>,
|
||||
<&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
|
||||
<&gcc GCC_PCIE0_AHB_ARES>,
|
||||
<&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
|
||||
reset-names = "pipe",
|
||||
"sleep",
|
||||
"sticky",
|
||||
"axi_m",
|
||||
"axi_s",
|
||||
"ahb",
|
||||
"axi_m_sticky";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie_phy1: phy@8e000 {
|
||||
compatible = "qcom,ipq8074-qmp-pcie-phy";
|
||||
reg = <0x8e000 0x1000>;
|
||||
#phy-cells = <0>;
|
||||
clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
|
||||
clock-names = "pipe_clk";
|
||||
clock-output-names = "pcie20_phy1_pipe_clk";
|
||||
|
||||
resets = <&gcc GCC_PCIE1_PHY_BCR>,
|
||||
<&gcc GCC_PCIE1PHY_PHY_BCR>;
|
||||
reset-names = "phy",
|
||||
"common";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie1: pci@10000000 {
|
||||
compatible = "qcom,pcie-ipq8074";
|
||||
reg = <0x10000000 0xf1d
|
||||
0x10000f20 0xa8
|
||||
0x88000 0x2000
|
||||
0x10100000 0x1000>;
|
||||
reg-names = "dbi", "elbi", "parf", "config";
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <1>;
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
phys = <&pcie_phy1>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
ranges = <0x81000000 0 0x10200000 0x10200000
|
||||
0 0x100000 /* downstream I/O */
|
||||
0x82000000 0 0x10300000 0x10300000
|
||||
0 0xd00000>; /* non-prefetchable memory */
|
||||
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 142
|
||||
IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
<0 0 0 2 &intc 0 143
|
||||
IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
<0 0 0 3 &intc 0 144
|
||||
IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
<0 0 0 4 &intc 0 145
|
||||
IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
|
||||
clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
|
||||
<&gcc GCC_PCIE1_AXI_M_CLK>,
|
||||
<&gcc GCC_PCIE1_AXI_S_CLK>,
|
||||
<&gcc GCC_PCIE1_AHB_CLK>,
|
||||
<&gcc GCC_PCIE1_AUX_CLK>;
|
||||
clock-names = "iface",
|
||||
"axi_m",
|
||||
"axi_s",
|
||||
"ahb",
|
||||
"aux";
|
||||
resets = <&gcc GCC_PCIE1_PIPE_ARES>,
|
||||
<&gcc GCC_PCIE1_SLEEP_ARES>,
|
||||
<&gcc GCC_PCIE1_CORE_STICKY_ARES>,
|
||||
<&gcc GCC_PCIE1_AXI_MASTER_ARES>,
|
||||
<&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
|
||||
<&gcc GCC_PCIE1_AHB_ARES>,
|
||||
<&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
|
||||
reset-names = "pipe",
|
||||
"sleep",
|
||||
"sticky",
|
||||
"axi_m",
|
||||
"axi_s",
|
||||
"ahb",
|
||||
"axi_m_sticky";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
@ -175,7 +484,7 @@
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
|
||||
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user