drm/amdgpu/soc15: fix xclk for raven
It's 25 Mhz (refclk / 4). This fixes the interpretation of the rlc clock counter. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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@ -272,7 +272,12 @@ static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
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static u32 soc15_get_xclk(struct amdgpu_device *adev)
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static u32 soc15_get_xclk(struct amdgpu_device *adev)
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{
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{
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return adev->clock.spll.reference_freq;
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u32 reference_clock = adev->clock.spll.reference_freq;
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if (adev->asic_type == CHIP_RAVEN)
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return reference_clock / 4;
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return reference_clock;
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}
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}
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