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clk: renesas: r8a779a0: Add RAVB clocks

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Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210121100619.5653-3-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Wolfram Sang 2021-01-21 11:06:16 +01:00 committed by Geert Uytterhoeven
parent 6893a77279
commit c5e91ba25a
1 changed files with 6 additions and 0 deletions
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6
drivers/clk/renesas/r8a779a0-cpg-mssr.c
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@ -156,6 +156,12 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
};
static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
DEF_MOD("avb0", 211, R8A779A0_CLK_S3D2),
DEF_MOD("avb1", 212, R8A779A0_CLK_S3D2),
DEF_MOD("avb2", 213, R8A779A0_CLK_S3D2),
DEF_MOD("avb3", 214, R8A779A0_CLK_S3D2),
DEF_MOD("avb4", 215, R8A779A0_CLK_S3D2),
DEF_MOD("avb5", 216, R8A779A0_CLK_S3D2),
DEF_MOD("csi40", 331, R8A779A0_CLK_CSI0),
DEF_MOD("csi41", 400, R8A779A0_CLK_CSI0),
DEF_MOD("csi42", 401, R8A779A0_CLK_CSI0),