forked from Minki/linux
MIPS: Add support for XPA.
Add support for extended physical addressing (XPA) so that
32-bit platforms can access equal to or greater than 40 bits
of physical addresses.
NOTE:
1) XPA and EVA are not the same and cannot be used
simultaneously.
2) If you configure your kernel for XPA, the PTEs
and all address sizes become 64-bit.
3) Your platform MUST have working HIGHMEM support.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9355/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Steven J. Hill
Ralf Baechle
parent
be0c37c985
commit
c5b367835c
@ -377,6 +377,7 @@ config MIPS_MALTA
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select SYS_HAS_CPU_MIPS32_R1
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select SYS_HAS_CPU_MIPS32_R2
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select SYS_HAS_CPU_MIPS32_R3_5
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select SYS_HAS_CPU_MIPS32_R5
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select SYS_HAS_CPU_MIPS32_R6
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select SYS_HAS_CPU_MIPS64_R1
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select SYS_HAS_CPU_MIPS64_R2
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@ -386,6 +387,7 @@ config MIPS_MALTA
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_64BIT_KERNEL
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select SYS_SUPPORTS_BIG_ENDIAN
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select SYS_SUPPORTS_HIGHMEM
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select SYS_SUPPORTS_MICROMIPS
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select SYS_SUPPORTS_MIPS_CMP
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@ -1596,6 +1598,33 @@ config CPU_MIPS32_3_5_EVA
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One of its primary benefits is an increase in the maximum size
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of lowmem (up to 3GB). If unsure, say 'N' here.
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config CPU_MIPS32_R5_FEATURES
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bool "MIPS32 Release 5 Features"
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depends on SYS_HAS_CPU_MIPS32_R5
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depends on CPU_MIPS32_R2
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help
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Choose this option to build a kernel for release 2 or later of the
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MIPS32 architecture including features from release 5 such as
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support for Extended Physical Addressing (XPA).
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config CPU_MIPS32_R5_XPA
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bool "Extended Physical Addressing (XPA)"
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depends on CPU_MIPS32_R5_FEATURES
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depends on !EVA
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depends on !PAGE_SIZE_4KB
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depends on SYS_SUPPORTS_HIGHMEM
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select XPA
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select HIGHMEM
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select ARCH_PHYS_ADDR_T_64BIT
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default n
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help
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Choose this option if you want to enable the Extended Physical
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Addressing (XPA) on your MIPS32 core (such as P5600 series). The
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benefit is to increase physical addressing equal to or greater
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than 40 bits. Note that this has the side effect of turning on
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64-bit addressing which in turn makes the PTEs 64-bit in size.
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If unsure, say 'N' here.
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if CPU_LOONGSON2F
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config CPU_NOP_WORKAROUNDS
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bool
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@ -1699,6 +1728,9 @@ config SYS_HAS_CPU_MIPS32_R2
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config SYS_HAS_CPU_MIPS32_R3_5
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bool
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config SYS_HAS_CPU_MIPS32_R5
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bool
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config SYS_HAS_CPU_MIPS32_R6
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bool
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@ -1836,6 +1868,9 @@ config CPU_MIPSR6
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config EVA
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bool
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config XPA
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bool
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config SYS_SUPPORTS_32BIT_KERNEL
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bool
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config SYS_SUPPORTS_64BIT_KERNEL
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@ -139,6 +139,9 @@
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# endif
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#endif
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#ifndef cpu_has_xpa
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#define cpu_has_xpa (cpu_data[0].options & MIPS_CPU_XPA)
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#endif
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#ifndef cpu_has_vtag_icache
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#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
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#endif
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@ -377,6 +377,7 @@ enum cpu_type_enum {
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#define MIPS_CPU_MAAR 0x400000000ull /* MAAR(I) registers are present */
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#define MIPS_CPU_FRE 0x800000000ull /* FRE & UFE bits implemented */
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#define MIPS_CPU_RW_LLB 0x1000000000ull /* LLADDR/LLB writes are allowed */
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#define MIPS_CPU_XPA 0x2000000000ull /* CPU supports Extended Physical Addressing */
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/*
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* CPU ASE encodings
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@ -105,13 +105,16 @@ static inline void pmd_clear(pmd_t *pmdp)
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#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
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#define pte_page(x) pfn_to_page(pte_pfn(x))
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#define pte_pfn(x) ((unsigned long)((x).pte_high >> 6))
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#define pte_pfn(x) (((unsigned long)((x).pte_high >> _PFN_SHIFT)) | (unsigned long)((x).pte_low << _PAGE_PRESENT_SHIFT))
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static inline pte_t
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pfn_pte(unsigned long pfn, pgprot_t prot)
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{
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pte_t pte;
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pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f);
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pte.pte_low = pgprot_val(prot);
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pte.pte_low = (pfn >> _PAGE_PRESENT_SHIFT) |
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(pgprot_val(prot) & ~_PFNX_MASK);
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pte.pte_high = (pfn << _PFN_SHIFT) |
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(pgprot_val(prot) & ~_PFN_MASK);
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return pte;
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}
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@ -166,9 +169,9 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
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#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
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/* Swap entries must have VALID and GLOBAL bits cleared. */
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#define __swp_type(x) (((x).val >> 2) & 0x1f)
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#define __swp_offset(x) ((x).val >> 7)
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#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) | ((offset) << 7) })
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#define __swp_type(x) (((x).val >> 4) & 0x1f)
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#define __swp_offset(x) ((x).val >> 9)
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#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 4) | ((offset) << 9) })
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
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#define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val })
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@ -37,7 +37,11 @@
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/*
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* The following bits are implemented by the TLB hardware
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*/
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#define _PAGE_GLOBAL_SHIFT 0
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#define _PAGE_NO_EXEC_SHIFT 0
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#define _PAGE_NO_EXEC (1 << _PAGE_NO_EXEC_SHIFT)
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#define _PAGE_NO_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1)
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#define _PAGE_NO_READ (1 << _PAGE_NO_READ_SHIFT)
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#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1)
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#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
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#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
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#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
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@ -49,7 +53,7 @@
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/*
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* The following bits are implemented in software
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*/
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#define _PAGE_PRESENT_SHIFT (_CACHE_SHIFT + 3)
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#define _PAGE_PRESENT_SHIFT (24)
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#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
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#define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
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#define _PAGE_READ (1 << _PAGE_READ_SHIFT)
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@ -62,6 +66,11 @@
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#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
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/*
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* Bits for extended EntryLo0/EntryLo1 registers
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*/
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#define _PFNX_MASK 0xffffff
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#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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/*
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@ -133,7 +133,7 @@ extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
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#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
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#define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))
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#define pte_none(pte) (!(((pte).pte_high) & ~_PAGE_GLOBAL))
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#define pte_present(pte) ((pte).pte_low & _PAGE_PRESENT)
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static inline void set_pte(pte_t *ptep, pte_t pte)
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@ -142,16 +142,14 @@ static inline void set_pte(pte_t *ptep, pte_t pte)
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smp_wmb();
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ptep->pte_low = pte.pte_low;
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if (pte.pte_low & _PAGE_GLOBAL) {
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if (pte.pte_high & _PAGE_GLOBAL) {
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pte_t *buddy = ptep_buddy(ptep);
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/*
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* Make sure the buddy is global too (if it's !none,
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* it better already be global)
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*/
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if (pte_none(*buddy)) {
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buddy->pte_low |= _PAGE_GLOBAL;
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if (pte_none(*buddy))
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buddy->pte_high |= _PAGE_GLOBAL;
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}
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}
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}
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@ -161,8 +159,8 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt
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htw_stop();
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/* Preserve global status for the pair */
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if (ptep_buddy(ptep)->pte_low & _PAGE_GLOBAL)
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null.pte_low = null.pte_high = _PAGE_GLOBAL;
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if (ptep_buddy(ptep)->pte_high & _PAGE_GLOBAL)
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null.pte_high = _PAGE_GLOBAL;
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set_pte_at(mm, addr, ptep, null);
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htw_start();
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@ -242,21 +240,21 @@ static inline int pte_young(pte_t pte) { return pte.pte_low & _PAGE_ACCESSED; }
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static inline pte_t pte_wrprotect(pte_t pte)
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{
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pte.pte_low &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
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pte.pte_low &= ~_PAGE_WRITE;
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pte.pte_high &= ~_PAGE_SILENT_WRITE;
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return pte;
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}
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static inline pte_t pte_mkclean(pte_t pte)
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{
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pte.pte_low &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE);
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pte.pte_low &= ~_PAGE_MODIFIED;
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pte.pte_high &= ~_PAGE_SILENT_WRITE;
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return pte;
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}
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static inline pte_t pte_mkold(pte_t pte)
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{
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pte.pte_low &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ);
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pte.pte_low &= ~_PAGE_ACCESSED;
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pte.pte_high &= ~_PAGE_SILENT_READ;
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return pte;
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}
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@ -264,30 +262,24 @@ static inline pte_t pte_mkold(pte_t pte)
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static inline pte_t pte_mkwrite(pte_t pte)
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{
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pte.pte_low |= _PAGE_WRITE;
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if (pte.pte_low & _PAGE_MODIFIED) {
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pte.pte_low |= _PAGE_SILENT_WRITE;
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if (pte.pte_low & _PAGE_MODIFIED)
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pte.pte_high |= _PAGE_SILENT_WRITE;
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}
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return pte;
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}
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static inline pte_t pte_mkdirty(pte_t pte)
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{
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pte.pte_low |= _PAGE_MODIFIED;
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if (pte.pte_low & _PAGE_WRITE) {
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pte.pte_low |= _PAGE_SILENT_WRITE;
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if (pte.pte_low & _PAGE_WRITE)
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pte.pte_high |= _PAGE_SILENT_WRITE;
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}
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return pte;
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}
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static inline pte_t pte_mkyoung(pte_t pte)
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{
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pte.pte_low |= _PAGE_ACCESSED;
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if (pte.pte_low & _PAGE_READ) {
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pte.pte_low |= _PAGE_SILENT_READ;
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if (pte.pte_low & _PAGE_READ)
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pte.pte_high |= _PAGE_SILENT_READ;
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}
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return pte;
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}
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#else
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@ -391,10 +383,10 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
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#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
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static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
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{
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pte.pte_low &= _PAGE_CHG_MASK;
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pte.pte_low &= (_PAGE_MODIFIED | _PAGE_ACCESSED | _PFNX_MASK);
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pte.pte_high &= (_PFN_MASK | _CACHE_MASK);
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pte.pte_low |= pgprot_val(newprot);
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pte.pte_high |= pgprot_val(newprot) & ~(_PFN_MASK | _CACHE_MASK);
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pte.pte_low |= pgprot_val(newprot) & ~_PFNX_MASK;
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pte.pte_high |= pgprot_val(newprot) & ~_PFN_MASK;
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return pte;
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}
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#else
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@ -516,6 +516,10 @@ static inline unsigned int decode_config5(struct cpuinfo_mips *c)
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c->options |= MIPS_CPU_MAAR;
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if (config5 & MIPS_CONF5_LLB)
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c->options |= MIPS_CPU_RW_LLB;
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#ifdef CONFIG_XPA
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if (config5 & MIPS_CONF5_MVH)
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c->options |= MIPS_CPU_XPA;
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#endif
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return config5 & MIPS_CONF_M;
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}
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@ -120,6 +120,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
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if (cpu_has_msa) seq_printf(m, "%s", " msa");
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if (cpu_has_eva) seq_printf(m, "%s", " eva");
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if (cpu_has_htw) seq_printf(m, "%s", " htw");
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if (cpu_has_xpa) seq_printf(m, "%s", " xpa");
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seq_printf(m, "\n");
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if (cpu_has_mmips) {
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@ -96,7 +96,7 @@ static void *__kmap_pgprot(struct page *page, unsigned long addr, pgprot_t prot)
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vaddr = __fix_to_virt(FIX_CMAP_END - idx);
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pte = mk_pte(page, prot);
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#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
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entrylo = pte.pte_high;
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entrylo = pte_to_entrylo(pte.pte_high);
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#else
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entrylo = pte_to_entrylo(pte_val(pte));
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#endif
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@ -106,6 +106,11 @@ static void *__kmap_pgprot(struct page *page, unsigned long addr, pgprot_t prot)
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write_c0_entryhi(vaddr & (PAGE_MASK << 1));
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write_c0_entrylo0(entrylo);
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write_c0_entrylo1(entrylo);
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#ifdef CONFIG_XPA
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entrylo = (pte.pte_low & _PFNX_MASK);
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writex_c0_entrylo0(entrylo);
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writex_c0_entrylo1(entrylo);
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#endif
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tlbidx = read_c0_wired();
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write_c0_wired(tlbidx + 1);
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write_c0_index(tlbidx);
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@ -333,9 +333,17 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
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ptep = pte_offset_map(pmdp, address);
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#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
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#ifdef CONFIG_XPA
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write_c0_entrylo0(pte_to_entrylo(ptep->pte_high));
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writex_c0_entrylo0(ptep->pte_low & _PFNX_MASK);
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ptep++;
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write_c0_entrylo1(pte_to_entrylo(ptep->pte_high));
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writex_c0_entrylo1(ptep->pte_low & _PFNX_MASK);
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#else
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write_c0_entrylo0(ptep->pte_high);
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ptep++;
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write_c0_entrylo1(ptep->pte_high);
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#endif
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#else
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write_c0_entrylo0(pte_to_entrylo(pte_val(*ptep++)));
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write_c0_entrylo1(pte_to_entrylo(pte_val(*ptep)));
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@ -355,6 +363,9 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
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void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
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unsigned long entryhi, unsigned long pagemask)
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{
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#ifdef CONFIG_XPA
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panic("Broken for XPA kernels");
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#else
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unsigned long flags;
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unsigned long wired;
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unsigned long old_pagemask;
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@ -383,6 +394,7 @@ void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
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write_c0_pagemask(old_pagemask);
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local_flush_tlb_all();
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local_irq_restore(flags);
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#endif
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}
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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@ -35,6 +35,17 @@
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#include <asm/uasm.h>
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#include <asm/setup.h>
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static int __cpuinitdata mips_xpa_disabled;
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static int __init xpa_disable(char *s)
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{
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mips_xpa_disabled = 1;
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return 1;
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}
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__setup("noxpa", xpa_disable);
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/*
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* TLB load/store/modify handlers.
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*
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@ -1027,12 +1038,27 @@ static void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep)
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} else {
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int pte_off_even = sizeof(pte_t) / 2;
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int pte_off_odd = pte_off_even + sizeof(pte_t);
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#ifdef CONFIG_XPA
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const int scratch = 1; /* Our extra working register */
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/* The pte entries are pre-shifted */
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uasm_i_lw(p, tmp, pte_off_even, ptep); /* get even pte */
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UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
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uasm_i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */
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UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
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uasm_i_addu(p, scratch, 0, ptep);
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#endif
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uasm_i_lw(p, tmp, pte_off_even, ptep); /* even pte */
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uasm_i_lw(p, ptep, pte_off_odd, ptep); /* odd pte */
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UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
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UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL));
|
||||
UASM_i_MTC0(p, tmp, C0_ENTRYLO0);
|
||||
UASM_i_MTC0(p, ptep, C0_ENTRYLO1);
|
||||
#ifdef CONFIG_XPA
|
||||
uasm_i_lw(p, tmp, 0, scratch);
|
||||
uasm_i_lw(p, ptep, sizeof(pte_t), scratch);
|
||||
uasm_i_lui(p, scratch, 0xff);
|
||||
uasm_i_ori(p, scratch, scratch, 0xffff);
|
||||
uasm_i_and(p, tmp, scratch, tmp);
|
||||
uasm_i_and(p, ptep, scratch, ptep);
|
||||
uasm_i_mthc0(p, tmp, C0_ENTRYLO0);
|
||||
uasm_i_mthc0(p, ptep, C0_ENTRYLO1);
|
||||
#endif
|
||||
}
|
||||
#else
|
||||
UASM_i_LW(p, tmp, 0, ptep); /* get even pte */
|
||||
@ -1533,8 +1559,14 @@ iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
|
||||
{
|
||||
#ifdef CONFIG_PHYS_ADDR_T_64BIT
|
||||
unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
|
||||
#endif
|
||||
|
||||
if (!cpu_has_64bits) {
|
||||
const int scratch = 1; /* Our extra working register */
|
||||
|
||||
uasm_i_lui(p, scratch, (mode >> 16));
|
||||
uasm_i_or(p, pte, pte, scratch);
|
||||
} else
|
||||
#endif
|
||||
uasm_i_ori(p, pte, pte, mode);
|
||||
#ifdef CONFIG_SMP
|
||||
# ifdef CONFIG_PHYS_ADDR_T_64BIT
|
||||
@ -1598,15 +1630,17 @@ build_pte_present(u32 **p, struct uasm_reloc **r,
|
||||
uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid);
|
||||
uasm_i_nop(p);
|
||||
} else {
|
||||
uasm_i_andi(p, t, pte, _PAGE_PRESENT);
|
||||
uasm_i_srl(p, t, pte, _PAGE_PRESENT_SHIFT);
|
||||
uasm_i_andi(p, t, t, 1);
|
||||
uasm_il_beqz(p, r, t, lid);
|
||||
if (pte == t)
|
||||
/* You lose the SMP race :-(*/
|
||||
iPTE_LW(p, pte, ptr);
|
||||
}
|
||||
} else {
|
||||
uasm_i_andi(p, t, pte, _PAGE_PRESENT | _PAGE_READ);
|
||||
uasm_i_xori(p, t, t, _PAGE_PRESENT | _PAGE_READ);
|
||||
uasm_i_srl(p, t, pte, _PAGE_PRESENT_SHIFT);
|
||||
uasm_i_andi(p, t, t, 3);
|
||||
uasm_i_xori(p, t, t, 3);
|
||||
uasm_il_bnez(p, r, t, lid);
|
||||
if (pte == t)
|
||||
/* You lose the SMP race :-(*/
|
||||
@ -1635,8 +1669,9 @@ build_pte_writable(u32 **p, struct uasm_reloc **r,
|
||||
{
|
||||
int t = scratch >= 0 ? scratch : pte;
|
||||
|
||||
uasm_i_andi(p, t, pte, _PAGE_PRESENT | _PAGE_WRITE);
|
||||
uasm_i_xori(p, t, t, _PAGE_PRESENT | _PAGE_WRITE);
|
||||
uasm_i_srl(p, t, pte, _PAGE_PRESENT_SHIFT);
|
||||
uasm_i_andi(p, t, t, 5);
|
||||
uasm_i_xori(p, t, t, 5);
|
||||
uasm_il_bnez(p, r, t, lid);
|
||||
if (pte == t)
|
||||
/* You lose the SMP race :-(*/
|
||||
@ -1672,7 +1707,8 @@ build_pte_modifiable(u32 **p, struct uasm_reloc **r,
|
||||
uasm_i_nop(p);
|
||||
} else {
|
||||
int t = scratch >= 0 ? scratch : pte;
|
||||
uasm_i_andi(p, t, pte, _PAGE_WRITE);
|
||||
uasm_i_srl(p, t, pte, _PAGE_WRITE_SHIFT);
|
||||
uasm_i_andi(p, t, t, 1);
|
||||
uasm_il_beqz(p, r, t, lid);
|
||||
if (pte == t)
|
||||
/* You lose the SMP race :-(*/
|
||||
@ -2285,6 +2321,11 @@ static void config_htw_params(void)
|
||||
|
||||
pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT;
|
||||
pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT;
|
||||
|
||||
/* If XPA has been enabled, PTEs are 64-bit in size. */
|
||||
if (read_c0_pagegrain() & PG_ELPA)
|
||||
pwsize |= 1;
|
||||
|
||||
write_c0_pwsize(pwsize);
|
||||
|
||||
/* Make sure everything is set before we enable the HTW */
|
||||
@ -2298,6 +2339,28 @@ static void config_htw_params(void)
|
||||
print_htw_config();
|
||||
}
|
||||
|
||||
static void config_xpa_params(void)
|
||||
{
|
||||
#ifdef CONFIG_XPA
|
||||
unsigned int pagegrain;
|
||||
|
||||
if (mips_xpa_disabled) {
|
||||
pr_info("Extended Physical Addressing (XPA) disabled\n");
|
||||
return;
|
||||
}
|
||||
|
||||
pagegrain = read_c0_pagegrain();
|
||||
write_c0_pagegrain(pagegrain | PG_ELPA);
|
||||
back_to_back_c0_hazard();
|
||||
pagegrain = read_c0_pagegrain();
|
||||
|
||||
if (pagegrain & PG_ELPA)
|
||||
pr_info("Extended Physical Addressing (XPA) enabled\n");
|
||||
else
|
||||
panic("Extended Physical Addressing (XPA) disabled");
|
||||
#endif
|
||||
}
|
||||
|
||||
void build_tlb_refill_handler(void)
|
||||
{
|
||||
/*
|
||||
@ -2362,8 +2425,9 @@ void build_tlb_refill_handler(void)
|
||||
}
|
||||
if (cpu_has_local_ebase)
|
||||
build_r4000_tlb_refill_handler();
|
||||
if (cpu_has_xpa)
|
||||
config_xpa_params();
|
||||
if (cpu_has_htw)
|
||||
config_htw_params();
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user