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MIPS: OCTEON: Update register definitions.

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Add support for cn68xx, cn61xx, cn63xx, cn66xx and cnf71XX.

Add little-endian register layouts.

Patch cvmx-interrupt-rsl.c for changed definition.

Signed-off-by: David Daney <david.daney@cavium.com>
This commit is contained in:
David Daney 2012-04-03 13:44:18 -07:00
parent 5cf02e5554
commit c5aa59e88f
38 changed files with 43234 additions and 1412 deletions
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2
arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c
View File

@ -130,7 +130,7 @@ void __cvmx_interrupt_gmxx_enable(int interface)
if (num_ports) {
if (OCTEON_IS_MODEL(OCTEON_CN38XX)
|| OCTEON_IS_MODEL(OCTEON_CN58XX))
gmx_tx_int_en.s.ncb_nxa = 1;
gmx_tx_int_en.cn38xx.ncb_nxa = 1;
gmx_tx_int_en.s.pko_nxa = 1;
}
gmx_tx_int_en.s.undflw = (1 << num_ports) - 1;

1014
arch/mips/include/asm/octeon/cvmx-agl-defs.h
View File

File diff suppressed because it is too large Load Diff

300
arch/mips/include/asm/octeon/cvmx-asxx-defs.h
View File

@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2008 Cavium Networks
* Copyright (c) 2003-2012 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@ -28,64 +28,43 @@
#ifndef __CVMX_ASXX_DEFS_H__
#define __CVMX_ASXX_DEFS_H__
#define CVMX_ASXX_GMII_RX_CLK_SET(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000180ull + (((block_id) & 0) * 0x8000000ull))
#define CVMX_ASXX_GMII_RX_DAT_SET(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000188ull + (((block_id) & 0) * 0x8000000ull))
#define CVMX_ASXX_INT_EN(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000018ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_INT_REG(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000010ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_MII_RX_DAT_SET(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000190ull + (((block_id) & 0) * 0x8000000ull))
#define CVMX_ASXX_PRT_LOOP(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000040ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RLD_BYPASS(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000248ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000250ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RLD_COMP(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000220ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RLD_DATA_DRV(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000218ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RLD_FCRAM_MODE(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000210ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RLD_NCTL_STRONG(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000230ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RLD_NCTL_WEAK(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000240ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RLD_PCTL_STRONG(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000228ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RLD_PCTL_WEAK(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000238ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RLD_SETTING(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000258ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000020ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RX_PRT_EN(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000000ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RX_WOL(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000100ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RX_WOL_MSK(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000108ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RX_WOL_POWOK(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000118ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RX_WOL_SIG(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000110ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000048ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_TX_COMP_BYP(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000068ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000080ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_TX_PRT_EN(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000008ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_GMII_RX_CLK_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000180ull))
#define CVMX_ASXX_GMII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000188ull))
#define CVMX_ASXX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_ASXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_ASXX_MII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000190ull))
#define CVMX_ASXX_PRT_LOOP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000040ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_ASXX_RLD_BYPASS(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000248ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000250ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_ASXX_RLD_COMP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000220ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_ASXX_RLD_DATA_DRV(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000218ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_ASXX_RLD_FCRAM_MODE(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000210ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_ASXX_RLD_NCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000230ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_ASXX_RLD_NCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000240ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_ASXX_RLD_PCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000228ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_ASXX_RLD_PCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000238ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_ASXX_RLD_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000258ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
#define CVMX_ASXX_RX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000000ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_ASXX_RX_WOL(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000100ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_ASXX_RX_WOL_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000108ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_ASXX_RX_WOL_POWOK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000118ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_ASXX_RX_WOL_SIG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000110ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
#define CVMX_ASXX_TX_COMP_BYP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000068ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
#define CVMX_ASXX_TX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull)
union cvmx_asxx_gmii_rx_clk_set {
uint64_t u64;
struct cvmx_asxx_gmii_rx_clk_set_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63:59;
uint64_t setting:5;
#else
uint64_t setting:5;
uint64_t reserved_5_63:59;
#endif
} s;
struct cvmx_asxx_gmii_rx_clk_set_s cn30xx;
struct cvmx_asxx_gmii_rx_clk_set_s cn31xx;
@ -95,8 +74,13 @@ union cvmx_asxx_gmii_rx_clk_set {
union cvmx_asxx_gmii_rx_dat_set {
uint64_t u64;
struct cvmx_asxx_gmii_rx_dat_set_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63:59;
uint64_t setting:5;
#else
uint64_t setting:5;
uint64_t reserved_5_63:59;
#endif
} s;
struct cvmx_asxx_gmii_rx_dat_set_s cn30xx;
struct cvmx_asxx_gmii_rx_dat_set_s cn31xx;
@ -106,18 +90,34 @@ union cvmx_asxx_gmii_rx_dat_set {
union cvmx_asxx_int_en {
uint64_t u64;
struct cvmx_asxx_int_en_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63:52;
uint64_t txpsh:4;
uint64_t txpop:4;
uint64_t ovrflw:4;
#else
uint64_t ovrflw:4;
uint64_t txpop:4;
uint64_t txpsh:4;
uint64_t reserved_12_63:52;
#endif
} s;
struct cvmx_asxx_int_en_cn30xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_11_63:53;
uint64_t txpsh:3;
uint64_t reserved_7_7:1;
uint64_t txpop:3;
uint64_t reserved_3_3:1;
uint64_t ovrflw:3;
#else
uint64_t ovrflw:3;
uint64_t reserved_3_3:1;
uint64_t txpop:3;
uint64_t reserved_7_7:1;
uint64_t txpsh:3;
uint64_t reserved_11_63:53;
#endif
} cn30xx;
struct cvmx_asxx_int_en_cn30xx cn31xx;
struct cvmx_asxx_int_en_s cn38xx;
@ -130,18 +130,34 @@ union cvmx_asxx_int_en {
union cvmx_asxx_int_reg {
uint64_t u64;
struct cvmx_asxx_int_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63:52;
uint64_t txpsh:4;
uint64_t txpop:4;
uint64_t ovrflw:4;
#else
uint64_t ovrflw:4;
uint64_t txpop:4;
uint64_t txpsh:4;
uint64_t reserved_12_63:52;
#endif
} s;
struct cvmx_asxx_int_reg_cn30xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_11_63:53;
uint64_t txpsh:3;
uint64_t reserved_7_7:1;
uint64_t txpop:3;
uint64_t reserved_3_3:1;
uint64_t ovrflw:3;
#else
uint64_t ovrflw:3;
uint64_t reserved_3_3:1;
uint64_t txpop:3;
uint64_t reserved_7_7:1;
uint64_t txpsh:3;
uint64_t reserved_11_63:53;
#endif
} cn30xx;
struct cvmx_asxx_int_reg_cn30xx cn31xx;
struct cvmx_asxx_int_reg_s cn38xx;
@ -154,8 +170,13 @@ union cvmx_asxx_int_reg {
union cvmx_asxx_mii_rx_dat_set {
uint64_t u64;
struct cvmx_asxx_mii_rx_dat_set_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63:59;
uint64_t setting:5;
#else
uint64_t setting:5;
uint64_t reserved_5_63:59;
#endif
} s;
struct cvmx_asxx_mii_rx_dat_set_s cn30xx;
struct cvmx_asxx_mii_rx_dat_set_s cn50xx;
@ -164,15 +185,28 @@ union cvmx_asxx_mii_rx_dat_set {
union cvmx_asxx_prt_loop {
uint64_t u64;
struct cvmx_asxx_prt_loop_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63:56;
uint64_t ext_loop:4;
uint64_t int_loop:4;
#else
uint64_t int_loop:4;
uint64_t ext_loop:4;
uint64_t reserved_8_63:56;
#endif
} s;
struct cvmx_asxx_prt_loop_cn30xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_7_63:57;
uint64_t ext_loop:3;
uint64_t reserved_3_3:1;
uint64_t int_loop:3;
#else
uint64_t int_loop:3;
uint64_t reserved_3_3:1;
uint64_t ext_loop:3;
uint64_t reserved_7_63:57;
#endif
} cn30xx;
struct cvmx_asxx_prt_loop_cn30xx cn31xx;
struct cvmx_asxx_prt_loop_s cn38xx;
@ -185,8 +219,13 @@ union cvmx_asxx_prt_loop {
union cvmx_asxx_rld_bypass {
uint64_t u64;
struct cvmx_asxx_rld_bypass_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63:63;
uint64_t bypass:1;
#else
uint64_t bypass:1;
uint64_t reserved_1_63:63;
#endif
} s;
struct cvmx_asxx_rld_bypass_s cn38xx;
struct cvmx_asxx_rld_bypass_s cn38xxp2;
@ -197,8 +236,13 @@ union cvmx_asxx_rld_bypass {
union cvmx_asxx_rld_bypass_setting {
uint64_t u64;
struct cvmx_asxx_rld_bypass_setting_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63:59;
uint64_t setting:5;
#else
uint64_t setting:5;
uint64_t reserved_5_63:59;
#endif
} s;
struct cvmx_asxx_rld_bypass_setting_s cn38xx;
struct cvmx_asxx_rld_bypass_setting_s cn38xxp2;
@ -209,14 +253,26 @@ union cvmx_asxx_rld_bypass_setting {
union cvmx_asxx_rld_comp {
uint64_t u64;
struct cvmx_asxx_rld_comp_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_9_63:55;
uint64_t pctl:5;
uint64_t nctl:4;
#else
uint64_t nctl:4;
uint64_t pctl:5;
uint64_t reserved_9_63:55;
#endif
} s;
struct cvmx_asxx_rld_comp_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63:56;
uint64_t pctl:4;
uint64_t nctl:4;
#else
uint64_t nctl:4;
uint64_t pctl:4;
uint64_t reserved_8_63:56;
#endif
} cn38xx;
struct cvmx_asxx_rld_comp_cn38xx cn38xxp2;
struct cvmx_asxx_rld_comp_s cn58xx;
@ -226,9 +282,15 @@ union cvmx_asxx_rld_comp {
union cvmx_asxx_rld_data_drv {
uint64_t u64;
struct cvmx_asxx_rld_data_drv_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63:56;
uint64_t pctl:4;
uint64_t nctl:4;
#else
uint64_t nctl:4;
uint64_t pctl:4;
uint64_t reserved_8_63:56;
#endif
} s;
struct cvmx_asxx_rld_data_drv_s cn38xx;
struct cvmx_asxx_rld_data_drv_s cn38xxp2;
@ -239,8 +301,13 @@ union cvmx_asxx_rld_data_drv {
union cvmx_asxx_rld_fcram_mode {
uint64_t u64;
struct cvmx_asxx_rld_fcram_mode_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63:63;
uint64_t mode:1;
#else
uint64_t mode:1;
uint64_t reserved_1_63:63;
#endif
} s;
struct cvmx_asxx_rld_fcram_mode_s cn38xx;
struct cvmx_asxx_rld_fcram_mode_s cn38xxp2;
@ -249,8 +316,13 @@ union cvmx_asxx_rld_fcram_mode {
union cvmx_asxx_rld_nctl_strong {
uint64_t u64;
struct cvmx_asxx_rld_nctl_strong_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63:59;
uint64_t nctl:5;
#else
uint64_t nctl:5;
uint64_t reserved_5_63:59;
#endif
} s;
struct cvmx_asxx_rld_nctl_strong_s cn38xx;
struct cvmx_asxx_rld_nctl_strong_s cn38xxp2;
@ -261,8 +333,13 @@ union cvmx_asxx_rld_nctl_strong {
union cvmx_asxx_rld_nctl_weak {
uint64_t u64;
struct cvmx_asxx_rld_nctl_weak_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63:59;
uint64_t nctl:5;
#else
uint64_t nctl:5;
uint64_t reserved_5_63:59;
#endif
} s;
struct cvmx_asxx_rld_nctl_weak_s cn38xx;
struct cvmx_asxx_rld_nctl_weak_s cn38xxp2;
@ -273,8 +350,13 @@ union cvmx_asxx_rld_nctl_weak {
union cvmx_asxx_rld_pctl_strong {
uint64_t u64;
struct cvmx_asxx_rld_pctl_strong_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63:59;
uint64_t pctl:5;
#else
uint64_t pctl:5;
uint64_t reserved_5_63:59;
#endif
} s;
struct cvmx_asxx_rld_pctl_strong_s cn38xx;
struct cvmx_asxx_rld_pctl_strong_s cn38xxp2;
@ -285,8 +367,13 @@ union cvmx_asxx_rld_pctl_strong {
union cvmx_asxx_rld_pctl_weak {
uint64_t u64;
struct cvmx_asxx_rld_pctl_weak_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63:59;
uint64_t pctl:5;
#else
uint64_t pctl:5;
uint64_t reserved_5_63:59;
#endif
} s;
struct cvmx_asxx_rld_pctl_weak_s cn38xx;
struct cvmx_asxx_rld_pctl_weak_s cn38xxp2;
@ -297,16 +384,30 @@ union cvmx_asxx_rld_pctl_weak {
union cvmx_asxx_rld_setting {
uint64_t u64;
struct cvmx_asxx_rld_setting_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_13_63:51;
uint64_t dfaset:5;
uint64_t dfalag:1;
uint64_t dfalead:1;
uint64_t dfalock:1;
uint64_t setting:5;
#else
uint64_t setting:5;
uint64_t dfalock:1;
uint64_t dfalead:1;
uint64_t dfalag:1;
uint64_t dfaset:5;
uint64_t reserved_13_63:51;
#endif
} s;
struct cvmx_asxx_rld_setting_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63:59;
uint64_t setting:5;
#else
uint64_t setting:5;
uint64_t reserved_5_63:59;
#endif
} cn38xx;
struct cvmx_asxx_rld_setting_cn38xx cn38xxp2;
struct cvmx_asxx_rld_setting_s cn58xx;
@ -316,8 +417,13 @@ union cvmx_asxx_rld_setting {
union cvmx_asxx_rx_clk_setx {
uint64_t u64;
struct cvmx_asxx_rx_clk_setx_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63:59;
uint64_t setting:5;
#else
uint64_t setting:5;
uint64_t reserved_5_63:59;
#endif
} s;
struct cvmx_asxx_rx_clk_setx_s cn30xx;
struct cvmx_asxx_rx_clk_setx_s cn31xx;
@ -331,12 +437,22 @@ union cvmx_asxx_rx_clk_setx {
union cvmx_asxx_rx_prt_en {
uint64_t u64;
struct cvmx_asxx_rx_prt_en_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63:60;
uint64_t prt_en:4;
#else
uint64_t prt_en:4;
uint64_t reserved_4_63:60;
#endif
} s;
struct cvmx_asxx_rx_prt_en_cn30xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_3_63:61;
uint64_t prt_en:3;
#else
uint64_t prt_en:3;
uint64_t reserved_3_63:61;
#endif
} cn30xx;
struct cvmx_asxx_rx_prt_en_cn30xx cn31xx;
struct cvmx_asxx_rx_prt_en_s cn38xx;
@ -349,9 +465,15 @@ union cvmx_asxx_rx_prt_en {
union cvmx_asxx_rx_wol {
uint64_t u64;
struct cvmx_asxx_rx_wol_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63:62;
uint64_t status:1;
uint64_t enable:1;
#else
uint64_t enable:1;
uint64_t status:1;
uint64_t reserved_2_63:62;
#endif
} s;
struct cvmx_asxx_rx_wol_s cn38xx;
struct cvmx_asxx_rx_wol_s cn38xxp2;
@ -360,7 +482,11 @@ union cvmx_asxx_rx_wol {
union cvmx_asxx_rx_wol_msk {
uint64_t u64;
struct cvmx_asxx_rx_wol_msk_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t msk:64;
#else
uint64_t msk:64;
#endif
} s;
struct cvmx_asxx_rx_wol_msk_s cn38xx;
struct cvmx_asxx_rx_wol_msk_s cn38xxp2;
@ -369,8 +495,13 @@ union cvmx_asxx_rx_wol_msk {
union cvmx_asxx_rx_wol_powok {
uint64_t u64;
struct cvmx_asxx_rx_wol_powok_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63:63;
uint64_t powerok:1;
#else
uint64_t powerok:1;
uint64_t reserved_1_63:63;
#endif
} s;
struct cvmx_asxx_rx_wol_powok_s cn38xx;
struct cvmx_asxx_rx_wol_powok_s cn38xxp2;
@ -379,8 +510,13 @@ union cvmx_asxx_rx_wol_powok {
union cvmx_asxx_rx_wol_sig {
uint64_t u64;
struct cvmx_asxx_rx_wol_sig_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
uint64_t sig:32;
#else
uint64_t sig:32;
uint64_t reserved_32_63:32;
#endif
} s;
struct cvmx_asxx_rx_wol_sig_s cn38xx;
struct cvmx_asxx_rx_wol_sig_s cn38xxp2;
@ -389,8 +525,13 @@ union cvmx_asxx_rx_wol_sig {
union cvmx_asxx_tx_clk_setx {
uint64_t u64;
struct cvmx_asxx_tx_clk_setx_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63:59;
uint64_t setting:5;
#else
uint64_t setting:5;
uint64_t reserved_5_63:59;
#endif
} s;
struct cvmx_asxx_tx_clk_setx_s cn30xx;
struct cvmx_asxx_tx_clk_setx_s cn31xx;
@ -404,34 +545,67 @@ union cvmx_asxx_tx_clk_setx {
union cvmx_asxx_tx_comp_byp {
uint64_t u64;
struct cvmx_asxx_tx_comp_byp_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_0_63:64;
#else
uint64_t reserved_0_63:64;
#endif
} s;
struct cvmx_asxx_tx_comp_byp_cn30xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_9_63:55;
uint64_t bypass:1;
uint64_t pctl:4;
uint64_t nctl:4;
#else
uint64_t nctl:4;
uint64_t pctl:4;
uint64_t bypass:1;
uint64_t reserved_9_63:55;
#endif
} cn30xx;
struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx;
struct cvmx_asxx_tx_comp_byp_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63:56;
uint64_t pctl:4;
uint64_t nctl:4;
#else
uint64_t nctl:4;
uint64_t pctl:4;
uint64_t reserved_8_63:56;
#endif
} cn38xx;
struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2;
struct cvmx_asxx_tx_comp_byp_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_17_63:47;
uint64_t bypass:1;
uint64_t reserved_13_15:3;
uint64_t pctl:5;
uint64_t reserved_5_7:3;
uint64_t nctl:5;
#else
uint64_t nctl:5;
uint64_t reserved_5_7:3;
uint64_t pctl:5;
uint64_t reserved_13_15:3;
uint64_t bypass:1;
uint64_t reserved_17_63:47;
#endif
} cn50xx;
struct cvmx_asxx_tx_comp_byp_cn58xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_13_63:51;
uint64_t pctl:5;
uint64_t reserved_5_7:3;
uint64_t nctl:5;
#else
uint64_t nctl:5;
uint64_t reserved_5_7:3;
uint64_t pctl:5;
uint64_t reserved_13_63:51;
#endif
} cn58xx;
struct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1;
};
@ -439,12 +613,22 @@ union cvmx_asxx_tx_comp_byp {
union cvmx_asxx_tx_hi_waterx {
uint64_t u64;
struct cvmx_asxx_tx_hi_waterx_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63:60;
uint64_t mark:4;
#else
uint64_t mark:4;
uint64_t reserved_4_63:60;
#endif
} s;
struct cvmx_asxx_tx_hi_waterx_cn30xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_3_63:61;
uint64_t mark:3;
#else
uint64_t mark:3;
uint64_t reserved_3_63:61;
#endif
} cn30xx;
struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx;
struct cvmx_asxx_tx_hi_waterx_s cn38xx;
@ -457,12 +641,22 @@ union cvmx_asxx_tx_hi_waterx {
union cvmx_asxx_tx_prt_en {
uint64_t u64;
struct cvmx_asxx_tx_prt_en_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63:60;
uint64_t prt_en:4;
#else
uint64_t prt_en:4;
uint64_t reserved_4_63:60;
#endif
} s;
struct cvmx_asxx_tx_prt_en_cn30xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_3_63:61;
uint64_t prt_en:3;
#else
uint64_t prt_en:3;
uint64_t reserved_3_63:61;
#endif
} cn30xx;
struct cvmx_asxx_tx_prt_en_cn30xx cn31xx;
struct cvmx_asxx_tx_prt_en_s cn38xx;

7883
arch/mips/include/asm/octeon/cvmx-ciu-defs.h
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File diff suppressed because it is too large Load Diff

7108
arch/mips/include/asm/octeon/cvmx-ciu2-defs.h Normal file
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File diff suppressed because it is too large Load Diff

39
arch/mips/include/asm/octeon/cvmx-dbg-defs.h
View File

@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2008 Cavium Networks
* Copyright (c) 2003-2012 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@ -28,27 +28,43 @@
#ifndef __CVMX_DBG_DEFS_H__
#define __CVMX_DBG_DEFS_H__
#define CVMX_DBG_DATA \
CVMX_ADD_IO_SEG(0x00011F00000001E8ull)
#define CVMX_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F00000001E8ull))
union cvmx_dbg_data {
uint64_t u64;
struct cvmx_dbg_data_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_23_63:41;
uint64_t c_mul:5;
uint64_t dsel_ext:1;
uint64_t data:17;
#else
uint64_t data:17;
uint64_t dsel_ext:1;
uint64_t c_mul:5;
uint64_t reserved_23_63:41;
#endif
} s;
struct cvmx_dbg_data_cn30xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_31_63:33;
uint64_t pll_mul:3;
uint64_t reserved_23_27:5;
uint64_t c_mul:5;
uint64_t dsel_ext:1;
uint64_t data:17;
#else
uint64_t data:17;
uint64_t dsel_ext:1;
uint64_t c_mul:5;
uint64_t reserved_23_27:5;
uint64_t pll_mul:3;
uint64_t reserved_31_63:33;
#endif
} cn30xx;
struct cvmx_dbg_data_cn30xx cn31xx;
struct cvmx_dbg_data_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_29_63:35;
uint64_t d_mul:4;
uint64_t dclk_mul2:1;
@ -56,15 +72,32 @@ union cvmx_dbg_data {
uint64_t c_mul:5;
uint64_t dsel_ext:1;
uint64_t data:17;
#else
uint64_t data:17;
uint64_t dsel_ext:1;
uint64_t c_mul:5;
uint64_t cclk_div2:1;
uint64_t dclk_mul2:1;
uint64_t d_mul:4;
uint64_t reserved_29_63:35;
#endif
} cn38xx;
struct cvmx_dbg_data_cn38xx cn38xxp2;
struct cvmx_dbg_data_cn30xx cn50xx;
struct cvmx_dbg_data_cn58xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_29_63:35;
uint64_t rem:6;
uint64_t c_mul:5;
uint64_t dsel_ext:1;
uint64_t data:17;
#else
uint64_t data:17;
uint64_t dsel_ext:1;
uint64_t c_mul:5;
uint64_t rem:6;
uint64_t reserved_29_63:35;
#endif
} cn58xx;
struct cvmx_dbg_data_cn58xx cn58xxp1;
};

411
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
View File

@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2011 Cavium Networks
* Copyright (c) 2003-2012 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@ -55,52 +55,107 @@
#define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull))
#define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull))
#define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8)
static inline uint64_t CVMX_DPI_SLI_PRTX_ERR(unsigned long offset)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1))
return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8;
if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2))
return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8;
}
return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
}
#define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8)
union cvmx_dpi_bist_status {
uint64_t u64;
struct cvmx_dpi_bist_status_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_47_63:17;
uint64_t bist:47;
#else
uint64_t bist:47;
uint64_t reserved_47_63:17;
#endif
} s;
struct cvmx_dpi_bist_status_s cn61xx;
struct cvmx_dpi_bist_status_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_45_63:19;
uint64_t bist:45;
#else
uint64_t bist:45;
uint64_t reserved_45_63:19;
#endif
} cn63xx;
struct cvmx_dpi_bist_status_cn63xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_37_63:27;
uint64_t bist:37;
#else
uint64_t bist:37;
uint64_t reserved_37_63:27;
#endif
} cn63xxp1;
struct cvmx_dpi_bist_status_s cn66xx;
struct cvmx_dpi_bist_status_cn63xx cn68xx;
struct cvmx_dpi_bist_status_cn63xx cn68xxp1;
struct cvmx_dpi_bist_status_s cnf71xx;
};
union cvmx_dpi_ctl {
uint64_t u64;
struct cvmx_dpi_ctl_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63:62;
uint64_t clk:1;
uint64_t en:1;
#else
uint64_t en:1;
uint64_t clk:1;
uint64_t reserved_2_63:62;
#endif
} s;
struct cvmx_dpi_ctl_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63:63;
uint64_t en:1;
#else
uint64_t en:1;
uint64_t reserved_1_63:63;
#endif
} cn61xx;
struct cvmx_dpi_ctl_s cn63xx;
struct cvmx_dpi_ctl_s cn63xxp1;
struct cvmx_dpi_ctl_s cn66xx;
struct cvmx_dpi_ctl_s cn68xx;
struct cvmx_dpi_ctl_s cn68xxp1;
struct cvmx_dpi_ctl_cn61xx cnf71xx;
};
union cvmx_dpi_dmax_counts {
uint64_t u64;
struct cvmx_dpi_dmax_counts_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_39_63:25;
uint64_t fcnt:7;
uint64_t dbell:32;
#else
uint64_t dbell:32;
uint64_t fcnt:7;
uint64_t reserved_39_63:25;
#endif
} s;
struct cvmx_dpi_dmax_counts_s cn61xx;
struct cvmx_dpi_dmax_counts_s cn63xx;
@ -108,13 +163,19 @@ union cvmx_dpi_dmax_counts {
struct cvmx_dpi_dmax_counts_s cn66xx;
struct cvmx_dpi_dmax_counts_s cn68xx;
struct cvmx_dpi_dmax_counts_s cn68xxp1;
struct cvmx_dpi_dmax_counts_s cnf71xx;
};
union cvmx_dpi_dmax_dbell {
uint64_t u64;
struct cvmx_dpi_dmax_dbell_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t dbell:16;
#else
uint64_t dbell:16;
uint64_t reserved_16_63:48;
#endif
} s;
struct cvmx_dpi_dmax_dbell_s cn61xx;
struct cvmx_dpi_dmax_dbell_s cn63xx;
@ -122,31 +183,48 @@ union cvmx_dpi_dmax_dbell {
struct cvmx_dpi_dmax_dbell_s cn66xx;
struct cvmx_dpi_dmax_dbell_s cn68xx;
struct cvmx_dpi_dmax_dbell_s cn68xxp1;
struct cvmx_dpi_dmax_dbell_s cnf71xx;
};
union cvmx_dpi_dmax_err_rsp_status {
uint64_t u64;
struct cvmx_dpi_dmax_err_rsp_status_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_6_63:58;
uint64_t status:6;
#else
uint64_t status:6;
uint64_t reserved_6_63:58;
#endif
} s;
struct cvmx_dpi_dmax_err_rsp_status_s cn61xx;
struct cvmx_dpi_dmax_err_rsp_status_s cn66xx;
struct cvmx_dpi_dmax_err_rsp_status_s cn68xx;
struct cvmx_dpi_dmax_err_rsp_status_s cn68xxp1;
struct cvmx_dpi_dmax_err_rsp_status_s cnf71xx;
};
union cvmx_dpi_dmax_ibuff_saddr {
uint64_t u64;
struct cvmx_dpi_dmax_ibuff_saddr_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_62_63:2;
uint64_t csize:14;
uint64_t reserved_41_47:7;
uint64_t idle:1;
uint64_t saddr:33;
uint64_t reserved_0_6:7;
#else
uint64_t reserved_0_6:7;
uint64_t saddr:33;
uint64_t idle:1;
uint64_t reserved_41_47:7;
uint64_t csize:14;
uint64_t reserved_62_63:2;
#endif
} s;
struct cvmx_dpi_dmax_ibuff_saddr_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_62_63:2;
uint64_t csize:14;
uint64_t reserved_41_47:7;
@ -154,47 +232,78 @@ union cvmx_dpi_dmax_ibuff_saddr {
uint64_t reserved_36_39:4;
uint64_t saddr:29;
uint64_t reserved_0_6:7;
#else
uint64_t reserved_0_6:7;
uint64_t saddr:29;
uint64_t reserved_36_39:4;
uint64_t idle:1;
uint64_t reserved_41_47:7;
uint64_t csize:14;
uint64_t reserved_62_63:2;
#endif
} cn61xx;
struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xx;
struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xxp1;
struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn66xx;
struct cvmx_dpi_dmax_ibuff_saddr_s cn68xx;
struct cvmx_dpi_dmax_ibuff_saddr_s cn68xxp1;
struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cnf71xx;
};
union cvmx_dpi_dmax_iflight {
uint64_t u64;
struct cvmx_dpi_dmax_iflight_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_3_63:61;
uint64_t cnt:3;
#else
uint64_t cnt:3;
uint64_t reserved_3_63:61;
#endif
} s;
struct cvmx_dpi_dmax_iflight_s cn61xx;
struct cvmx_dpi_dmax_iflight_s cn66xx;
struct cvmx_dpi_dmax_iflight_s cn68xx;
struct cvmx_dpi_dmax_iflight_s cn68xxp1;
struct cvmx_dpi_dmax_iflight_s cnf71xx;
};
union cvmx_dpi_dmax_naddr {
uint64_t u64;
struct cvmx_dpi_dmax_naddr_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_40_63:24;
uint64_t addr:40;
#else
uint64_t addr:40;
uint64_t reserved_40_63:24;
#endif
} s;
struct cvmx_dpi_dmax_naddr_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_36_63:28;
uint64_t addr:36;
#else
uint64_t addr:36;
uint64_t reserved_36_63:28;
#endif
} cn61xx;
struct cvmx_dpi_dmax_naddr_cn61xx cn63xx;
struct cvmx_dpi_dmax_naddr_cn61xx cn63xxp1;
struct cvmx_dpi_dmax_naddr_cn61xx cn66xx;
struct cvmx_dpi_dmax_naddr_s cn68xx;
struct cvmx_dpi_dmax_naddr_s cn68xxp1;
struct cvmx_dpi_dmax_naddr_cn61xx cnf71xx;
};
union cvmx_dpi_dmax_reqbnk0 {
uint64_t u64;
struct cvmx_dpi_dmax_reqbnk0_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t state:64;
#else
uint64_t state:64;
#endif
} s;
struct cvmx_dpi_dmax_reqbnk0_s cn61xx;
struct cvmx_dpi_dmax_reqbnk0_s cn63xx;
@ -202,12 +311,17 @@ union cvmx_dpi_dmax_reqbnk0 {
struct cvmx_dpi_dmax_reqbnk0_s cn66xx;
struct cvmx_dpi_dmax_reqbnk0_s cn68xx;
struct cvmx_dpi_dmax_reqbnk0_s cn68xxp1;
struct cvmx_dpi_dmax_reqbnk0_s cnf71xx;
};
union cvmx_dpi_dmax_reqbnk1 {
uint64_t u64;
struct cvmx_dpi_dmax_reqbnk1_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t state:64;
#else
uint64_t state:64;
#endif
} s;
struct cvmx_dpi_dmax_reqbnk1_s cn61xx;
struct cvmx_dpi_dmax_reqbnk1_s cn63xx;
@ -215,11 +329,13 @@ union cvmx_dpi_dmax_reqbnk1 {
struct cvmx_dpi_dmax_reqbnk1_s cn66xx;
struct cvmx_dpi_dmax_reqbnk1_s cn68xx;
struct cvmx_dpi_dmax_reqbnk1_s cn68xxp1;
struct cvmx_dpi_dmax_reqbnk1_s cnf71xx;
};
union cvmx_dpi_dma_control {
uint64_t u64;
struct cvmx_dpi_dma_control_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_62_63:2;
uint64_t dici_mode:1;
uint64_t pkt_en1:1;
@ -240,9 +356,32 @@ union cvmx_dpi_dma_control {
uint64_t o_es:2;
uint64_t o_mode:1;
uint64_t reserved_0_13:14;
#else
uint64_t reserved_0_13:14;
uint64_t o_mode:1;
uint64_t o_es:2;
uint64_t o_ns:1;
uint64_t o_ro:1;
uint64_t o_add1:1;
uint64_t fpa_que:3;
uint64_t dwb_ichk:9;
uint64_t dwb_denb:1;
uint64_t b0_lend:1;
uint64_t reserved_34_47:14;
uint64_t dma_enb:6;
uint64_t reserved_54_55:2;
uint64_t pkt_en:1;
uint64_t pkt_hp:1;
uint64_t commit_mode:1;
uint64_t ffp_dis:1;
uint64_t pkt_en1:1;
uint64_t dici_mode:1;
uint64_t reserved_62_63:2;
#endif
} s;
struct cvmx_dpi_dma_control_s cn61xx;
struct cvmx_dpi_dma_control_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_61_63:3;
uint64_t pkt_en1:1;
uint64_t ffp_dis:1;
@ -262,8 +401,30 @@ union cvmx_dpi_dma_control {
uint64_t o_es:2;
uint64_t o_mode:1;
uint64_t reserved_0_13:14;
#else
uint64_t reserved_0_13:14;
uint64_t o_mode:1;
uint64_t o_es:2;
uint64_t o_ns:1;
uint64_t o_ro:1;
uint64_t o_add1:1;
uint64_t fpa_que:3;
uint64_t dwb_ichk:9;
uint64_t dwb_denb:1;
uint64_t b0_lend:1;
uint64_t reserved_34_47:14;
uint64_t dma_enb:6;
uint64_t reserved_54_55:2;
uint64_t pkt_en:1;
uint64_t pkt_hp:1;
uint64_t commit_mode:1;
uint64_t ffp_dis:1;
uint64_t pkt_en1:1;
uint64_t reserved_61_63:3;
#endif
} cn63xx;
struct cvmx_dpi_dma_control_cn63xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_59_63:5;
uint64_t commit_mode:1;
uint64_t pkt_hp:1;
@ -281,17 +442,42 @@ union cvmx_dpi_dma_control {
uint64_t o_es:2;
uint64_t o_mode:1;
uint64_t reserved_0_13:14;
#else
uint64_t reserved_0_13:14;
uint64_t o_mode:1;
uint64_t o_es:2;
uint64_t o_ns:1;
uint64_t o_ro:1;
uint64_t o_add1:1;
uint64_t fpa_que:3;
uint64_t dwb_ichk:9;
uint64_t dwb_denb:1;
uint64_t b0_lend:1;
uint64_t reserved_34_47:14;
uint64_t dma_enb:6;
uint64_t reserved_54_55:2;
uint64_t pkt_en:1;
uint64_t pkt_hp:1;
uint64_t commit_mode:1;
uint64_t reserved_59_63:5;
#endif
} cn63xxp1;
struct cvmx_dpi_dma_control_cn63xx cn66xx;
struct cvmx_dpi_dma_control_s cn68xx;
struct cvmx_dpi_dma_control_cn63xx cn68xxp1;
struct cvmx_dpi_dma_control_s cnf71xx;
};
union cvmx_dpi_dma_engx_en {
uint64_t u64;
struct cvmx_dpi_dma_engx_en_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63:56;
uint64_t qen:8;
#else
uint64_t qen:8;
uint64_t reserved_8_63:56;
#endif
} s;
struct cvmx_dpi_dma_engx_en_s cn61xx;
struct cvmx_dpi_dma_engx_en_s cn63xx;
@ -299,63 +485,101 @@ union cvmx_dpi_dma_engx_en {
struct cvmx_dpi_dma_engx_en_s cn66xx;
struct cvmx_dpi_dma_engx_en_s cn68xx;
struct cvmx_dpi_dma_engx_en_s cn68xxp1;
struct cvmx_dpi_dma_engx_en_s cnf71xx;
};
union cvmx_dpi_dma_ppx_cnt {
uint64_t u64;
struct cvmx_dpi_dma_ppx_cnt_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t cnt:16;
#else
uint64_t cnt:16;
uint64_t reserved_16_63:48;
#endif
} s;
struct cvmx_dpi_dma_ppx_cnt_s cn61xx;
struct cvmx_dpi_dma_ppx_cnt_s cn68xx;
struct cvmx_dpi_dma_ppx_cnt_s cnf71xx;
};
union cvmx_dpi_engx_buf {
uint64_t u64;
struct cvmx_dpi_engx_buf_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_37_63:27;
uint64_t compblks:5;
uint64_t reserved_9_31:23;
uint64_t base:5;
uint64_t blks:4;
#else
uint64_t blks:4;
uint64_t base:5;
uint64_t reserved_9_31:23;
uint64_t compblks:5;
uint64_t reserved_37_63:27;
#endif
} s;
struct cvmx_dpi_engx_buf_s cn61xx;
struct cvmx_dpi_engx_buf_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63:56;
uint64_t base:4;
uint64_t blks:4;
#else
uint64_t blks:4;
uint64_t base:4;
uint64_t reserved_8_63:56;
#endif
} cn63xx;
struct cvmx_dpi_engx_buf_cn63xx cn63xxp1;
struct cvmx_dpi_engx_buf_s cn66xx;
struct cvmx_dpi_engx_buf_s cn68xx;
struct cvmx_dpi_engx_buf_s cn68xxp1;
struct cvmx_dpi_engx_buf_s cnf71xx;
};
union cvmx_dpi_info_reg {
uint64_t u64;
struct cvmx_dpi_info_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63:56;
uint64_t ffp:4;
uint64_t reserved_2_3:2;
uint64_t ncb:1;
uint64_t rsl:1;
#else
uint64_t rsl:1;
uint64_t ncb:1;
uint64_t reserved_2_3:2;
uint64_t ffp:4;
uint64_t reserved_8_63:56;
#endif
} s;
struct cvmx_dpi_info_reg_s cn61xx;
struct cvmx_dpi_info_reg_s cn63xx;
struct cvmx_dpi_info_reg_cn63xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63:62;
uint64_t ncb:1;
uint64_t rsl:1;
#else
uint64_t rsl:1;
uint64_t ncb:1;
uint64_t reserved_2_63:62;
#endif
} cn63xxp1;
struct cvmx_dpi_info_reg_s cn66xx;
struct cvmx_dpi_info_reg_s cn68xx;
struct cvmx_dpi_info_reg_s cn68xxp1;
struct cvmx_dpi_info_reg_s cnf71xx;
};
union cvmx_dpi_int_en {
uint64_t u64;
struct cvmx_dpi_int_en_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_28_63:36;
uint64_t sprt3_rst:1;
uint64_t sprt2_rst:1;
@ -373,9 +597,29 @@ union cvmx_dpi_int_en {
uint64_t reserved_2_7:6;
uint64_t nfovr:1;
uint64_t nderr:1;
#else
uint64_t nderr:1;
uint64_t nfovr:1;
uint64_t reserved_2_7:6;
uint64_t dmadbo:8;
uint64_t req_badadr:1;
uint64_t req_badlen:1;
uint64_t req_ovrflw:1;
uint64_t req_undflw:1;
uint64_t req_anull:1;
uint64_t req_inull:1;
uint64_t req_badfil:1;
uint64_t reserved_23_23:1;
uint64_t sprt0_rst:1;
uint64_t sprt1_rst:1;
uint64_t sprt2_rst:1;
uint64_t sprt3_rst:1;
uint64_t reserved_28_63:36;
#endif
} s;
struct cvmx_dpi_int_en_s cn61xx;
struct cvmx_dpi_int_en_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_26_63:38;
uint64_t sprt1_rst:1;
uint64_t sprt0_rst:1;
@ -391,16 +635,35 @@ union cvmx_dpi_int_en {
uint64_t reserved_2_7:6;
uint64_t nfovr:1;
uint64_t nderr:1;
#else
uint64_t nderr:1;
uint64_t nfovr:1;
uint64_t reserved_2_7:6;
uint64_t dmadbo:8;
uint64_t req_badadr:1;
uint64_t req_badlen:1;
uint64_t req_ovrflw:1;
uint64_t req_undflw:1;
uint64_t req_anull:1;
uint64_t req_inull:1;
uint64_t req_badfil:1;
uint64_t reserved_23_23:1;
uint64_t sprt0_rst:1;
uint64_t sprt1_rst:1;
uint64_t reserved_26_63:38;
#endif
} cn63xx;
struct cvmx_dpi_int_en_cn63xx cn63xxp1;
struct cvmx_dpi_int_en_s cn66xx;
struct cvmx_dpi_int_en_cn63xx cn68xx;
struct cvmx_dpi_int_en_cn63xx cn68xxp1;
struct cvmx_dpi_int_en_s cnf71xx;
};
union cvmx_dpi_int_reg {
uint64_t u64;
struct cvmx_dpi_int_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_28_63:36;
uint64_t sprt3_rst:1;
uint64_t sprt2_rst:1;
@ -418,9 +681,29 @@ union cvmx_dpi_int_reg {
uint64_t reserved_2_7:6;
uint64_t nfovr:1;
uint64_t nderr:1;
#else
uint64_t nderr:1;
uint64_t nfovr:1;
uint64_t reserved_2_7:6;
uint64_t dmadbo:8;
uint64_t req_badadr:1;
uint64_t req_badlen:1;
uint64_t req_ovrflw:1;
uint64_t req_undflw:1;
uint64_t req_anull:1;
uint64_t req_inull:1;
uint64_t req_badfil:1;
uint64_t reserved_23_23:1;
uint64_t sprt0_rst:1;
uint64_t sprt1_rst:1;
uint64_t sprt2_rst:1;
uint64_t sprt3_rst:1;
uint64_t reserved_28_63:36;
#endif
} s;
struct cvmx_dpi_int_reg_s cn61xx;
struct cvmx_dpi_int_reg_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_26_63:38;
uint64_t sprt1_rst:1;
uint64_t sprt0_rst:1;
@ -436,31 +719,62 @@ union cvmx_dpi_int_reg {
uint64_t reserved_2_7:6;
uint64_t nfovr:1;
uint64_t nderr:1;
#else
uint64_t nderr:1;
uint64_t nfovr:1;
uint64_t reserved_2_7:6;
uint64_t dmadbo:8;
uint64_t req_badadr:1;
uint64_t req_badlen:1;
uint64_t req_ovrflw:1;
uint64_t req_undflw:1;
uint64_t req_anull:1;
uint64_t req_inull:1;
uint64_t req_badfil:1;
uint64_t reserved_23_23:1;
uint64_t sprt0_rst:1;
uint64_t sprt1_rst:1;
uint64_t reserved_26_63:38;
#endif
} cn63xx;
struct cvmx_dpi_int_reg_cn63xx cn63xxp1;
struct cvmx_dpi_int_reg_s cn66xx;
struct cvmx_dpi_int_reg_cn63xx cn68xx;
struct cvmx_dpi_int_reg_cn63xx cn68xxp1;
struct cvmx_dpi_int_reg_s cnf71xx;
};
union cvmx_dpi_ncbx_cfg {
uint64_t u64;
struct cvmx_dpi_ncbx_cfg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_6_63:58;
uint64_t molr:6;
#else
uint64_t molr:6;
uint64_t reserved_6_63:58;
#endif
} s;
struct cvmx_dpi_ncbx_cfg_s cn61xx;
struct cvmx_dpi_ncbx_cfg_s cn66xx;
struct cvmx_dpi_ncbx_cfg_s cn68xx;
struct cvmx_dpi_ncbx_cfg_s cnf71xx;
};
union cvmx_dpi_pint_info {
uint64_t u64;
struct cvmx_dpi_pint_info_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_14_63:50;
uint64_t iinfo:6;
uint64_t reserved_6_7:2;
uint64_t sinfo:6;
#else
uint64_t sinfo:6;
uint64_t reserved_6_7:2;
uint64_t iinfo:6;
uint64_t reserved_14_63:50;
#endif
} s;
struct cvmx_dpi_pint_info_s cn61xx;
struct cvmx_dpi_pint_info_s cn63xx;
@ -468,13 +782,19 @@ union cvmx_dpi_pint_info {
struct cvmx_dpi_pint_info_s cn66xx;
struct cvmx_dpi_pint_info_s cn68xx;
struct cvmx_dpi_pint_info_s cn68xxp1;
struct cvmx_dpi_pint_info_s cnf71xx;
};
union cvmx_dpi_pkt_err_rsp {
uint64_t u64;
struct cvmx_dpi_pkt_err_rsp_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63:63;
uint64_t pkterr:1;
#else
uint64_t pkterr:1;
uint64_t reserved_1_63:63;
#endif
} s;
struct cvmx_dpi_pkt_err_rsp_s cn61xx;
struct cvmx_dpi_pkt_err_rsp_s cn63xx;
@ -482,13 +802,19 @@ union cvmx_dpi_pkt_err_rsp {
struct cvmx_dpi_pkt_err_rsp_s cn66xx;
struct cvmx_dpi_pkt_err_rsp_s cn68xx;
struct cvmx_dpi_pkt_err_rsp_s cn68xxp1;
struct cvmx_dpi_pkt_err_rsp_s cnf71xx;
};
union cvmx_dpi_req_err_rsp {
uint64_t u64;
struct cvmx_dpi_req_err_rsp_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63:56;
uint64_t qerr:8;
#else
uint64_t qerr:8;
uint64_t reserved_8_63:56;
#endif
} s;
struct cvmx_dpi_req_err_rsp_s cn61xx;
struct cvmx_dpi_req_err_rsp_s cn63xx;
@ -496,13 +822,19 @@ union cvmx_dpi_req_err_rsp {
struct cvmx_dpi_req_err_rsp_s cn66xx;
struct cvmx_dpi_req_err_rsp_s cn68xx;
struct cvmx_dpi_req_err_rsp_s cn68xxp1;
struct cvmx_dpi_req_err_rsp_s cnf71xx;
};
union cvmx_dpi_req_err_rsp_en {
uint64_t u64;
struct cvmx_dpi_req_err_rsp_en_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63:56;
uint64_t en:8;
#else
uint64_t en:8;
uint64_t reserved_8_63:56;
#endif
} s;
struct cvmx_dpi_req_err_rsp_en_s cn61xx;
struct cvmx_dpi_req_err_rsp_en_s cn63xx;
@ -510,13 +842,19 @@ union cvmx_dpi_req_err_rsp_en {
struct cvmx_dpi_req_err_rsp_en_s cn66xx;
struct cvmx_dpi_req_err_rsp_en_s cn68xx;
struct cvmx_dpi_req_err_rsp_en_s cn68xxp1;
struct cvmx_dpi_req_err_rsp_en_s cnf71xx;
};
union cvmx_dpi_req_err_rst {
uint64_t u64;
struct cvmx_dpi_req_err_rst_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63:56;
uint64_t qerr:8;
#else
uint64_t qerr:8;
uint64_t reserved_8_63:56;
#endif
} s;
struct cvmx_dpi_req_err_rst_s cn61xx;
struct cvmx_dpi_req_err_rst_s cn63xx;
@ -524,13 +862,19 @@ union cvmx_dpi_req_err_rst {
struct cvmx_dpi_req_err_rst_s cn66xx;
struct cvmx_dpi_req_err_rst_s cn68xx;
struct cvmx_dpi_req_err_rst_s cn68xxp1;
struct cvmx_dpi_req_err_rst_s cnf71xx;
};
union cvmx_dpi_req_err_rst_en {
uint64_t u64;
struct cvmx_dpi_req_err_rst_en_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63:56;
uint64_t en:8;
#else
uint64_t en:8;
uint64_t reserved_8_63:56;
#endif
} s;
struct cvmx_dpi_req_err_rst_en_s cn61xx;
struct cvmx_dpi_req_err_rst_en_s cn63xx;
@ -538,27 +882,41 @@ union cvmx_dpi_req_err_rst_en {
struct cvmx_dpi_req_err_rst_en_s cn66xx;
struct cvmx_dpi_req_err_rst_en_s cn68xx;
struct cvmx_dpi_req_err_rst_en_s cn68xxp1;
struct cvmx_dpi_req_err_rst_en_s cnf71xx;
};
union cvmx_dpi_req_err_skip_comp {
uint64_t u64;
struct cvmx_dpi_req_err_skip_comp_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_24_63:40;
uint64_t en_rst:8;
uint64_t reserved_8_15:8;
uint64_t en_rsp:8;
#else
uint64_t en_rsp:8;
uint64_t reserved_8_15:8;
uint64_t en_rst:8;
uint64_t reserved_24_63:40;
#endif
} s;
struct cvmx_dpi_req_err_skip_comp_s cn61xx;
struct cvmx_dpi_req_err_skip_comp_s cn66xx;
struct cvmx_dpi_req_err_skip_comp_s cn68xx;
struct cvmx_dpi_req_err_skip_comp_s cn68xxp1;
struct cvmx_dpi_req_err_skip_comp_s cnf71xx;
};
union cvmx_dpi_req_gbl_en {
uint64_t u64;
struct cvmx_dpi_req_gbl_en_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63:56;
uint64_t qen:8;
#else
uint64_t qen:8;
uint64_t reserved_8_63:56;
#endif
} s;
struct cvmx_dpi_req_gbl_en_s cn61xx;
struct cvmx_dpi_req_gbl_en_s cn63xx;
@ -566,11 +924,13 @@ union cvmx_dpi_req_gbl_en {
struct cvmx_dpi_req_gbl_en_s cn66xx;
struct cvmx_dpi_req_gbl_en_s cn68xx;
struct cvmx_dpi_req_gbl_en_s cn68xxp1;
struct cvmx_dpi_req_gbl_en_s cnf71xx;
};
union cvmx_dpi_sli_prtx_cfg {
uint64_t u64;
struct cvmx_dpi_sli_prtx_cfg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_25_63:39;
uint64_t halt:1;
uint64_t qlm_cfg:4;
@ -584,9 +944,25 @@ union cvmx_dpi_sli_prtx_cfg {
uint64_t mrrs_lim:1;
uint64_t reserved_2_2:1;
uint64_t mrrs:2;
#else
uint64_t mrrs:2;
uint64_t reserved_2_2:1;
uint64_t mrrs_lim:1;
uint64_t mps:1;
uint64_t reserved_5_6:2;
uint64_t mps_lim:1;
uint64_t molr:6;
uint64_t reserved_14_15:2;
uint64_t rd_mode:1;
uint64_t reserved_17_19:3;
uint64_t qlm_cfg:4;
uint64_t halt:1;
uint64_t reserved_25_63:39;
#endif
} s;
struct cvmx_dpi_sli_prtx_cfg_s cn61xx;
struct cvmx_dpi_sli_prtx_cfg_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_25_63:39;
uint64_t halt:1;
uint64_t reserved_21_23:3;
@ -601,18 +977,40 @@ union cvmx_dpi_sli_prtx_cfg {
uint64_t mrrs_lim:1;
uint64_t reserved_2_2:1;
uint64_t mrrs:2;
#else
uint64_t mrrs:2;
uint64_t reserved_2_2:1;
uint64_t mrrs_lim:1;
uint64_t mps:1;
uint64_t reserved_5_6:2;
uint64_t mps_lim:1;
uint64_t molr:6;
uint64_t reserved_14_15:2;
uint64_t rd_mode:1;
uint64_t reserved_17_19:3;
uint64_t qlm_cfg:1;
uint64_t reserved_21_23:3;
uint64_t halt:1;
uint64_t reserved_25_63:39;
#endif
} cn63xx;
struct cvmx_dpi_sli_prtx_cfg_cn63xx cn63xxp1;
struct cvmx_dpi_sli_prtx_cfg_s cn66xx;
struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xx;
struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xxp1;
struct cvmx_dpi_sli_prtx_cfg_s cnf71xx;
};
union cvmx_dpi_sli_prtx_err {
uint64_t u64;
struct cvmx_dpi_sli_prtx_err_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t addr:61;
uint64_t reserved_0_2:3;
#else
uint64_t reserved_0_2:3;
uint64_t addr:61;
#endif
} s;
struct cvmx_dpi_sli_prtx_err_s cn61xx;
struct cvmx_dpi_sli_prtx_err_s cn63xx;
@ -620,17 +1018,27 @@ union cvmx_dpi_sli_prtx_err {
struct cvmx_dpi_sli_prtx_err_s cn66xx;
struct cvmx_dpi_sli_prtx_err_s cn68xx;
struct cvmx_dpi_sli_prtx_err_s cn68xxp1;
struct cvmx_dpi_sli_prtx_err_s cnf71xx;
};
union cvmx_dpi_sli_prtx_err_info {
uint64_t u64;
struct cvmx_dpi_sli_prtx_err_info_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_9_63:55;
uint64_t lock:1;
uint64_t reserved_5_7:3;
uint64_t type:1;
uint64_t reserved_3_3:1;
uint64_t reqq:3;
#else
uint64_t reqq:3;
uint64_t reserved_3_3:1;
uint64_t type:1;
uint64_t reserved_5_7:3;
uint64_t lock:1;
uint64_t reserved_9_63:55;
#endif
} s;
struct cvmx_dpi_sli_prtx_err_info_s cn61xx;
struct cvmx_dpi_sli_prtx_err_info_s cn63xx;
@ -638,6 +1046,7 @@ union cvmx_dpi_sli_prtx_err_info {
struct cvmx_dpi_sli_prtx_err_info_s cn66xx;
struct cvmx_dpi_sli_prtx_err_info_s cn68xx;
struct cvmx_dpi_sli_prtx_err_info_s cn68xxp1;
struct cvmx_dpi_sli_prtx_err_info_s cnf71xx;
};
#endif

1307
arch/mips/include/asm/octeon/cvmx-fpa-defs.h
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4934
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
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File diff suppressed because it is too large Load Diff

282
arch/mips/include/asm/octeon/cvmx-gpio-defs.h
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@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2010 Cavium Networks
* Copyright (c) 2003-2012 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@ -34,7 +34,10 @@
#define CVMX_GPIO_CLK_QLMX(offset) (CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8)
#define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
#define CVMX_GPIO_INT_CLR (CVMX_ADD_IO_SEG(0x0001070000000898ull))
#define CVMX_GPIO_MULTI_CAST (CVMX_ADD_IO_SEG(0x00010700000008B0ull))
#define CVMX_GPIO_PIN_ENA (CVMX_ADD_IO_SEG(0x00010700000008B8ull))
#define CVMX_GPIO_RX_DAT (CVMX_ADD_IO_SEG(0x0001070000000880ull))
#define CVMX_GPIO_TIM_CTL (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
#define CVMX_GPIO_TX_CLR (CVMX_ADD_IO_SEG(0x0001070000000890ull))
#define CVMX_GPIO_TX_SET (CVMX_ADD_IO_SEG(0x0001070000000888ull))
#define CVMX_GPIO_XBIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16)
@ -42,6 +45,7 @@
union cvmx_gpio_bit_cfgx {
uint64_t u64;
struct cvmx_gpio_bit_cfgx_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_17_63:47;
uint64_t synce_sel:2;
uint64_t clk_gen:1;
@ -52,8 +56,21 @@ union cvmx_gpio_bit_cfgx {
uint64_t int_en:1;
uint64_t rx_xor:1;
uint64_t tx_oe:1;
#else
uint64_t tx_oe:1;
uint64_t rx_xor:1;
uint64_t int_en:1;
uint64_t int_type:1;
uint64_t fil_cnt:4;
uint64_t fil_sel:4;
uint64_t clk_sel:2;
uint64_t clk_gen:1;
uint64_t synce_sel:2;
uint64_t reserved_17_63:47;
#endif
} s;
struct cvmx_gpio_bit_cfgx_cn30xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63:52;
uint64_t fil_sel:4;
uint64_t fil_cnt:4;
@ -61,12 +78,22 @@ union cvmx_gpio_bit_cfgx {
uint64_t int_en:1;
uint64_t rx_xor:1;
uint64_t tx_oe:1;
#else
uint64_t tx_oe:1;
uint64_t rx_xor:1;
uint64_t int_en:1;
uint64_t int_type:1;
uint64_t fil_cnt:4;
uint64_t fil_sel:4;
uint64_t reserved_12_63:52;
#endif
} cn30xx;
struct cvmx_gpio_bit_cfgx_cn30xx cn31xx;
struct cvmx_gpio_bit_cfgx_cn30xx cn38xx;
struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2;
struct cvmx_gpio_bit_cfgx_cn30xx cn50xx;
struct cvmx_gpio_bit_cfgx_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_15_63:49;
uint64_t clk_gen:1;
uint64_t clk_sel:2;
@ -76,22 +103,44 @@ union cvmx_gpio_bit_cfgx {
uint64_t int_en:1;
uint64_t rx_xor:1;
uint64_t tx_oe:1;
#else
uint64_t tx_oe:1;
uint64_t rx_xor:1;
uint64_t int_en:1;
uint64_t int_type:1;
uint64_t fil_cnt:4;
uint64_t fil_sel:4;
uint64_t clk_sel:2;
uint64_t clk_gen:1;
uint64_t reserved_15_63:49;
#endif
} cn52xx;
struct cvmx_gpio_bit_cfgx_cn52xx cn52xxp1;
struct cvmx_gpio_bit_cfgx_cn52xx cn56xx;
struct cvmx_gpio_bit_cfgx_cn52xx cn56xxp1;
struct cvmx_gpio_bit_cfgx_cn30xx cn58xx;
struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1;
struct cvmx_gpio_bit_cfgx_s cn61xx;
struct cvmx_gpio_bit_cfgx_s cn63xx;
struct cvmx_gpio_bit_cfgx_s cn63xxp1;
struct cvmx_gpio_bit_cfgx_s cn66xx;
struct cvmx_gpio_bit_cfgx_s cn68xx;
struct cvmx_gpio_bit_cfgx_s cn68xxp1;
struct cvmx_gpio_bit_cfgx_s cnf71xx;
};
union cvmx_gpio_boot_ena {
uint64_t u64;
struct cvmx_gpio_boot_ena_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63:52;
uint64_t boot_ena:4;
uint64_t reserved_0_7:8;
#else
uint64_t reserved_0_7:8;
uint64_t boot_ena:4;
uint64_t reserved_12_63:52;
#endif
} s;
struct cvmx_gpio_boot_ena_s cn30xx;
struct cvmx_gpio_boot_ena_s cn31xx;
@ -101,33 +150,87 @@ union cvmx_gpio_boot_ena {
union cvmx_gpio_clk_genx {
uint64_t u64;
struct cvmx_gpio_clk_genx_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
uint64_t n:32;
#else
uint64_t n:32;
uint64_t reserved_32_63:32;
#endif
} s;
struct cvmx_gpio_clk_genx_s cn52xx;
struct cvmx_gpio_clk_genx_s cn52xxp1;
struct cvmx_gpio_clk_genx_s cn56xx;
struct cvmx_gpio_clk_genx_s cn56xxp1;
struct cvmx_gpio_clk_genx_s cn61xx;
struct cvmx_gpio_clk_genx_s cn63xx;
struct cvmx_gpio_clk_genx_s cn63xxp1;
struct cvmx_gpio_clk_genx_s cn66xx;
struct cvmx_gpio_clk_genx_s cn68xx;
struct cvmx_gpio_clk_genx_s cn68xxp1;
struct cvmx_gpio_clk_genx_s cnf71xx;
};
union cvmx_gpio_clk_qlmx {
uint64_t u64;
struct cvmx_gpio_clk_qlmx_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_11_63:53;
uint64_t qlm_sel:3;
uint64_t reserved_3_7:5;
uint64_t div:1;
uint64_t lane_sel:2;
#else
uint64_t lane_sel:2;
uint64_t div:1;
uint64_t reserved_3_7:5;
uint64_t qlm_sel:3;
uint64_t reserved_11_63:53;
#endif
} s;
struct cvmx_gpio_clk_qlmx_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_10_63:54;
uint64_t qlm_sel:2;
uint64_t reserved_3_7:5;
uint64_t div:1;
uint64_t lane_sel:2;
#else
uint64_t lane_sel:2;
uint64_t div:1;
uint64_t reserved_3_7:5;
uint64_t qlm_sel:2;
uint64_t reserved_10_63:54;
#endif
} cn61xx;
struct cvmx_gpio_clk_qlmx_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_3_63:61;
uint64_t div:1;
uint64_t lane_sel:2;
} s;
struct cvmx_gpio_clk_qlmx_s cn63xx;
struct cvmx_gpio_clk_qlmx_s cn63xxp1;
#else
uint64_t lane_sel:2;
uint64_t div:1;
uint64_t reserved_3_63:61;
#endif
} cn63xx;
struct cvmx_gpio_clk_qlmx_cn63xx cn63xxp1;
struct cvmx_gpio_clk_qlmx_cn61xx cn66xx;
struct cvmx_gpio_clk_qlmx_s cn68xx;
struct cvmx_gpio_clk_qlmx_s cn68xxp1;
struct cvmx_gpio_clk_qlmx_cn61xx cnf71xx;
};
union cvmx_gpio_dbg_ena {
uint64_t u64;
struct cvmx_gpio_dbg_ena_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_21_63:43;
uint64_t dbg_ena:21;
#else
uint64_t dbg_ena:21;
uint64_t reserved_21_63:43;
#endif
} s;
struct cvmx_gpio_dbg_ena_s cn30xx;
struct cvmx_gpio_dbg_ena_s cn31xx;
@ -137,8 +240,13 @@ union cvmx_gpio_dbg_ena {
union cvmx_gpio_int_clr {
uint64_t u64;
struct cvmx_gpio_int_clr_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t type:16;
#else
uint64_t type:16;
uint64_t reserved_16_63:48;
#endif
} s;
struct cvmx_gpio_int_clr_s cn30xx;
struct cvmx_gpio_int_clr_s cn31xx;
@ -151,21 +259,69 @@ union cvmx_gpio_int_clr {
struct cvmx_gpio_int_clr_s cn56xxp1;
struct cvmx_gpio_int_clr_s cn58xx;
struct cvmx_gpio_int_clr_s cn58xxp1;
struct cvmx_gpio_int_clr_s cn61xx;
struct cvmx_gpio_int_clr_s cn63xx;
struct cvmx_gpio_int_clr_s cn63xxp1;
struct cvmx_gpio_int_clr_s cn66xx;
struct cvmx_gpio_int_clr_s cn68xx;
struct cvmx_gpio_int_clr_s cn68xxp1;
struct cvmx_gpio_int_clr_s cnf71xx;
};
union cvmx_gpio_multi_cast {
uint64_t u64;
struct cvmx_gpio_multi_cast_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63:63;
uint64_t en:1;
#else
uint64_t en:1;
uint64_t reserved_1_63:63;
#endif
} s;
struct cvmx_gpio_multi_cast_s cn61xx;
struct cvmx_gpio_multi_cast_s cnf71xx;
};
union cvmx_gpio_pin_ena {
uint64_t u64;
struct cvmx_gpio_pin_ena_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63:44;
uint64_t ena19:1;
uint64_t ena18:1;
uint64_t reserved_0_17:18;
#else
uint64_t reserved_0_17:18;
uint64_t ena18:1;
uint64_t ena19:1;
uint64_t reserved_20_63:44;
#endif
} s;
struct cvmx_gpio_pin_ena_s cn66xx;
};
union cvmx_gpio_rx_dat {
uint64_t u64;
struct cvmx_gpio_rx_dat_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_24_63:40;
uint64_t dat:24;
#else
uint64_t dat:24;
uint64_t reserved_24_63:40;
#endif
} s;
struct cvmx_gpio_rx_dat_s cn30xx;
struct cvmx_gpio_rx_dat_s cn31xx;
struct cvmx_gpio_rx_dat_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t dat:16;
#else
uint64_t dat:16;
uint64_t reserved_16_63:48;
#endif
} cn38xx;
struct cvmx_gpio_rx_dat_cn38xx cn38xxp2;
struct cvmx_gpio_rx_dat_s cn50xx;
@ -175,21 +331,59 @@ union cvmx_gpio_rx_dat {
struct cvmx_gpio_rx_dat_cn38xx cn56xxp1;
struct cvmx_gpio_rx_dat_cn38xx cn58xx;
struct cvmx_gpio_rx_dat_cn38xx cn58xxp1;
struct cvmx_gpio_rx_dat_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63:44;
uint64_t dat:20;
#else
uint64_t dat:20;
uint64_t reserved_20_63:44;
#endif
} cn61xx;
struct cvmx_gpio_rx_dat_cn38xx cn63xx;
struct cvmx_gpio_rx_dat_cn38xx cn63xxp1;
struct cvmx_gpio_rx_dat_cn61xx cn66xx;
struct cvmx_gpio_rx_dat_cn38xx cn68xx;
struct cvmx_gpio_rx_dat_cn38xx cn68xxp1;
struct cvmx_gpio_rx_dat_cn61xx cnf71xx;
};
union cvmx_gpio_tim_ctl {
uint64_t u64;
struct cvmx_gpio_tim_ctl_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63:60;
uint64_t sel:4;
#else
uint64_t sel:4;
uint64_t reserved_4_63:60;
#endif
} s;
struct cvmx_gpio_tim_ctl_s cn68xx;
struct cvmx_gpio_tim_ctl_s cn68xxp1;
};
union cvmx_gpio_tx_clr {
uint64_t u64;
struct cvmx_gpio_tx_clr_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_24_63:40;
uint64_t clr:24;
#else
uint64_t clr:24;
uint64_t reserved_24_63:40;
#endif
} s;
struct cvmx_gpio_tx_clr_s cn30xx;
struct cvmx_gpio_tx_clr_s cn31xx;
struct cvmx_gpio_tx_clr_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t clr:16;
#else
uint64_t clr:16;
uint64_t reserved_16_63:48;
#endif
} cn38xx;
struct cvmx_gpio_tx_clr_cn38xx cn38xxp2;
struct cvmx_gpio_tx_clr_s cn50xx;
@ -199,21 +393,44 @@ union cvmx_gpio_tx_clr {
struct cvmx_gpio_tx_clr_cn38xx cn56xxp1;
struct cvmx_gpio_tx_clr_cn38xx cn58xx;
struct cvmx_gpio_tx_clr_cn38xx cn58xxp1;
struct cvmx_gpio_tx_clr_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63:44;
uint64_t clr:20;
#else
uint64_t clr:20;
uint64_t reserved_20_63:44;
#endif
} cn61xx;
struct cvmx_gpio_tx_clr_cn38xx cn63xx;
struct cvmx_gpio_tx_clr_cn38xx cn63xxp1;
struct cvmx_gpio_tx_clr_cn61xx cn66xx;
struct cvmx_gpio_tx_clr_cn38xx cn68xx;
struct cvmx_gpio_tx_clr_cn38xx cn68xxp1;
struct cvmx_gpio_tx_clr_cn61xx cnf71xx;
};
union cvmx_gpio_tx_set {
uint64_t u64;
struct cvmx_gpio_tx_set_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_24_63:40;
uint64_t set:24;
#else
uint64_t set:24;
uint64_t reserved_24_63:40;
#endif
} s;
struct cvmx_gpio_tx_set_s cn30xx;
struct cvmx_gpio_tx_set_s cn31xx;
struct cvmx_gpio_tx_set_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t set:16;
#else
uint64_t set:16;
uint64_t reserved_16_63:48;
#endif
} cn38xx;
struct cvmx_gpio_tx_set_cn38xx cn38xxp2;
struct cvmx_gpio_tx_set_s cn50xx;
@ -223,23 +440,72 @@ union cvmx_gpio_tx_set {
struct cvmx_gpio_tx_set_cn38xx cn56xxp1;
struct cvmx_gpio_tx_set_cn38xx cn58xx;
struct cvmx_gpio_tx_set_cn38xx cn58xxp1;
struct cvmx_gpio_tx_set_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63:44;
uint64_t set:20;
#else
uint64_t set:20;
uint64_t reserved_20_63:44;
#endif
} cn61xx;
struct cvmx_gpio_tx_set_cn38xx cn63xx;
struct cvmx_gpio_tx_set_cn38xx cn63xxp1;
struct cvmx_gpio_tx_set_cn61xx cn66xx;
struct cvmx_gpio_tx_set_cn38xx cn68xx;
struct cvmx_gpio_tx_set_cn38xx cn68xxp1;
struct cvmx_gpio_tx_set_cn61xx cnf71xx;
};
union cvmx_gpio_xbit_cfgx {
uint64_t u64;
struct cvmx_gpio_xbit_cfgx_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_17_63:47;
uint64_t synce_sel:2;
uint64_t clk_gen:1;
uint64_t clk_sel:2;
uint64_t fil_sel:4;
uint64_t fil_cnt:4;
uint64_t int_type:1;
uint64_t int_en:1;
uint64_t rx_xor:1;
uint64_t tx_oe:1;
#else
uint64_t tx_oe:1;
uint64_t rx_xor:1;
uint64_t int_en:1;
uint64_t int_type:1;
uint64_t fil_cnt:4;
uint64_t fil_sel:4;
uint64_t clk_sel:2;
uint64_t clk_gen:1;
uint64_t synce_sel:2;
uint64_t reserved_17_63:47;
#endif
} s;
struct cvmx_gpio_xbit_cfgx_cn30xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63:52;
uint64_t fil_sel:4;
uint64_t fil_cnt:4;
uint64_t reserved_2_3:2;
uint64_t rx_xor:1;
uint64_t tx_oe:1;
} s;
struct cvmx_gpio_xbit_cfgx_s cn30xx;
struct cvmx_gpio_xbit_cfgx_s cn31xx;
struct cvmx_gpio_xbit_cfgx_s cn50xx;
#else
uint64_t tx_oe:1;
uint64_t rx_xor:1;
uint64_t reserved_2_3:2;
uint64_t fil_cnt:4;
uint64_t fil_sel:4;
uint64_t reserved_12_63:52;
#endif
} cn30xx;
struct cvmx_gpio_xbit_cfgx_cn30xx cn31xx;
struct cvmx_gpio_xbit_cfgx_cn30xx cn50xx;
struct cvmx_gpio_xbit_cfgx_s cn61xx;
struct cvmx_gpio_xbit_cfgx_s cn66xx;
struct cvmx_gpio_xbit_cfgx_s cnf71xx;
};
#endif

758
arch/mips/include/asm/octeon/cvmx-iob-defs.h
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1243
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
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1716
arch/mips/include/asm/octeon/cvmx-l2c-defs.h
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171
arch/mips/include/asm/octeon/cvmx-l2d-defs.h
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@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2010 Cavium Networks
* Copyright (c) 2003-2012 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@ -44,9 +44,15 @@
union cvmx_l2d_bst0 {
uint64_t u64;
struct cvmx_l2d_bst0_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_35_63:29;
uint64_t ftl:1;
uint64_t q0stat:34;
#else
uint64_t q0stat:34;
uint64_t ftl:1;
uint64_t reserved_35_63:29;
#endif
} s;
struct cvmx_l2d_bst0_s cn30xx;
struct cvmx_l2d_bst0_s cn31xx;
@ -64,8 +70,13 @@ union cvmx_l2d_bst0 {
union cvmx_l2d_bst1 {
uint64_t u64;
struct cvmx_l2d_bst1_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_34_63:30;
uint64_t q1stat:34;
#else
uint64_t q1stat:34;
uint64_t reserved_34_63:30;
#endif
} s;
struct cvmx_l2d_bst1_s cn30xx;
struct cvmx_l2d_bst1_s cn31xx;
@ -83,8 +94,13 @@ union cvmx_l2d_bst1 {
union cvmx_l2d_bst2 {
uint64_t u64;
struct cvmx_l2d_bst2_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_34_63:30;
uint64_t q2stat:34;
#else
uint64_t q2stat:34;
uint64_t reserved_34_63:30;
#endif
} s;
struct cvmx_l2d_bst2_s cn30xx;
struct cvmx_l2d_bst2_s cn31xx;
@ -102,8 +118,13 @@ union cvmx_l2d_bst2 {
union cvmx_l2d_bst3 {
uint64_t u64;
struct cvmx_l2d_bst3_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_34_63:30;
uint64_t q3stat:34;
#else
uint64_t q3stat:34;
uint64_t reserved_34_63:30;
#endif
} s;
struct cvmx_l2d_bst3_s cn30xx;
struct cvmx_l2d_bst3_s cn31xx;
@ -121,6 +142,7 @@ union cvmx_l2d_bst3 {
union cvmx_l2d_err {
uint64_t u64;
struct cvmx_l2d_err_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_6_63:58;
uint64_t bmhclsel:1;
uint64_t ded_err:1;
@ -128,6 +150,15 @@ union cvmx_l2d_err {
uint64_t ded_intena:1;
uint64_t sec_intena:1;
uint64_t ecc_ena:1;
#else
uint64_t ecc_ena:1;
uint64_t sec_intena:1;
uint64_t ded_intena:1;
uint64_t sec_err:1;
uint64_t ded_err:1;
uint64_t bmhclsel:1;
uint64_t reserved_6_63:58;
#endif
} s;
struct cvmx_l2d_err_s cn30xx;
struct cvmx_l2d_err_s cn31xx;
@ -145,48 +176,97 @@ union cvmx_l2d_err {
union cvmx_l2d_fadr {
uint64_t u64;
struct cvmx_l2d_fadr_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_19_63:45;
uint64_t fadru:1;
uint64_t fowmsk:4;
uint64_t fset:3;
uint64_t fadr:11;
#else
uint64_t fadr:11;
uint64_t fset:3;
uint64_t fowmsk:4;
uint64_t fadru:1;
uint64_t reserved_19_63:45;
#endif
} s;
struct cvmx_l2d_fadr_cn30xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_18_63:46;
uint64_t fowmsk:4;
uint64_t reserved_13_13:1;
uint64_t fset:2;
uint64_t reserved_9_10:2;
uint64_t fadr:9;
#else
uint64_t fadr:9;
uint64_t reserved_9_10:2;
uint64_t fset:2;
uint64_t reserved_13_13:1;
uint64_t fowmsk:4;
uint64_t reserved_18_63:46;
#endif
} cn30xx;
struct cvmx_l2d_fadr_cn31xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_18_63:46;
uint64_t fowmsk:4;
uint64_t reserved_13_13:1;
uint64_t fset:2;
uint64_t reserved_10_10:1;
uint64_t fadr:10;
#else
uint64_t fadr:10;
uint64_t reserved_10_10:1;
uint64_t fset:2;
uint64_t reserved_13_13:1;
uint64_t fowmsk:4;
uint64_t reserved_18_63:46;
#endif
} cn31xx;
struct cvmx_l2d_fadr_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_18_63:46;
uint64_t fowmsk:4;
uint64_t fset:3;
uint64_t fadr:11;
#else
uint64_t fadr:11;
uint64_t fset:3;
uint64_t fowmsk:4;
uint64_t reserved_18_63:46;
#endif
} cn38xx;
struct cvmx_l2d_fadr_cn38xx cn38xxp2;
struct cvmx_l2d_fadr_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_18_63:46;
uint64_t fowmsk:4;
uint64_t fset:3;
uint64_t reserved_8_10:3;
uint64_t fadr:8;
#else
uint64_t fadr:8;
uint64_t reserved_8_10:3;
uint64_t fset:3;
uint64_t fowmsk:4;
uint64_t reserved_18_63:46;
#endif
} cn50xx;
struct cvmx_l2d_fadr_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_18_63:46;
uint64_t fowmsk:4;
uint64_t fset:3;
uint64_t reserved_10_10:1;
uint64_t fadr:10;
#else
uint64_t fadr:10;
uint64_t reserved_10_10:1;
uint64_t fset:3;
uint64_t fowmsk:4;
uint64_t reserved_18_63:46;
#endif
} cn52xx;
struct cvmx_l2d_fadr_cn52xx cn52xxp1;
struct cvmx_l2d_fadr_s cn56xx;
@ -198,9 +278,15 @@ union cvmx_l2d_fadr {
union cvmx_l2d_fsyn0 {
uint64_t u64;
struct cvmx_l2d_fsyn0_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63:44;
uint64_t fsyn_ow1:10;
uint64_t fsyn_ow0:10;
#else
uint64_t fsyn_ow0:10;
uint64_t fsyn_ow1:10;
uint64_t reserved_20_63:44;
#endif
} s;
struct cvmx_l2d_fsyn0_s cn30xx;
struct cvmx_l2d_fsyn0_s cn31xx;
@ -218,9 +304,15 @@ union cvmx_l2d_fsyn0 {
union cvmx_l2d_fsyn1 {
uint64_t u64;
struct cvmx_l2d_fsyn1_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63:44;
uint64_t fsyn_ow3:10;
uint64_t fsyn_ow2:10;
#else
uint64_t fsyn_ow2:10;
uint64_t fsyn_ow3:10;
uint64_t reserved_20_63:44;
#endif
} s;
struct cvmx_l2d_fsyn1_s cn30xx;
struct cvmx_l2d_fsyn1_s cn31xx;
@ -238,8 +330,13 @@ union cvmx_l2d_fsyn1 {
union cvmx_l2d_fus0 {
uint64_t u64;
struct cvmx_l2d_fus0_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_34_63:30;
uint64_t q0fus:34;
#else
uint64_t q0fus:34;
uint64_t reserved_34_63:30;
#endif
} s;
struct cvmx_l2d_fus0_s cn30xx;
struct cvmx_l2d_fus0_s cn31xx;
@ -257,8 +354,13 @@ union cvmx_l2d_fus0 {
union cvmx_l2d_fus1 {
uint64_t u64;
struct cvmx_l2d_fus1_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_34_63:30;
uint64_t q1fus:34;
#else
uint64_t q1fus:34;
uint64_t reserved_34_63:30;
#endif
} s;
struct cvmx_l2d_fus1_s cn30xx;
struct cvmx_l2d_fus1_s cn31xx;
@ -276,8 +378,13 @@ union cvmx_l2d_fus1 {
union cvmx_l2d_fus2 {
uint64_t u64;
struct cvmx_l2d_fus2_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_34_63:30;
uint64_t q2fus:34;
#else
uint64_t q2fus:34;
uint64_t reserved_34_63:30;
#endif
} s;
struct cvmx_l2d_fus2_s cn30xx;
struct cvmx_l2d_fus2_s cn31xx;
@ -295,61 +402,123 @@ union cvmx_l2d_fus2 {
union cvmx_l2d_fus3 {
uint64_t u64;
struct cvmx_l2d_fus3_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_40_63:24;
uint64_t ema_ctl:3;
uint64_t reserved_34_36:3;
uint64_t q3fus:34;
#else
uint64_t q3fus:34;
uint64_t reserved_34_36:3;
uint64_t ema_ctl:3;
uint64_t reserved_40_63:24;
#endif
} s;
struct cvmx_l2d_fus3_cn30xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_35_63:29;
uint64_t crip_64k:1;
uint64_t q3fus:34;
#else
uint64_t q3fus:34;
uint64_t crip_64k:1;
uint64_t reserved_35_63:29;
#endif
} cn30xx;
struct cvmx_l2d_fus3_cn31xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_35_63:29;
uint64_t crip_128k:1;
uint64_t q3fus:34;
#else
uint64_t q3fus:34;
uint64_t crip_128k:1;
uint64_t reserved_35_63:29;
#endif
} cn31xx;
struct cvmx_l2d_fus3_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_36_63:28;
uint64_t crip_256k:1;
uint64_t crip_512k:1;
uint64_t q3fus:34;
#else
uint64_t q3fus:34;
uint64_t crip_512k:1;
uint64_t crip_256k:1;
uint64_t reserved_36_63:28;
#endif
} cn38xx;
struct cvmx_l2d_fus3_cn38xx cn38xxp2;
struct cvmx_l2d_fus3_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_40_63:24;
uint64_t ema_ctl:3;
uint64_t reserved_36_36:1;
uint64_t crip_32k:1;
uint64_t crip_64k:1;
uint64_t q3fus:34;
#else
uint64_t q3fus:34;
uint64_t crip_64k:1;
uint64_t crip_32k:1;
uint64_t reserved_36_36:1;
uint64_t ema_ctl:3;
uint64_t reserved_40_63:24;
#endif
} cn50xx;
struct cvmx_l2d_fus3_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_40_63:24;
uint64_t ema_ctl:3;
uint64_t reserved_36_36:1;
uint64_t crip_128k:1;
uint64_t crip_256k:1;
uint64_t q3fus:34;
#else
uint64_t q3fus:34;
uint64_t crip_256k:1;
uint64_t crip_128k:1;
uint64_t reserved_36_36:1;
uint64_t ema_ctl:3;
uint64_t reserved_40_63:24;
#endif
} cn52xx;
struct cvmx_l2d_fus3_cn52xx cn52xxp1;
struct cvmx_l2d_fus3_cn56xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_40_63:24;
uint64_t ema_ctl:3;
uint64_t reserved_36_36:1;
uint64_t crip_512k:1;
uint64_t crip_1024k:1;
uint64_t q3fus:34;
#else
uint64_t q3fus:34;
uint64_t crip_1024k:1;
uint64_t crip_512k:1;
uint64_t reserved_36_36:1;
uint64_t ema_ctl:3;
uint64_t reserved_40_63:24;
#endif
} cn56xx;
struct cvmx_l2d_fus3_cn56xx cn56xxp1;
struct cvmx_l2d_fus3_cn58xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_39_63:25;
uint64_t ema_ctl:2;
uint64_t reserved_36_36:1;
uint64_t crip_512k:1;
uint64_t crip_1024k:1;
uint64_t q3fus:34;
#else
uint64_t q3fus:34;
uint64_t crip_1024k:1;
uint64_t crip_512k:1;
uint64_t reserved_36_36:1;
uint64_t ema_ctl:2;
uint64_t reserved_39_63:25;
#endif
} cn58xx;
struct cvmx_l2d_fus3_cn58xx cn58xxp1;
};

105
arch/mips/include/asm/octeon/cvmx-l2t-defs.h
View File

@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2010 Cavium Networks
* Copyright (c) 2003-2012 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@ -33,6 +33,7 @@
union cvmx_l2t_err {
uint64_t u64;
struct cvmx_l2t_err_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_29_63:35;
uint64_t fadru:1;
uint64_t lck_intena2:1;
@ -47,8 +48,25 @@ union cvmx_l2t_err {
uint64_t ded_intena:1;
uint64_t sec_intena:1;
uint64_t ecc_ena:1;
#else
uint64_t ecc_ena:1;
uint64_t sec_intena:1;
uint64_t ded_intena:1;
uint64_t sec_err:1;
uint64_t ded_err:1;
uint64_t fsyn:6;
uint64_t fadr:10;
uint64_t fset:3;
uint64_t lckerr:1;
uint64_t lck_intena:1;
uint64_t lckerr2:1;
uint64_t lck_intena2:1;
uint64_t fadru:1;
uint64_t reserved_29_63:35;
#endif
} s;
struct cvmx_l2t_err_cn30xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_28_63:36;
uint64_t lck_intena2:1;
uint64_t lckerr2:1;
@ -64,8 +82,26 @@ union cvmx_l2t_err {
uint64_t ded_intena:1;
uint64_t sec_intena:1;
uint64_t ecc_ena:1;
#else
uint64_t ecc_ena:1;
uint64_t sec_intena:1;
uint64_t ded_intena:1;
uint64_t sec_err:1;
uint64_t ded_err:1;
uint64_t fsyn:6;
uint64_t fadr:8;
uint64_t reserved_19_20:2;
uint64_t fset:2;
uint64_t reserved_23_23:1;
uint64_t lckerr:1;
uint64_t lck_intena:1;
uint64_t lckerr2:1;
uint64_t lck_intena2:1;
uint64_t reserved_28_63:36;
#endif
} cn30xx;
struct cvmx_l2t_err_cn31xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_28_63:36;
uint64_t lck_intena2:1;
uint64_t lckerr2:1;
@ -81,8 +117,26 @@ union cvmx_l2t_err {
uint64_t ded_intena:1;
uint64_t sec_intena:1;
uint64_t ecc_ena:1;
#else
uint64_t ecc_ena:1;
uint64_t sec_intena:1;
uint64_t ded_intena:1;
uint64_t sec_err:1;
uint64_t ded_err:1;
uint64_t fsyn:6;
uint64_t fadr:9;
uint64_t reserved_20_20:1;
uint64_t fset:2;
uint64_t reserved_23_23:1;
uint64_t lckerr:1;
uint64_t lck_intena:1;
uint64_t lckerr2:1;
uint64_t lck_intena2:1;
uint64_t reserved_28_63:36;
#endif
} cn31xx;
struct cvmx_l2t_err_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_28_63:36;
uint64_t lck_intena2:1;
uint64_t lckerr2:1;
@ -96,9 +150,25 @@ union cvmx_l2t_err {
uint64_t ded_intena:1;
uint64_t sec_intena:1;
uint64_t ecc_ena:1;
#else
uint64_t ecc_ena:1;
uint64_t sec_intena:1;
uint64_t ded_intena:1;
uint64_t sec_err:1;
uint64_t ded_err:1;
uint64_t fsyn:6;
uint64_t fadr:10;
uint64_t fset:3;
uint64_t lckerr:1;
uint64_t lck_intena:1;
uint64_t lckerr2:1;
uint64_t lck_intena2:1;
uint64_t reserved_28_63:36;
#endif
} cn38xx;
struct cvmx_l2t_err_cn38xx cn38xxp2;
struct cvmx_l2t_err_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_28_63:36;
uint64_t lck_intena2:1;
uint64_t lckerr2:1;
@ -113,8 +183,25 @@ union cvmx_l2t_err {
uint64_t ded_intena:1;
uint64_t sec_intena:1;
uint64_t ecc_ena:1;
#else
uint64_t ecc_ena:1;
uint64_t sec_intena:1;
uint64_t ded_intena:1;
uint64_t sec_err:1;
uint64_t ded_err:1;
uint64_t fsyn:6;
uint64_t fadr:7;
uint64_t reserved_18_20:3;
uint64_t fset:3;
uint64_t lckerr:1;
uint64_t lck_intena:1;
uint64_t lckerr2:1;
uint64_t lck_intena2:1;
uint64_t reserved_28_63:36;
#endif
} cn50xx;
struct cvmx_l2t_err_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_28_63:36;
uint64_t lck_intena2:1;
uint64_t lckerr2:1;
@ -129,6 +216,22 @@ union cvmx_l2t_err {
uint64_t ded_intena:1;
uint64_t sec_intena:1;
uint64_t ecc_ena:1;
#else
uint64_t ecc_ena:1;
uint64_t sec_intena:1;
uint64_t ded_intena:1;
uint64_t sec_err:1;
uint64_t ded_err:1;
uint64_t fsyn:6;
uint64_t fadr:9;
uint64_t reserved_20_20:1;
uint64_t fset:3;
uint64_t lckerr:1;
uint64_t lck_intena:1;
uint64_t lckerr2:1;
uint64_t lck_intena2:1;
uint64_t reserved_28_63:36;
#endif
} cn52xx;
struct cvmx_l2t_err_cn52xx cn52xxp1;
struct cvmx_l2t_err_s cn56xx;

67
arch/mips/include/asm/octeon/cvmx-led-defs.h
View File

@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2010 Cavium Networks
* Copyright (c) 2003-2012 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@ -45,8 +45,13 @@
union cvmx_led_blink {
uint64_t u64;
struct cvmx_led_blink_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63:56;
uint64_t rate:8;
#else
uint64_t rate:8;
uint64_t reserved_8_63:56;
#endif
} s;
struct cvmx_led_blink_s cn38xx;
struct cvmx_led_blink_s cn38xxp2;
@ -59,8 +64,13 @@ union cvmx_led_blink {
union cvmx_led_clk_phase {
uint64_t u64;
struct cvmx_led_clk_phase_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_7_63:57;
uint64_t phase:7;
#else
uint64_t phase:7;
uint64_t reserved_7_63:57;
#endif
} s;
struct cvmx_led_clk_phase_s cn38xx;
struct cvmx_led_clk_phase_s cn38xxp2;
@ -73,8 +83,13 @@ union cvmx_led_clk_phase {
union cvmx_led_cylon {
uint64_t u64;
struct cvmx_led_cylon_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t rate:16;
#else
uint64_t rate:16;
uint64_t reserved_16_63:48;
#endif
} s;
struct cvmx_led_cylon_s cn38xx;
struct cvmx_led_cylon_s cn38xxp2;
@ -87,8 +102,13 @@ union cvmx_led_cylon {
union cvmx_led_dbg {
uint64_t u64;
struct cvmx_led_dbg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63:63;
uint64_t dbg_en:1;
#else
uint64_t dbg_en:1;
uint64_t reserved_1_63:63;
#endif
} s;
struct cvmx_led_dbg_s cn38xx;
struct cvmx_led_dbg_s cn38xxp2;
@ -101,8 +121,13 @@ union cvmx_led_dbg {
union cvmx_led_en {
uint64_t u64;
struct cvmx_led_en_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63:63;
uint64_t en:1;
#else
uint64_t en:1;
uint64_t reserved_1_63:63;
#endif
} s;
struct cvmx_led_en_s cn38xx;
struct cvmx_led_en_s cn38xxp2;
@ -115,8 +140,13 @@ union cvmx_led_en {
union cvmx_led_polarity {
uint64_t u64;
struct cvmx_led_polarity_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63:63;
uint64_t polarity:1;
#else
uint64_t polarity:1;
uint64_t reserved_1_63:63;
#endif
} s;
struct cvmx_led_polarity_s cn38xx;
struct cvmx_led_polarity_s cn38xxp2;
@ -129,8 +159,13 @@ union cvmx_led_polarity {
union cvmx_led_prt {
uint64_t u64;
struct cvmx_led_prt_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63:56;
uint64_t prt_en:8;
#else
uint64_t prt_en:8;
uint64_t reserved_8_63:56;
#endif
} s;
struct cvmx_led_prt_s cn38xx;
struct cvmx_led_prt_s cn38xxp2;
@ -143,8 +178,13 @@ union cvmx_led_prt {
union cvmx_led_prt_fmt {
uint64_t u64;
struct cvmx_led_prt_fmt_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63:60;
uint64_t format:4;
#else
uint64_t format:4;
uint64_t reserved_4_63:60;
#endif
} s;
struct cvmx_led_prt_fmt_s cn38xx;
struct cvmx_led_prt_fmt_s cn38xxp2;
@ -157,8 +197,13 @@ union cvmx_led_prt_fmt {
union cvmx_led_prt_statusx {
uint64_t u64;
struct cvmx_led_prt_statusx_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_6_63:58;
uint64_t status:6;
#else
uint64_t status:6;
uint64_t reserved_6_63:58;
#endif
} s;
struct cvmx_led_prt_statusx_s cn38xx;
struct cvmx_led_prt_statusx_s cn38xxp2;
@ -171,8 +216,13 @@ union cvmx_led_prt_statusx {
union cvmx_led_udd_cntx {
uint64_t u64;
struct cvmx_led_udd_cntx_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_6_63:58;
uint64_t cnt:6;
#else
uint64_t cnt:6;
uint64_t reserved_6_63:58;
#endif
} s;
struct cvmx_led_udd_cntx_s cn38xx;
struct cvmx_led_udd_cntx_s cn38xxp2;
@ -185,8 +235,13 @@ union cvmx_led_udd_cntx {
union cvmx_led_udd_datx {
uint64_t u64;
struct cvmx_led_udd_datx_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
uint64_t dat:32;
#else
uint64_t dat:32;
uint64_t reserved_32_63:32;
#endif
} s;
struct cvmx_led_udd_datx_s cn38xx;
struct cvmx_led_udd_datx_s cn38xxp2;
@ -199,8 +254,13 @@ union cvmx_led_udd_datx {
union cvmx_led_udd_dat_clrx {
uint64_t u64;
struct cvmx_led_udd_dat_clrx_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
uint64_t clr:32;
#else
uint64_t clr:32;
uint64_t reserved_32_63:32;
#endif
} s;
struct cvmx_led_udd_dat_clrx_s cn38xx;
struct cvmx_led_udd_dat_clrx_s cn38xxp2;
@ -213,8 +273,13 @@ union cvmx_led_udd_dat_clrx {
union cvmx_led_udd_dat_setx {
uint64_t u64;
struct cvmx_led_udd_dat_setx_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
uint64_t set:32;
#else
uint64_t set:32;
uint64_t reserved_32_63:32;
#endif
} s;
struct cvmx_led_udd_dat_setx_s cn38xx;
struct cvmx_led_udd_dat_setx_s cn38xxp2;

1897
arch/mips/include/asm/octeon/cvmx-mio-defs.h
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234
arch/mips/include/asm/octeon/cvmx-mixx-defs.h
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@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2010 Cavium Networks
* Copyright (c) 2003-2012 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@ -47,6 +47,7 @@
union cvmx_mixx_bist {
uint64_t u64;
struct cvmx_mixx_bist_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_6_63:58;
uint64_t opfdat:1;
uint64_t mrgdat:1;
@ -54,24 +55,46 @@ union cvmx_mixx_bist {
uint64_t ipfdat:1;
uint64_t irfdat:1;
uint64_t orfdat:1;
#else
uint64_t orfdat:1;
uint64_t irfdat:1;
uint64_t ipfdat:1;
uint64_t mrqdat:1;
uint64_t mrgdat:1;
uint64_t opfdat:1;
uint64_t reserved_6_63:58;
#endif
} s;
struct cvmx_mixx_bist_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63:60;
uint64_t mrqdat:1;
uint64_t ipfdat:1;
uint64_t irfdat:1;
uint64_t orfdat:1;
#else
uint64_t orfdat:1;
uint64_t irfdat:1;
uint64_t ipfdat:1;
uint64_t mrqdat:1;
uint64_t reserved_4_63:60;
#endif
} cn52xx;
struct cvmx_mixx_bist_cn52xx cn52xxp1;
struct cvmx_mixx_bist_cn52xx cn56xx;
struct cvmx_mixx_bist_cn52xx cn56xxp1;
struct cvmx_mixx_bist_s cn61xx;
struct cvmx_mixx_bist_s cn63xx;
struct cvmx_mixx_bist_s cn63xxp1;
struct cvmx_mixx_bist_s cn66xx;
struct cvmx_mixx_bist_s cn68xx;
struct cvmx_mixx_bist_s cn68xxp1;
};
union cvmx_mixx_ctl {
uint64_t u64;
struct cvmx_mixx_ctl_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63:52;
uint64_t ts_thresh:4;
uint64_t crc_strip:1;
@ -81,8 +104,20 @@ union cvmx_mixx_ctl {
uint64_t lendian:1;
uint64_t nbtarb:1;
uint64_t mrq_hwm:2;
#else
uint64_t mrq_hwm:2;
uint64_t nbtarb:1;
uint64_t lendian:1;
uint64_t reset:1;
uint64_t en:1;
uint64_t busy:1;
uint64_t crc_strip:1;
uint64_t ts_thresh:4;
uint64_t reserved_12_63:52;
#endif
} s;
struct cvmx_mixx_ctl_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63:56;
uint64_t crc_strip:1;
uint64_t busy:1;
@ -91,17 +126,32 @@ union cvmx_mixx_ctl {
uint64_t lendian:1;
uint64_t nbtarb:1;
uint64_t mrq_hwm:2;
#else
uint64_t mrq_hwm:2;
uint64_t nbtarb:1;
uint64_t lendian:1;
uint64_t reset:1;
uint64_t en:1;
uint64_t busy:1;
uint64_t crc_strip:1;
uint64_t reserved_8_63:56;
#endif
} cn52xx;
struct cvmx_mixx_ctl_cn52xx cn52xxp1;
struct cvmx_mixx_ctl_cn52xx cn56xx;
struct cvmx_mixx_ctl_cn52xx cn56xxp1;
struct cvmx_mixx_ctl_s cn61xx;
struct cvmx_mixx_ctl_s cn63xx;
struct cvmx_mixx_ctl_s cn63xxp1;
struct cvmx_mixx_ctl_s cn66xx;
struct cvmx_mixx_ctl_s cn68xx;
struct cvmx_mixx_ctl_s cn68xxp1;
};
union cvmx_mixx_intena {
uint64_t u64;
struct cvmx_mixx_intena_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63:56;
uint64_t tsena:1;
uint64_t orunena:1;
@ -111,8 +161,20 @@ union cvmx_mixx_intena {
uint64_t othena:1;
uint64_t ivfena:1;
uint64_t ovfena:1;
#else
uint64_t ovfena:1;
uint64_t ivfena:1;
uint64_t othena:1;
uint64_t ithena:1;
uint64_t data_drpena:1;
uint64_t irunena:1;
uint64_t orunena:1;
uint64_t tsena:1;
uint64_t reserved_8_63:56;
#endif
} s;
struct cvmx_mixx_intena_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_7_63:57;
uint64_t orunena:1;
uint64_t irunena:1;
@ -121,84 +183,148 @@ union cvmx_mixx_intena {
uint64_t othena:1;
uint64_t ivfena:1;
uint64_t ovfena:1;
#else
uint64_t ovfena:1;
uint64_t ivfena:1;
uint64_t othena:1;
uint64_t ithena:1;
uint64_t data_drpena:1;
uint64_t irunena:1;
uint64_t orunena:1;
uint64_t reserved_7_63:57;
#endif
} cn52xx;
struct cvmx_mixx_intena_cn52xx cn52xxp1;
struct cvmx_mixx_intena_cn52xx cn56xx;
struct cvmx_mixx_intena_cn52xx cn56xxp1;
struct cvmx_mixx_intena_s cn61xx;
struct cvmx_mixx_intena_s cn63xx;
struct cvmx_mixx_intena_s cn63xxp1;
struct cvmx_mixx_intena_s cn66xx;
struct cvmx_mixx_intena_s cn68xx;
struct cvmx_mixx_intena_s cn68xxp1;
};
union cvmx_mixx_ircnt {
uint64_t u64;
struct cvmx_mixx_ircnt_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63:44;
uint64_t ircnt:20;
#else
uint64_t ircnt:20;
uint64_t reserved_20_63:44;
#endif
} s;
struct cvmx_mixx_ircnt_s cn52xx;
struct cvmx_mixx_ircnt_s cn52xxp1;
struct cvmx_mixx_ircnt_s cn56xx;
struct cvmx_mixx_ircnt_s cn56xxp1;
struct cvmx_mixx_ircnt_s cn61xx;
struct cvmx_mixx_ircnt_s cn63xx;
struct cvmx_mixx_ircnt_s cn63xxp1;
struct cvmx_mixx_ircnt_s cn66xx;
struct cvmx_mixx_ircnt_s cn68xx;
struct cvmx_mixx_ircnt_s cn68xxp1;
};
union cvmx_mixx_irhwm {
uint64_t u64;
struct cvmx_mixx_irhwm_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_40_63:24;
uint64_t ibplwm:20;
uint64_t irhwm:20;
#else
uint64_t irhwm:20;
uint64_t ibplwm:20;
uint64_t reserved_40_63:24;
#endif
} s;
struct cvmx_mixx_irhwm_s cn52xx;
struct cvmx_mixx_irhwm_s cn52xxp1;
struct cvmx_mixx_irhwm_s cn56xx;
struct cvmx_mixx_irhwm_s cn56xxp1;
struct cvmx_mixx_irhwm_s cn61xx;
struct cvmx_mixx_irhwm_s cn63xx;
struct cvmx_mixx_irhwm_s cn63xxp1;
struct cvmx_mixx_irhwm_s cn66xx;
struct cvmx_mixx_irhwm_s cn68xx;
struct cvmx_mixx_irhwm_s cn68xxp1;
};
union cvmx_mixx_iring1 {
uint64_t u64;
struct cvmx_mixx_iring1_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_60_63:4;
uint64_t isize:20;
uint64_t ibase:37;
uint64_t reserved_0_2:3;
#else
uint64_t reserved_0_2:3;
uint64_t ibase:37;
uint64_t isize:20;
uint64_t reserved_60_63:4;
#endif
} s;
struct cvmx_mixx_iring1_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_60_63:4;
uint64_t isize:20;
uint64_t reserved_36_39:4;
uint64_t ibase:33;
uint64_t reserved_0_2:3;
#else
uint64_t reserved_0_2:3;
uint64_t ibase:33;
uint64_t reserved_36_39:4;
uint64_t isize:20;
uint64_t reserved_60_63:4;
#endif
} cn52xx;
struct cvmx_mixx_iring1_cn52xx cn52xxp1;
struct cvmx_mixx_iring1_cn52xx cn56xx;
struct cvmx_mixx_iring1_cn52xx cn56xxp1;
struct cvmx_mixx_iring1_s cn61xx;
struct cvmx_mixx_iring1_s cn63xx;
struct cvmx_mixx_iring1_s cn63xxp1;
struct cvmx_mixx_iring1_s cn66xx;
struct cvmx_mixx_iring1_s cn68xx;
struct cvmx_mixx_iring1_s cn68xxp1;
};
union cvmx_mixx_iring2 {
uint64_t u64;
struct cvmx_mixx_iring2_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_52_63:12;
uint64_t itlptr:20;
uint64_t reserved_20_31:12;
uint64_t idbell:20;
#else
uint64_t idbell:20;
uint64_t reserved_20_31:12;
uint64_t itlptr:20;
uint64_t reserved_52_63:12;
#endif
} s;
struct cvmx_mixx_iring2_s cn52xx;
struct cvmx_mixx_iring2_s cn52xxp1;
struct cvmx_mixx_iring2_s cn56xx;
struct cvmx_mixx_iring2_s cn56xxp1;
struct cvmx_mixx_iring2_s cn61xx;
struct cvmx_mixx_iring2_s cn63xx;
struct cvmx_mixx_iring2_s cn63xxp1;
struct cvmx_mixx_iring2_s cn66xx;
struct cvmx_mixx_iring2_s cn68xx;
struct cvmx_mixx_iring2_s cn68xxp1;
};
union cvmx_mixx_isr {
uint64_t u64;
struct cvmx_mixx_isr_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63:56;
uint64_t ts:1;
uint64_t orun:1;
@ -208,8 +334,20 @@ union cvmx_mixx_isr {
uint64_t orthresh:1;
uint64_t idblovf:1;
uint64_t odblovf:1;
#else
uint64_t odblovf:1;
uint64_t idblovf:1;
uint64_t orthresh:1;
uint64_t irthresh:1;
uint64_t data_drp:1;
uint64_t irun:1;
uint64_t orun:1;
uint64_t ts:1;
uint64_t reserved_8_63:56;
#endif
} s;
struct cvmx_mixx_isr_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_7_63:57;
uint64_t orun:1;
uint64_t irun:1;
@ -218,117 +356,211 @@ union cvmx_mixx_isr {
uint64_t orthresh:1;
uint64_t idblovf:1;
uint64_t odblovf:1;
#else
uint64_t odblovf:1;
uint64_t idblovf:1;
uint64_t orthresh:1;
uint64_t irthresh:1;
uint64_t data_drp:1;
uint64_t irun:1;
uint64_t orun:1;
uint64_t reserved_7_63:57;
#endif
} cn52xx;
struct cvmx_mixx_isr_cn52xx cn52xxp1;
struct cvmx_mixx_isr_cn52xx cn56xx;
struct cvmx_mixx_isr_cn52xx cn56xxp1;
struct cvmx_mixx_isr_s cn61xx;
struct cvmx_mixx_isr_s cn63xx;
struct cvmx_mixx_isr_s cn63xxp1;
struct cvmx_mixx_isr_s cn66xx;
struct cvmx_mixx_isr_s cn68xx;
struct cvmx_mixx_isr_s cn68xxp1;
};
union cvmx_mixx_orcnt {
uint64_t u64;
struct cvmx_mixx_orcnt_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63:44;
uint64_t orcnt:20;
#else
uint64_t orcnt:20;
uint64_t reserved_20_63:44;
#endif
} s;
struct cvmx_mixx_orcnt_s cn52xx;
struct cvmx_mixx_orcnt_s cn52xxp1;
struct cvmx_mixx_orcnt_s cn56xx;
struct cvmx_mixx_orcnt_s cn56xxp1;
struct cvmx_mixx_orcnt_s cn61xx;
struct cvmx_mixx_orcnt_s cn63xx;
struct cvmx_mixx_orcnt_s cn63xxp1;
struct cvmx_mixx_orcnt_s cn66xx;
struct cvmx_mixx_orcnt_s cn68xx;
struct cvmx_mixx_orcnt_s cn68xxp1;
};
union cvmx_mixx_orhwm {
uint64_t u64;
struct cvmx_mixx_orhwm_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63:44;
uint64_t orhwm:20;
#else
uint64_t orhwm:20;
uint64_t reserved_20_63:44;
#endif
} s;
struct cvmx_mixx_orhwm_s cn52xx;
struct cvmx_mixx_orhwm_s cn52xxp1;
struct cvmx_mixx_orhwm_s cn56xx;
struct cvmx_mixx_orhwm_s cn56xxp1;
struct cvmx_mixx_orhwm_s cn61xx;
struct cvmx_mixx_orhwm_s cn63xx;
struct cvmx_mixx_orhwm_s cn63xxp1;
struct cvmx_mixx_orhwm_s cn66xx;
struct cvmx_mixx_orhwm_s cn68xx;
struct cvmx_mixx_orhwm_s cn68xxp1;
};
union cvmx_mixx_oring1 {
uint64_t u64;
struct cvmx_mixx_oring1_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_60_63:4;
uint64_t osize:20;
uint64_t obase:37;
uint64_t reserved_0_2:3;
#else
uint64_t reserved_0_2:3;
uint64_t obase:37;
uint64_t osize:20;
uint64_t reserved_60_63:4;
#endif
} s;
struct cvmx_mixx_oring1_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_60_63:4;
uint64_t osize:20;
uint64_t reserved_36_39:4;
uint64_t obase:33;
uint64_t reserved_0_2:3;
#else
uint64_t reserved_0_2:3;
uint64_t obase:33;
uint64_t reserved_36_39:4;
uint64_t osize:20;
uint64_t reserved_60_63:4;
#endif
} cn52xx;
struct cvmx_mixx_oring1_cn52xx cn52xxp1;
struct cvmx_mixx_oring1_cn52xx cn56xx;
struct cvmx_mixx_oring1_cn52xx cn56xxp1;
struct cvmx_mixx_oring1_s cn61xx;
struct cvmx_mixx_oring1_s cn63xx;
struct cvmx_mixx_oring1_s cn63xxp1;
struct cvmx_mixx_oring1_s cn66xx;
struct cvmx_mixx_oring1_s cn68xx;
struct cvmx_mixx_oring1_s cn68xxp1;
};
union cvmx_mixx_oring2 {
uint64_t u64;
struct cvmx_mixx_oring2_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_52_63:12;
uint64_t otlptr:20;
uint64_t reserved_20_31:12;
uint64_t odbell:20;
#else
uint64_t odbell:20;
uint64_t reserved_20_31:12;
uint64_t otlptr:20;
uint64_t reserved_52_63:12;
#endif
} s;
struct cvmx_mixx_oring2_s cn52xx;
struct cvmx_mixx_oring2_s cn52xxp1;
struct cvmx_mixx_oring2_s cn56xx;
struct cvmx_mixx_oring2_s cn56xxp1;
struct cvmx_mixx_oring2_s cn61xx;
struct cvmx_mixx_oring2_s cn63xx;
struct cvmx_mixx_oring2_s cn63xxp1;
struct cvmx_mixx_oring2_s cn66xx;
struct cvmx_mixx_oring2_s cn68xx;
struct cvmx_mixx_oring2_s cn68xxp1;
};
union cvmx_mixx_remcnt {
uint64_t u64;
struct cvmx_mixx_remcnt_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_52_63:12;
uint64_t iremcnt:20;
uint64_t reserved_20_31:12;
uint64_t oremcnt:20;
#else
uint64_t oremcnt:20;
uint64_t reserved_20_31:12;
uint64_t iremcnt:20;
uint64_t reserved_52_63:12;
#endif
} s;
struct cvmx_mixx_remcnt_s cn52xx;
struct cvmx_mixx_remcnt_s cn52xxp1;
struct cvmx_mixx_remcnt_s cn56xx;
struct cvmx_mixx_remcnt_s cn56xxp1;
struct cvmx_mixx_remcnt_s cn61xx;
struct cvmx_mixx_remcnt_s cn63xx;
struct cvmx_mixx_remcnt_s cn63xxp1;
struct cvmx_mixx_remcnt_s cn66xx;
struct cvmx_mixx_remcnt_s cn68xx;
struct cvmx_mixx_remcnt_s cn68xxp1;
};
union cvmx_mixx_tsctl {
uint64_t u64;
struct cvmx_mixx_tsctl_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_21_63:43;
uint64_t tsavl:5;
uint64_t reserved_13_15:3;
uint64_t tstot:5;
uint64_t reserved_5_7:3;
uint64_t tscnt:5;
#else
uint64_t tscnt:5;
uint64_t reserved_5_7:3;
uint64_t tstot:5;
uint64_t reserved_13_15:3;
uint64_t tsavl:5;
uint64_t reserved_21_63:43;
#endif
} s;
struct cvmx_mixx_tsctl_s cn61xx;
struct cvmx_mixx_tsctl_s cn63xx;
struct cvmx_mixx_tsctl_s cn63xxp1;
struct cvmx_mixx_tsctl_s cn66xx;
struct cvmx_mixx_tsctl_s cn68xx;
struct cvmx_mixx_tsctl_s cn68xxp1;
};
union cvmx_mixx_tstamp {
uint64_t u64;
struct cvmx_mixx_tstamp_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t tstamp:64;
#else
uint64_t tstamp:64;
#endif
} s;
struct cvmx_mixx_tstamp_s cn61xx;
struct cvmx_mixx_tstamp_s cn63xx;
struct cvmx_mixx_tstamp_s cn63xxp1;
struct cvmx_mixx_tstamp_s cn66xx;
struct cvmx_mixx_tstamp_s cn68xx;
struct cvmx_mixx_tstamp_s cn68xxp1;
};
#endif

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arch/mips/include/asm/octeon/cvmx-npei-defs.h
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arch/mips/include/asm/octeon/cvmx-npi-defs.h
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arch/mips/include/asm/octeon/cvmx-pci-defs.h
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arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
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arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
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@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2008 Cavium Networks
* Copyright (c) 2003-2012 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@ -28,44 +28,316 @@
#ifndef __CVMX_PCSX_DEFS_H__
#define __CVMX_PCSX_DEFS_H__
#define CVMX_PCSX_ANX_ADV_REG(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800B0001010ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSX_ANX_EXT_ST_REG(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800B0001028ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSX_ANX_LP_ABIL_REG(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800B0001018ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSX_ANX_RESULTS_REG(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800B0001020ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSX_INTX_EN_REG(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800B0001088ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSX_INTX_REG(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800B0001080ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSX_LINKX_TIMER_COUNT_REG(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800B0001040ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSX_LOG_ANLX_REG(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800B0001090ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSX_MISCX_CTL_REG(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800B0001078ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSX_MRX_CONTROL_REG(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800B0001000ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSX_MRX_STATUS_REG(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800B0001008ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSX_RXX_STATES_REG(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800B0001058ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSX_RXX_SYNC_REG(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800B0001050ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSX_SGMX_AN_ADV_REG(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800B0001068ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSX_SGMX_LP_ADV_REG(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800B0001070ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSX_TXX_STATES_REG(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800B0001060ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSX_TX_RXX_POLARITY_REG(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800B0001048ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
static inline uint64_t CVMX_PCSX_ANX_ADV_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_ANX_EXT_ST_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_ANX_LP_ABIL_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_ANX_RESULTS_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_INTX_EN_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_INTX_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_LINKX_TIMER_COUNT_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_LOG_ANLX_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_MISCX_CTL_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_MRX_CONTROL_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_MRX_STATUS_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_RXX_STATES_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_RXX_SYNC_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_SGMX_AN_ADV_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_SGMX_LP_ADV_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_TXX_STATES_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_TX_RXX_POLARITY_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
union cvmx_pcsx_anx_adv_reg {
uint64_t u64;
struct cvmx_pcsx_anx_adv_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t np:1;
uint64_t reserved_14_14:1;
@ -75,32 +347,67 @@ union cvmx_pcsx_anx_adv_reg {
uint64_t hfd:1;
uint64_t fd:1;
uint64_t reserved_0_4:5;
#else
uint64_t reserved_0_4:5;
uint64_t fd:1;
uint64_t hfd:1;
uint64_t pause:2;
uint64_t reserved_9_11:3;
uint64_t rem_flt:2;
uint64_t reserved_14_14:1;
uint64_t np:1;
uint64_t reserved_16_63:48;
#endif
} s;
struct cvmx_pcsx_anx_adv_reg_s cn52xx;
struct cvmx_pcsx_anx_adv_reg_s cn52xxp1;
struct cvmx_pcsx_anx_adv_reg_s cn56xx;
struct cvmx_pcsx_anx_adv_reg_s cn56xxp1;
struct cvmx_pcsx_anx_adv_reg_s cn61xx;
struct cvmx_pcsx_anx_adv_reg_s cn63xx;
struct cvmx_pcsx_anx_adv_reg_s cn63xxp1;
struct cvmx_pcsx_anx_adv_reg_s cn66xx;
struct cvmx_pcsx_anx_adv_reg_s cn68xx;
struct cvmx_pcsx_anx_adv_reg_s cn68xxp1;
struct cvmx_pcsx_anx_adv_reg_s cnf71xx;
};
union cvmx_pcsx_anx_ext_st_reg {
uint64_t u64;
struct cvmx_pcsx_anx_ext_st_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t thou_xfd:1;
uint64_t thou_xhd:1;
uint64_t thou_tfd:1;
uint64_t thou_thd:1;
uint64_t reserved_0_11:12;
#else
uint64_t reserved_0_11:12;
uint64_t thou_thd:1;
uint64_t thou_tfd:1;
uint64_t thou_xhd:1;
uint64_t thou_xfd:1;
uint64_t reserved_16_63:48;
#endif
} s;
struct cvmx_pcsx_anx_ext_st_reg_s cn52xx;
struct cvmx_pcsx_anx_ext_st_reg_s cn52xxp1;
struct cvmx_pcsx_anx_ext_st_reg_s cn56xx;
struct cvmx_pcsx_anx_ext_st_reg_s cn56xxp1;
struct cvmx_pcsx_anx_ext_st_reg_s cn61xx;
struct cvmx_pcsx_anx_ext_st_reg_s cn63xx;
struct cvmx_pcsx_anx_ext_st_reg_s cn63xxp1;
struct cvmx_pcsx_anx_ext_st_reg_s cn66xx;
struct cvmx_pcsx_anx_ext_st_reg_s cn68xx;
struct cvmx_pcsx_anx_ext_st_reg_s cn68xxp1;
struct cvmx_pcsx_anx_ext_st_reg_s cnf71xx;
};
union cvmx_pcsx_anx_lp_abil_reg {
uint64_t u64;
struct cvmx_pcsx_anx_lp_abil_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t np:1;
uint64_t ack:1;
@ -110,32 +417,100 @@ union cvmx_pcsx_anx_lp_abil_reg {
uint64_t hfd:1;
uint64_t fd:1;
uint64_t reserved_0_4:5;
#else
uint64_t reserved_0_4:5;
uint64_t fd:1;
uint64_t hfd:1;
uint64_t pause:2;
uint64_t reserved_9_11:3;
uint64_t rem_flt:2;
uint64_t ack:1;
uint64_t np:1;
uint64_t reserved_16_63:48;
#endif
} s;
struct cvmx_pcsx_anx_lp_abil_reg_s cn52xx;
struct cvmx_pcsx_anx_lp_abil_reg_s cn52xxp1;
struct cvmx_pcsx_anx_lp_abil_reg_s cn56xx;
struct cvmx_pcsx_anx_lp_abil_reg_s cn56xxp1;
struct cvmx_pcsx_anx_lp_abil_reg_s cn61xx;
struct cvmx_pcsx_anx_lp_abil_reg_s cn63xx;
struct cvmx_pcsx_anx_lp_abil_reg_s cn63xxp1;
struct cvmx_pcsx_anx_lp_abil_reg_s cn66xx;
struct cvmx_pcsx_anx_lp_abil_reg_s cn68xx;
struct cvmx_pcsx_anx_lp_abil_reg_s cn68xxp1;
struct cvmx_pcsx_anx_lp_abil_reg_s cnf71xx;
};
union cvmx_pcsx_anx_results_reg {
uint64_t u64;
struct cvmx_pcsx_anx_results_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_7_63:57;
uint64_t pause:2;
uint64_t spd:2;
uint64_t an_cpt:1;
uint64_t dup:1;
uint64_t link_ok:1;
#else
uint64_t link_ok:1;
uint64_t dup:1;
uint64_t an_cpt:1;
uint64_t spd:2;
uint64_t pause:2;
uint64_t reserved_7_63:57;
#endif
} s;
struct cvmx_pcsx_anx_results_reg_s cn52xx;
struct cvmx_pcsx_anx_results_reg_s cn52xxp1;
struct cvmx_pcsx_anx_results_reg_s cn56xx;
struct cvmx_pcsx_anx_results_reg_s cn56xxp1;
struct cvmx_pcsx_anx_results_reg_s cn61xx;
struct cvmx_pcsx_anx_results_reg_s cn63xx;
struct cvmx_pcsx_anx_results_reg_s cn63xxp1;
struct cvmx_pcsx_anx_results_reg_s cn66xx;
struct cvmx_pcsx_anx_results_reg_s cn68xx;
struct cvmx_pcsx_anx_results_reg_s cn68xxp1;
struct cvmx_pcsx_anx_results_reg_s cnf71xx;
};
union cvmx_pcsx_intx_en_reg {
uint64_t u64;
struct cvmx_pcsx_intx_en_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_13_63:51;
uint64_t dbg_sync_en:1;
uint64_t dup:1;
uint64_t sync_bad_en:1;
uint64_t an_bad_en:1;
uint64_t rxlock_en:1;
uint64_t rxbad_en:1;
uint64_t rxerr_en:1;
uint64_t txbad_en:1;
uint64_t txfifo_en:1;
uint64_t txfifu_en:1;
uint64_t an_err_en:1;
uint64_t xmit_en:1;
uint64_t lnkspd_en:1;
#else
uint64_t lnkspd_en:1;
uint64_t xmit_en:1;
uint64_t an_err_en:1;
uint64_t txfifu_en:1;
uint64_t txfifo_en:1;
uint64_t txbad_en:1;
uint64_t rxerr_en:1;
uint64_t rxbad_en:1;
uint64_t rxlock_en:1;
uint64_t an_bad_en:1;
uint64_t sync_bad_en:1;
uint64_t dup:1;
uint64_t dbg_sync_en:1;
uint64_t reserved_13_63:51;
#endif
} s;
struct cvmx_pcsx_intx_en_reg_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63:52;
uint64_t dup:1;
uint64_t sync_bad_en:1;
@ -149,16 +524,71 @@ union cvmx_pcsx_intx_en_reg {
uint64_t an_err_en:1;
uint64_t xmit_en:1;
uint64_t lnkspd_en:1;
} s;
struct cvmx_pcsx_intx_en_reg_s cn52xx;
struct cvmx_pcsx_intx_en_reg_s cn52xxp1;
struct cvmx_pcsx_intx_en_reg_s cn56xx;
struct cvmx_pcsx_intx_en_reg_s cn56xxp1;
#else
uint64_t lnkspd_en:1;
uint64_t xmit_en:1;
uint64_t an_err_en:1;
uint64_t txfifu_en:1;
uint64_t txfifo_en:1;
uint64_t txbad_en:1;
uint64_t rxerr_en:1;
uint64_t rxbad_en:1;
uint64_t rxlock_en:1;
uint64_t an_bad_en:1;
uint64_t sync_bad_en:1;
uint64_t dup:1;
uint64_t reserved_12_63:52;
#endif
} cn52xx;
struct cvmx_pcsx_intx_en_reg_cn52xx cn52xxp1;
struct cvmx_pcsx_intx_en_reg_cn52xx cn56xx;
struct cvmx_pcsx_intx_en_reg_cn52xx cn56xxp1;
struct cvmx_pcsx_intx_en_reg_s cn61xx;
struct cvmx_pcsx_intx_en_reg_s cn63xx;
struct cvmx_pcsx_intx_en_reg_s cn63xxp1;
struct cvmx_pcsx_intx_en_reg_s cn66xx;
struct cvmx_pcsx_intx_en_reg_s cn68xx;
struct cvmx_pcsx_intx_en_reg_s cn68xxp1;
struct cvmx_pcsx_intx_en_reg_s cnf71xx;
};
union cvmx_pcsx_intx_reg {
uint64_t u64;
struct cvmx_pcsx_intx_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_13_63:51;
uint64_t dbg_sync:1;
uint64_t dup:1;
uint64_t sync_bad:1;
uint64_t an_bad:1;
uint64_t rxlock:1;
uint64_t rxbad:1;
uint64_t rxerr:1;
uint64_t txbad:1;
uint64_t txfifo:1;
uint64_t txfifu:1;
uint64_t an_err:1;
uint64_t xmit:1;
uint64_t lnkspd:1;
#else
uint64_t lnkspd:1;
uint64_t xmit:1;
uint64_t an_err:1;
uint64_t txfifu:1;
uint64_t txfifo:1;
uint64_t txbad:1;
uint64_t rxerr:1;
uint64_t rxbad:1;
uint64_t rxlock:1;
uint64_t an_bad:1;
uint64_t sync_bad:1;
uint64_t dup:1;
uint64_t dbg_sync:1;
uint64_t reserved_13_63:51;
#endif
} s;
struct cvmx_pcsx_intx_reg_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63:52;
uint64_t dup:1;
uint64_t sync_bad:1;
@ -172,42 +602,90 @@ union cvmx_pcsx_intx_reg {
uint64_t an_err:1;
uint64_t xmit:1;
uint64_t lnkspd:1;
} s;
struct cvmx_pcsx_intx_reg_s cn52xx;
struct cvmx_pcsx_intx_reg_s cn52xxp1;
struct cvmx_pcsx_intx_reg_s cn56xx;
struct cvmx_pcsx_intx_reg_s cn56xxp1;
#else
uint64_t lnkspd:1;
uint64_t xmit:1;
uint64_t an_err:1;
uint64_t txfifu:1;
uint64_t txfifo:1;
uint64_t txbad:1;
uint64_t rxerr:1;
uint64_t rxbad:1;
uint64_t rxlock:1;
uint64_t an_bad:1;
uint64_t sync_bad:1;
uint64_t dup:1;
uint64_t reserved_12_63:52;
#endif
} cn52xx;
struct cvmx_pcsx_intx_reg_cn52xx cn52xxp1;
struct cvmx_pcsx_intx_reg_cn52xx cn56xx;
struct cvmx_pcsx_intx_reg_cn52xx cn56xxp1;
struct cvmx_pcsx_intx_reg_s cn61xx;
struct cvmx_pcsx_intx_reg_s cn63xx;
struct cvmx_pcsx_intx_reg_s cn63xxp1;
struct cvmx_pcsx_intx_reg_s cn66xx;
struct cvmx_pcsx_intx_reg_s cn68xx;
struct cvmx_pcsx_intx_reg_s cn68xxp1;
struct cvmx_pcsx_intx_reg_s cnf71xx;
};
union cvmx_pcsx_linkx_timer_count_reg {
uint64_t u64;
struct cvmx_pcsx_linkx_timer_count_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t count:16;
#else
uint64_t count:16;
uint64_t reserved_16_63:48;
#endif
} s;
struct cvmx_pcsx_linkx_timer_count_reg_s cn52xx;
struct cvmx_pcsx_linkx_timer_count_reg_s cn52xxp1;
struct cvmx_pcsx_linkx_timer_count_reg_s cn56xx;
struct cvmx_pcsx_linkx_timer_count_reg_s cn56xxp1;
struct cvmx_pcsx_linkx_timer_count_reg_s cn61xx;
struct cvmx_pcsx_linkx_timer_count_reg_s cn63xx;
struct cvmx_pcsx_linkx_timer_count_reg_s cn63xxp1;
struct cvmx_pcsx_linkx_timer_count_reg_s cn66xx;
struct cvmx_pcsx_linkx_timer_count_reg_s cn68xx;
struct cvmx_pcsx_linkx_timer_count_reg_s cn68xxp1;
struct cvmx_pcsx_linkx_timer_count_reg_s cnf71xx;
};
union cvmx_pcsx_log_anlx_reg {
uint64_t u64;
struct cvmx_pcsx_log_anlx_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63:60;
uint64_t lafifovfl:1;
uint64_t la_en:1;
uint64_t pkt_sz:2;
#else
uint64_t pkt_sz:2;
uint64_t la_en:1;
uint64_t lafifovfl:1;
uint64_t reserved_4_63:60;
#endif
} s;
struct cvmx_pcsx_log_anlx_reg_s cn52xx;
struct cvmx_pcsx_log_anlx_reg_s cn52xxp1;
struct cvmx_pcsx_log_anlx_reg_s cn56xx;
struct cvmx_pcsx_log_anlx_reg_s cn56xxp1;
struct cvmx_pcsx_log_anlx_reg_s cn61xx;
struct cvmx_pcsx_log_anlx_reg_s cn63xx;
struct cvmx_pcsx_log_anlx_reg_s cn63xxp1;
struct cvmx_pcsx_log_anlx_reg_s cn66xx;
struct cvmx_pcsx_log_anlx_reg_s cn68xx;
struct cvmx_pcsx_log_anlx_reg_s cn68xxp1;
struct cvmx_pcsx_log_anlx_reg_s cnf71xx;
};
union cvmx_pcsx_miscx_ctl_reg {
uint64_t u64;
struct cvmx_pcsx_miscx_ctl_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_13_63:51;
uint64_t sgmii:1;
uint64_t gmxeno:1;
@ -216,16 +694,34 @@ union cvmx_pcsx_miscx_ctl_reg {
uint64_t mode:1;
uint64_t an_ovrd:1;
uint64_t samp_pt:7;
#else
uint64_t samp_pt:7;
uint64_t an_ovrd:1;
uint64_t mode:1;
uint64_t mac_phy:1;
uint64_t loopbck2:1;
uint64_t gmxeno:1;
uint64_t sgmii:1;
uint64_t reserved_13_63:51;
#endif
} s;
struct cvmx_pcsx_miscx_ctl_reg_s cn52xx;
struct cvmx_pcsx_miscx_ctl_reg_s cn52xxp1;
struct cvmx_pcsx_miscx_ctl_reg_s cn56xx;
struct cvmx_pcsx_miscx_ctl_reg_s cn56xxp1;
struct cvmx_pcsx_miscx_ctl_reg_s cn61xx;
struct cvmx_pcsx_miscx_ctl_reg_s cn63xx;
struct cvmx_pcsx_miscx_ctl_reg_s cn63xxp1;
struct cvmx_pcsx_miscx_ctl_reg_s cn66xx;
struct cvmx_pcsx_miscx_ctl_reg_s cn68xx;
struct cvmx_pcsx_miscx_ctl_reg_s cn68xxp1;
struct cvmx_pcsx_miscx_ctl_reg_s cnf71xx;
};
union cvmx_pcsx_mrx_control_reg {
uint64_t u64;
struct cvmx_pcsx_mrx_control_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t reset:1;
uint64_t loopbck1:1;
@ -239,16 +735,39 @@ union cvmx_pcsx_mrx_control_reg {
uint64_t spdmsb:1;
uint64_t uni:1;
uint64_t reserved_0_4:5;
#else
uint64_t reserved_0_4:5;
uint64_t uni:1;
uint64_t spdmsb:1;
uint64_t coltst:1;
uint64_t dup:1;
uint64_t rst_an:1;
uint64_t reserved_10_10:1;
uint64_t pwr_dn:1;
uint64_t an_en:1;
uint64_t spdlsb:1;
uint64_t loopbck1:1;
uint64_t reset:1;
uint64_t reserved_16_63:48;
#endif
} s;
struct cvmx_pcsx_mrx_control_reg_s cn52xx;
struct cvmx_pcsx_mrx_control_reg_s cn52xxp1;
struct cvmx_pcsx_mrx_control_reg_s cn56xx;
struct cvmx_pcsx_mrx_control_reg_s cn56xxp1;
struct cvmx_pcsx_mrx_control_reg_s cn61xx;
struct cvmx_pcsx_mrx_control_reg_s cn63xx;
struct cvmx_pcsx_mrx_control_reg_s cn63xxp1;
struct cvmx_pcsx_mrx_control_reg_s cn66xx;
struct cvmx_pcsx_mrx_control_reg_s cn68xx;
struct cvmx_pcsx_mrx_control_reg_s cn68xxp1;
struct cvmx_pcsx_mrx_control_reg_s cnf71xx;
};
union cvmx_pcsx_mrx_status_reg {
uint64_t u64;
struct cvmx_pcsx_mrx_status_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t hun_t4:1;
uint64_t hun_xfd:1;
@ -266,16 +785,43 @@ union cvmx_pcsx_mrx_status_reg {
uint64_t lnk_st:1;
uint64_t reserved_1_1:1;
uint64_t extnd:1;
#else
uint64_t extnd:1;
uint64_t reserved_1_1:1;
uint64_t lnk_st:1;
uint64_t an_abil:1;
uint64_t rm_flt:1;
uint64_t an_cpt:1;
uint64_t prb_sup:1;
uint64_t reserved_7_7:1;
uint64_t ext_st:1;
uint64_t hun_t2hd:1;
uint64_t hun_t2fd:1;
uint64_t ten_hd:1;
uint64_t ten_fd:1;
uint64_t hun_xhd:1;
uint64_t hun_xfd:1;
uint64_t hun_t4:1;
uint64_t reserved_16_63:48;
#endif
} s;
struct cvmx_pcsx_mrx_status_reg_s cn52xx;
struct cvmx_pcsx_mrx_status_reg_s cn52xxp1;
struct cvmx_pcsx_mrx_status_reg_s cn56xx;
struct cvmx_pcsx_mrx_status_reg_s cn56xxp1;
struct cvmx_pcsx_mrx_status_reg_s cn61xx;
struct cvmx_pcsx_mrx_status_reg_s cn63xx;
struct cvmx_pcsx_mrx_status_reg_s cn63xxp1;
struct cvmx_pcsx_mrx_status_reg_s cn66xx;
struct cvmx_pcsx_mrx_status_reg_s cn68xx;
struct cvmx_pcsx_mrx_status_reg_s cn68xxp1;
struct cvmx_pcsx_mrx_status_reg_s cnf71xx;
};
union cvmx_pcsx_rxx_states_reg {
uint64_t u64;
struct cvmx_pcsx_rxx_states_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t rx_bad:1;
uint64_t rx_st:5;
@ -283,29 +829,59 @@ union cvmx_pcsx_rxx_states_reg {
uint64_t sync:4;
uint64_t an_bad:1;
uint64_t an_st:4;
#else
uint64_t an_st:4;
uint64_t an_bad:1;
uint64_t sync:4;
uint64_t sync_bad:1;
uint64_t rx_st:5;
uint64_t rx_bad:1;
uint64_t reserved_16_63:48;
#endif
} s;
struct cvmx_pcsx_rxx_states_reg_s cn52xx;
struct cvmx_pcsx_rxx_states_reg_s cn52xxp1;
struct cvmx_pcsx_rxx_states_reg_s cn56xx;
struct cvmx_pcsx_rxx_states_reg_s cn56xxp1;
struct cvmx_pcsx_rxx_states_reg_s cn61xx;
struct cvmx_pcsx_rxx_states_reg_s cn63xx;
struct cvmx_pcsx_rxx_states_reg_s cn63xxp1;
struct cvmx_pcsx_rxx_states_reg_s cn66xx;
struct cvmx_pcsx_rxx_states_reg_s cn68xx;
struct cvmx_pcsx_rxx_states_reg_s cn68xxp1;
struct cvmx_pcsx_rxx_states_reg_s cnf71xx;
};
union cvmx_pcsx_rxx_sync_reg {
uint64_t u64;
struct cvmx_pcsx_rxx_sync_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63:62;
uint64_t sync:1;
uint64_t bit_lock:1;
#else
uint64_t bit_lock:1;
uint64_t sync:1;
uint64_t reserved_2_63:62;
#endif
} s;
struct cvmx_pcsx_rxx_sync_reg_s cn52xx;
struct cvmx_pcsx_rxx_sync_reg_s cn52xxp1;
struct cvmx_pcsx_rxx_sync_reg_s cn56xx;
struct cvmx_pcsx_rxx_sync_reg_s cn56xxp1;
struct cvmx_pcsx_rxx_sync_reg_s cn61xx;
struct cvmx_pcsx_rxx_sync_reg_s cn63xx;
struct cvmx_pcsx_rxx_sync_reg_s cn63xxp1;
struct cvmx_pcsx_rxx_sync_reg_s cn66xx;
struct cvmx_pcsx_rxx_sync_reg_s cn68xx;
struct cvmx_pcsx_rxx_sync_reg_s cn68xxp1;
struct cvmx_pcsx_rxx_sync_reg_s cnf71xx;
};
union cvmx_pcsx_sgmx_an_adv_reg {
uint64_t u64;
struct cvmx_pcsx_sgmx_an_adv_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t link:1;
uint64_t ack:1;
@ -314,16 +890,34 @@ union cvmx_pcsx_sgmx_an_adv_reg {
uint64_t speed:2;
uint64_t reserved_1_9:9;
uint64_t one:1;
#else
uint64_t one:1;
uint64_t reserved_1_9:9;
uint64_t speed:2;
uint64_t dup:1;
uint64_t reserved_13_13:1;
uint64_t ack:1;
uint64_t link:1;
uint64_t reserved_16_63:48;
#endif
} s;
struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xx;
struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xxp1;
struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xx;
struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xxp1;
struct cvmx_pcsx_sgmx_an_adv_reg_s cn61xx;
struct cvmx_pcsx_sgmx_an_adv_reg_s cn63xx;
struct cvmx_pcsx_sgmx_an_adv_reg_s cn63xxp1;
struct cvmx_pcsx_sgmx_an_adv_reg_s cn66xx;
struct cvmx_pcsx_sgmx_an_adv_reg_s cn68xx;
struct cvmx_pcsx_sgmx_an_adv_reg_s cn68xxp1;
struct cvmx_pcsx_sgmx_an_adv_reg_s cnf71xx;
};
union cvmx_pcsx_sgmx_lp_adv_reg {
uint64_t u64;
struct cvmx_pcsx_sgmx_lp_adv_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t link:1;
uint64_t reserved_13_14:2;
@ -331,40 +925,85 @@ union cvmx_pcsx_sgmx_lp_adv_reg {
uint64_t speed:2;
uint64_t reserved_1_9:9;
uint64_t one:1;
#else
uint64_t one:1;
uint64_t reserved_1_9:9;
uint64_t speed:2;
uint64_t dup:1;
uint64_t reserved_13_14:2;
uint64_t link:1;
uint64_t reserved_16_63:48;
#endif
} s;
struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xx;
struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xxp1;
struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xx;
struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xxp1;
struct cvmx_pcsx_sgmx_lp_adv_reg_s cn61xx;
struct cvmx_pcsx_sgmx_lp_adv_reg_s cn63xx;
struct cvmx_pcsx_sgmx_lp_adv_reg_s cn63xxp1;
struct cvmx_pcsx_sgmx_lp_adv_reg_s cn66xx;
struct cvmx_pcsx_sgmx_lp_adv_reg_s cn68xx;
struct cvmx_pcsx_sgmx_lp_adv_reg_s cn68xxp1;
struct cvmx_pcsx_sgmx_lp_adv_reg_s cnf71xx;
};
union cvmx_pcsx_txx_states_reg {
uint64_t u64;
struct cvmx_pcsx_txx_states_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_7_63:57;
uint64_t xmit:2;
uint64_t tx_bad:1;
uint64_t ord_st:4;
#else
uint64_t ord_st:4;
uint64_t tx_bad:1;
uint64_t xmit:2;
uint64_t reserved_7_63:57;
#endif
} s;
struct cvmx_pcsx_txx_states_reg_s cn52xx;
struct cvmx_pcsx_txx_states_reg_s cn52xxp1;
struct cvmx_pcsx_txx_states_reg_s cn56xx;
struct cvmx_pcsx_txx_states_reg_s cn56xxp1;
struct cvmx_pcsx_txx_states_reg_s cn61xx;
struct cvmx_pcsx_txx_states_reg_s cn63xx;
struct cvmx_pcsx_txx_states_reg_s cn63xxp1;
struct cvmx_pcsx_txx_states_reg_s cn66xx;
struct cvmx_pcsx_txx_states_reg_s cn68xx;
struct cvmx_pcsx_txx_states_reg_s cn68xxp1;
struct cvmx_pcsx_txx_states_reg_s cnf71xx;
};
union cvmx_pcsx_tx_rxx_polarity_reg {
uint64_t u64;
struct cvmx_pcsx_tx_rxx_polarity_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63:60;
uint64_t rxovrd:1;
uint64_t autorxpl:1;
uint64_t rxplrt:1;
uint64_t txplrt:1;
#else
uint64_t txplrt:1;
uint64_t rxplrt:1;
uint64_t autorxpl:1;
uint64_t rxovrd:1;
uint64_t reserved_4_63:60;
#endif
} s;
struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xx;
struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xxp1;
struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xx;
struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xxp1;
struct cvmx_pcsx_tx_rxx_polarity_reg_s cn61xx;
struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xx;
struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xxp1;
struct cvmx_pcsx_tx_rxx_polarity_reg_s cn66xx;
struct cvmx_pcsx_tx_rxx_polarity_reg_s cn68xx;
struct cvmx_pcsx_tx_rxx_polarity_reg_s cn68xxp1;
struct cvmx_pcsx_tx_rxx_polarity_reg_s cnf71xx;
};
#endif

574
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
View File

@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2008 Cavium Networks
* Copyright (c) 2003-2012 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@ -28,40 +28,250 @@
#ifndef __CVMX_PCSXX_DEFS_H__
#define __CVMX_PCSXX_DEFS_H__
#define CVMX_PCSXX_10GBX_STATUS_REG(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000828ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSXX_BIST_STATUS_REG(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000870ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSXX_BIT_LOCK_STATUS_REG(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000850ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSXX_CONTROL1_REG(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000800ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSXX_CONTROL2_REG(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000818ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSXX_INT_EN_REG(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000860ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSXX_INT_REG(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000858ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSXX_LOG_ANL_REG(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000868ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSXX_MISC_CTL_REG(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000848ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSXX_RX_SYNC_STATES_REG(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000838ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSXX_SPD_ABIL_REG(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000810ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSXX_STATUS1_REG(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000808ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSXX_STATUS2_REG(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000820ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSXX_TX_RX_POLARITY_REG(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000840ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSXX_TX_RX_STATES_REG(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000830ull + (((block_id) & 1) * 0x8000000ull))
static inline uint64_t CVMX_PCSXX_10GBX_STATUS_REG(unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull;
}
return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull;
}
static inline uint64_t CVMX_PCSXX_BIST_STATUS_REG(unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull;
}
return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull;
}
static inline uint64_t CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull;
}
return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull;
}
static inline uint64_t CVMX_PCSXX_CONTROL1_REG(unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull;
}
return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull;
}
static inline uint64_t CVMX_PCSXX_CONTROL2_REG(unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull;
}
return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull;
}
static inline uint64_t CVMX_PCSXX_INT_EN_REG(unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull;
}
return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull;
}
static inline uint64_t CVMX_PCSXX_INT_REG(unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull;
}
return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull;
}
static inline uint64_t CVMX_PCSXX_LOG_ANL_REG(unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull;
}
return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull;
}
static inline uint64_t CVMX_PCSXX_MISC_CTL_REG(unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull;
}
return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull;
}
static inline uint64_t CVMX_PCSXX_RX_SYNC_STATES_REG(unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull;
}
return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull;
}
static inline uint64_t CVMX_PCSXX_SPD_ABIL_REG(unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull;
}
return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull;
}
static inline uint64_t CVMX_PCSXX_STATUS1_REG(unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull;
}
return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull;
}
static inline uint64_t CVMX_PCSXX_STATUS2_REG(unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull;
}
return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull;
}
static inline uint64_t CVMX_PCSXX_TX_RX_POLARITY_REG(unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull;
}
return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull;
}
static inline uint64_t CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull;
}
return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull;
}
union cvmx_pcsxx_10gbx_status_reg {
uint64_t u64;
struct cvmx_pcsxx_10gbx_status_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_13_63:51;
uint64_t alignd:1;
uint64_t pattst:1;
@ -70,43 +280,85 @@ union cvmx_pcsxx_10gbx_status_reg {
uint64_t l2sync:1;
uint64_t l1sync:1;
uint64_t l0sync:1;
#else
uint64_t l0sync:1;
uint64_t l1sync:1;
uint64_t l2sync:1;
uint64_t l3sync:1;
uint64_t reserved_4_10:7;
uint64_t pattst:1;
uint64_t alignd:1;
uint64_t reserved_13_63:51;
#endif
} s;
struct cvmx_pcsxx_10gbx_status_reg_s cn52xx;
struct cvmx_pcsxx_10gbx_status_reg_s cn52xxp1;
struct cvmx_pcsxx_10gbx_status_reg_s cn56xx;
struct cvmx_pcsxx_10gbx_status_reg_s cn56xxp1;
struct cvmx_pcsxx_10gbx_status_reg_s cn61xx;
struct cvmx_pcsxx_10gbx_status_reg_s cn63xx;
struct cvmx_pcsxx_10gbx_status_reg_s cn63xxp1;
struct cvmx_pcsxx_10gbx_status_reg_s cn66xx;
struct cvmx_pcsxx_10gbx_status_reg_s cn68xx;
struct cvmx_pcsxx_10gbx_status_reg_s cn68xxp1;
};
union cvmx_pcsxx_bist_status_reg {
uint64_t u64;
struct cvmx_pcsxx_bist_status_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63:63;
uint64_t bist_status:1;
#else
uint64_t bist_status:1;
uint64_t reserved_1_63:63;
#endif
} s;
struct cvmx_pcsxx_bist_status_reg_s cn52xx;
struct cvmx_pcsxx_bist_status_reg_s cn52xxp1;
struct cvmx_pcsxx_bist_status_reg_s cn56xx;
struct cvmx_pcsxx_bist_status_reg_s cn56xxp1;
struct cvmx_pcsxx_bist_status_reg_s cn61xx;
struct cvmx_pcsxx_bist_status_reg_s cn63xx;
struct cvmx_pcsxx_bist_status_reg_s cn63xxp1;
struct cvmx_pcsxx_bist_status_reg_s cn66xx;
struct cvmx_pcsxx_bist_status_reg_s cn68xx;
struct cvmx_pcsxx_bist_status_reg_s cn68xxp1;
};
union cvmx_pcsxx_bit_lock_status_reg {
uint64_t u64;
struct cvmx_pcsxx_bit_lock_status_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63:60;
uint64_t bitlck3:1;
uint64_t bitlck2:1;
uint64_t bitlck1:1;
uint64_t bitlck0:1;
#else
uint64_t bitlck0:1;
uint64_t bitlck1:1;
uint64_t bitlck2:1;
uint64_t bitlck3:1;
uint64_t reserved_4_63:60;
#endif
} s;
struct cvmx_pcsxx_bit_lock_status_reg_s cn52xx;
struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1;
struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx;
struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1;
struct cvmx_pcsxx_bit_lock_status_reg_s cn61xx;
struct cvmx_pcsxx_bit_lock_status_reg_s cn63xx;
struct cvmx_pcsxx_bit_lock_status_reg_s cn63xxp1;
struct cvmx_pcsxx_bit_lock_status_reg_s cn66xx;
struct cvmx_pcsxx_bit_lock_status_reg_s cn68xx;
struct cvmx_pcsxx_bit_lock_status_reg_s cn68xxp1;
};
union cvmx_pcsxx_control1_reg {
uint64_t u64;
struct cvmx_pcsxx_control1_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t reset:1;
uint64_t loopbck1:1;
@ -117,28 +369,79 @@ union cvmx_pcsxx_control1_reg {
uint64_t spdsel0:1;
uint64_t spd:4;
uint64_t reserved_0_1:2;
#else
uint64_t reserved_0_1:2;
uint64_t spd:4;
uint64_t spdsel0:1;
uint64_t reserved_7_10:4;
uint64_t lo_pwr:1;
uint64_t reserved_12_12:1;
uint64_t spdsel1:1;
uint64_t loopbck1:1;
uint64_t reset:1;
uint64_t reserved_16_63:48;
#endif
} s;
struct cvmx_pcsxx_control1_reg_s cn52xx;
struct cvmx_pcsxx_control1_reg_s cn52xxp1;
struct cvmx_pcsxx_control1_reg_s cn56xx;
struct cvmx_pcsxx_control1_reg_s cn56xxp1;
struct cvmx_pcsxx_control1_reg_s cn61xx;
struct cvmx_pcsxx_control1_reg_s cn63xx;
struct cvmx_pcsxx_control1_reg_s cn63xxp1;
struct cvmx_pcsxx_control1_reg_s cn66xx;
struct cvmx_pcsxx_control1_reg_s cn68xx;
struct cvmx_pcsxx_control1_reg_s cn68xxp1;
};
union cvmx_pcsxx_control2_reg {
uint64_t u64;
struct cvmx_pcsxx_control2_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63:62;
uint64_t type:2;
#else
uint64_t type:2;
uint64_t reserved_2_63:62;
#endif
} s;
struct cvmx_pcsxx_control2_reg_s cn52xx;
struct cvmx_pcsxx_control2_reg_s cn52xxp1;
struct cvmx_pcsxx_control2_reg_s cn56xx;
struct cvmx_pcsxx_control2_reg_s cn56xxp1;
struct cvmx_pcsxx_control2_reg_s cn61xx;
struct cvmx_pcsxx_control2_reg_s cn63xx;
struct cvmx_pcsxx_control2_reg_s cn63xxp1;
struct cvmx_pcsxx_control2_reg_s cn66xx;
struct cvmx_pcsxx_control2_reg_s cn68xx;
struct cvmx_pcsxx_control2_reg_s cn68xxp1;
};
union cvmx_pcsxx_int_en_reg {
uint64_t u64;
struct cvmx_pcsxx_int_en_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_7_63:57;
uint64_t dbg_sync_en:1;
uint64_t algnlos_en:1;
uint64_t synlos_en:1;
uint64_t bitlckls_en:1;
uint64_t rxsynbad_en:1;
uint64_t rxbad_en:1;
uint64_t txflt_en:1;
#else
uint64_t txflt_en:1;
uint64_t rxbad_en:1;
uint64_t rxsynbad_en:1;
uint64_t bitlckls_en:1;
uint64_t synlos_en:1;
uint64_t algnlos_en:1;
uint64_t dbg_sync_en:1;
uint64_t reserved_7_63:57;
#endif
} s;
struct cvmx_pcsxx_int_en_reg_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_6_63:58;
uint64_t algnlos_en:1;
uint64_t synlos_en:1;
@ -146,16 +449,52 @@ union cvmx_pcsxx_int_en_reg {
uint64_t rxsynbad_en:1;
uint64_t rxbad_en:1;
uint64_t txflt_en:1;
} s;
struct cvmx_pcsxx_int_en_reg_s cn52xx;
struct cvmx_pcsxx_int_en_reg_s cn52xxp1;
struct cvmx_pcsxx_int_en_reg_s cn56xx;
struct cvmx_pcsxx_int_en_reg_s cn56xxp1;
#else
uint64_t txflt_en:1;
uint64_t rxbad_en:1;
uint64_t rxsynbad_en:1;
uint64_t bitlckls_en:1;
uint64_t synlos_en:1;
uint64_t algnlos_en:1;
uint64_t reserved_6_63:58;
#endif
} cn52xx;
struct cvmx_pcsxx_int_en_reg_cn52xx cn52xxp1;
struct cvmx_pcsxx_int_en_reg_cn52xx cn56xx;
struct cvmx_pcsxx_int_en_reg_cn52xx cn56xxp1;
struct cvmx_pcsxx_int_en_reg_s cn61xx;
struct cvmx_pcsxx_int_en_reg_s cn63xx;
struct cvmx_pcsxx_int_en_reg_s cn63xxp1;
struct cvmx_pcsxx_int_en_reg_s cn66xx;
struct cvmx_pcsxx_int_en_reg_s cn68xx;
struct cvmx_pcsxx_int_en_reg_s cn68xxp1;
};
union cvmx_pcsxx_int_reg {
uint64_t u64;
struct cvmx_pcsxx_int_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_7_63:57;
uint64_t dbg_sync:1;
uint64_t algnlos:1;
uint64_t synlos:1;
uint64_t bitlckls:1;
uint64_t rxsynbad:1;
uint64_t rxbad:1;
uint64_t txflt:1;
#else
uint64_t txflt:1;
uint64_t rxbad:1;
uint64_t rxsynbad:1;
uint64_t bitlckls:1;
uint64_t synlos:1;
uint64_t algnlos:1;
uint64_t dbg_sync:1;
uint64_t reserved_7_63:57;
#endif
} s;
struct cvmx_pcsxx_int_reg_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_6_63:58;
uint64_t algnlos:1;
uint64_t synlos:1;
@ -163,91 +502,176 @@ union cvmx_pcsxx_int_reg {
uint64_t rxsynbad:1;
uint64_t rxbad:1;
uint64_t txflt:1;
} s;
struct cvmx_pcsxx_int_reg_s cn52xx;
struct cvmx_pcsxx_int_reg_s cn52xxp1;
struct cvmx_pcsxx_int_reg_s cn56xx;
struct cvmx_pcsxx_int_reg_s cn56xxp1;
#else
uint64_t txflt:1;
uint64_t rxbad:1;
uint64_t rxsynbad:1;
uint64_t bitlckls:1;
uint64_t synlos:1;
uint64_t algnlos:1;
uint64_t reserved_6_63:58;
#endif
} cn52xx;
struct cvmx_pcsxx_int_reg_cn52xx cn52xxp1;
struct cvmx_pcsxx_int_reg_cn52xx cn56xx;
struct cvmx_pcsxx_int_reg_cn52xx cn56xxp1;
struct cvmx_pcsxx_int_reg_s cn61xx;
struct cvmx_pcsxx_int_reg_s cn63xx;
struct cvmx_pcsxx_int_reg_s cn63xxp1;
struct cvmx_pcsxx_int_reg_s cn66xx;
struct cvmx_pcsxx_int_reg_s cn68xx;
struct cvmx_pcsxx_int_reg_s cn68xxp1;
};
union cvmx_pcsxx_log_anl_reg {
uint64_t u64;
struct cvmx_pcsxx_log_anl_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_7_63:57;
uint64_t enc_mode:1;
uint64_t drop_ln:2;
uint64_t lafifovfl:1;
uint64_t la_en:1;
uint64_t pkt_sz:2;
#else
uint64_t pkt_sz:2;
uint64_t la_en:1;
uint64_t lafifovfl:1;
uint64_t drop_ln:2;
uint64_t enc_mode:1;
uint64_t reserved_7_63:57;
#endif
} s;
struct cvmx_pcsxx_log_anl_reg_s cn52xx;
struct cvmx_pcsxx_log_anl_reg_s cn52xxp1;
struct cvmx_pcsxx_log_anl_reg_s cn56xx;
struct cvmx_pcsxx_log_anl_reg_s cn56xxp1;
struct cvmx_pcsxx_log_anl_reg_s cn61xx;
struct cvmx_pcsxx_log_anl_reg_s cn63xx;
struct cvmx_pcsxx_log_anl_reg_s cn63xxp1;
struct cvmx_pcsxx_log_anl_reg_s cn66xx;
struct cvmx_pcsxx_log_anl_reg_s cn68xx;
struct cvmx_pcsxx_log_anl_reg_s cn68xxp1;
};
union cvmx_pcsxx_misc_ctl_reg {
uint64_t u64;
struct cvmx_pcsxx_misc_ctl_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63:60;
uint64_t tx_swap:1;
uint64_t rx_swap:1;
uint64_t xaui:1;
uint64_t gmxeno:1;
#else
uint64_t gmxeno:1;
uint64_t xaui:1;
uint64_t rx_swap:1;
uint64_t tx_swap:1;
uint64_t reserved_4_63:60;
#endif
} s;
struct cvmx_pcsxx_misc_ctl_reg_s cn52xx;
struct cvmx_pcsxx_misc_ctl_reg_s cn52xxp1;
struct cvmx_pcsxx_misc_ctl_reg_s cn56xx;
struct cvmx_pcsxx_misc_ctl_reg_s cn56xxp1;
struct cvmx_pcsxx_misc_ctl_reg_s cn61xx;
struct cvmx_pcsxx_misc_ctl_reg_s cn63xx;
struct cvmx_pcsxx_misc_ctl_reg_s cn63xxp1;
struct cvmx_pcsxx_misc_ctl_reg_s cn66xx;
struct cvmx_pcsxx_misc_ctl_reg_s cn68xx;
struct cvmx_pcsxx_misc_ctl_reg_s cn68xxp1;
};
union cvmx_pcsxx_rx_sync_states_reg {
uint64_t u64;
struct cvmx_pcsxx_rx_sync_states_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t sync3st:4;
uint64_t sync2st:4;
uint64_t sync1st:4;
uint64_t sync0st:4;
#else
uint64_t sync0st:4;
uint64_t sync1st:4;
uint64_t sync2st:4;
uint64_t sync3st:4;
uint64_t reserved_16_63:48;
#endif
} s;
struct cvmx_pcsxx_rx_sync_states_reg_s cn52xx;
struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1;
struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx;
struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1;
struct cvmx_pcsxx_rx_sync_states_reg_s cn61xx;
struct cvmx_pcsxx_rx_sync_states_reg_s cn63xx;
struct cvmx_pcsxx_rx_sync_states_reg_s cn63xxp1;
struct cvmx_pcsxx_rx_sync_states_reg_s cn66xx;
struct cvmx_pcsxx_rx_sync_states_reg_s cn68xx;
struct cvmx_pcsxx_rx_sync_states_reg_s cn68xxp1;
};
union cvmx_pcsxx_spd_abil_reg {
uint64_t u64;
struct cvmx_pcsxx_spd_abil_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63:62;
uint64_t tenpasst:1;
uint64_t tengb:1;
#else
uint64_t tengb:1;
uint64_t tenpasst:1;
uint64_t reserved_2_63:62;
#endif
} s;
struct cvmx_pcsxx_spd_abil_reg_s cn52xx;
struct cvmx_pcsxx_spd_abil_reg_s cn52xxp1;
struct cvmx_pcsxx_spd_abil_reg_s cn56xx;
struct cvmx_pcsxx_spd_abil_reg_s cn56xxp1;
struct cvmx_pcsxx_spd_abil_reg_s cn61xx;
struct cvmx_pcsxx_spd_abil_reg_s cn63xx;
struct cvmx_pcsxx_spd_abil_reg_s cn63xxp1;
struct cvmx_pcsxx_spd_abil_reg_s cn66xx;
struct cvmx_pcsxx_spd_abil_reg_s cn68xx;
struct cvmx_pcsxx_spd_abil_reg_s cn68xxp1;
};
union cvmx_pcsxx_status1_reg {
uint64_t u64;
struct cvmx_pcsxx_status1_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63:56;
uint64_t flt:1;
uint64_t reserved_3_6:4;
uint64_t rcv_lnk:1;
uint64_t lpable:1;
uint64_t reserved_0_0:1;
#else
uint64_t reserved_0_0:1;
uint64_t lpable:1;
uint64_t rcv_lnk:1;
uint64_t reserved_3_6:4;
uint64_t flt:1;
uint64_t reserved_8_63:56;
#endif
} s;
struct cvmx_pcsxx_status1_reg_s cn52xx;
struct cvmx_pcsxx_status1_reg_s cn52xxp1;
struct cvmx_pcsxx_status1_reg_s cn56xx;
struct cvmx_pcsxx_status1_reg_s cn56xxp1;
struct cvmx_pcsxx_status1_reg_s cn61xx;
struct cvmx_pcsxx_status1_reg_s cn63xx;
struct cvmx_pcsxx_status1_reg_s cn63xxp1;
struct cvmx_pcsxx_status1_reg_s cn66xx;
struct cvmx_pcsxx_status1_reg_s cn68xx;
struct cvmx_pcsxx_status1_reg_s cn68xxp1;
};
union cvmx_pcsxx_status2_reg {
uint64_t u64;
struct cvmx_pcsxx_status2_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t dev:2;
uint64_t reserved_12_13:2;
@ -257,35 +681,73 @@ union cvmx_pcsxx_status2_reg {
uint64_t tengb_w:1;
uint64_t tengb_x:1;
uint64_t tengb_r:1;
#else
uint64_t tengb_r:1;
uint64_t tengb_x:1;
uint64_t tengb_w:1;
uint64_t reserved_3_9:7;
uint64_t rcvflt:1;
uint64_t xmtflt:1;
uint64_t reserved_12_13:2;
uint64_t dev:2;
uint64_t reserved_16_63:48;
#endif
} s;
struct cvmx_pcsxx_status2_reg_s cn52xx;
struct cvmx_pcsxx_status2_reg_s cn52xxp1;
struct cvmx_pcsxx_status2_reg_s cn56xx;
struct cvmx_pcsxx_status2_reg_s cn56xxp1;
struct cvmx_pcsxx_status2_reg_s cn61xx;
struct cvmx_pcsxx_status2_reg_s cn63xx;
struct cvmx_pcsxx_status2_reg_s cn63xxp1;
struct cvmx_pcsxx_status2_reg_s cn66xx;
struct cvmx_pcsxx_status2_reg_s cn68xx;
struct cvmx_pcsxx_status2_reg_s cn68xxp1;
};
union cvmx_pcsxx_tx_rx_polarity_reg {
uint64_t u64;
struct cvmx_pcsxx_tx_rx_polarity_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_10_63:54;
uint64_t xor_rxplrt:4;
uint64_t xor_txplrt:4;
uint64_t rxplrt:1;
uint64_t txplrt:1;
#else
uint64_t txplrt:1;
uint64_t rxplrt:1;
uint64_t xor_txplrt:4;
uint64_t xor_rxplrt:4;
uint64_t reserved_10_63:54;
#endif
} s;
struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx;
struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63:62;
uint64_t rxplrt:1;
uint64_t txplrt:1;
#else
uint64_t txplrt:1;
uint64_t rxplrt:1;
uint64_t reserved_2_63:62;
#endif
} cn52xxp1;
struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx;
struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1;
struct cvmx_pcsxx_tx_rx_polarity_reg_s cn61xx;
struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xx;
struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xxp1;
struct cvmx_pcsxx_tx_rx_polarity_reg_s cn66xx;
struct cvmx_pcsxx_tx_rx_polarity_reg_s cn68xx;
struct cvmx_pcsxx_tx_rx_polarity_reg_s cn68xxp1;
};
union cvmx_pcsxx_tx_rx_states_reg {
uint64_t u64;
struct cvmx_pcsxx_tx_rx_states_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_14_63:50;
uint64_t term_err:1;
uint64_t syn3bad:1;
@ -296,9 +758,22 @@ union cvmx_pcsxx_tx_rx_states_reg {
uint64_t algn_st:3;
uint64_t rx_st:2;
uint64_t tx_st:3;
#else
uint64_t tx_st:3;
uint64_t rx_st:2;
uint64_t algn_st:3;
uint64_t rxbad:1;
uint64_t syn0bad:1;
uint64_t syn1bad:1;
uint64_t syn2bad:1;
uint64_t syn3bad:1;
uint64_t term_err:1;
uint64_t reserved_14_63:50;
#endif
} s;
struct cvmx_pcsxx_tx_rx_states_reg_s cn52xx;
struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_13_63:51;
uint64_t syn3bad:1;
uint64_t syn2bad:1;
@ -308,9 +783,26 @@ union cvmx_pcsxx_tx_rx_states_reg {
uint64_t algn_st:3;
uint64_t rx_st:2;
uint64_t tx_st:3;
#else
uint64_t tx_st:3;
uint64_t rx_st:2;
uint64_t algn_st:3;
uint64_t rxbad:1;
uint64_t syn0bad:1;
uint64_t syn1bad:1;
uint64_t syn2bad:1;
uint64_t syn3bad:1;
uint64_t reserved_13_63:51;
#endif
} cn52xxp1;
struct cvmx_pcsxx_tx_rx_states_reg_s cn56xx;
struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1;
struct cvmx_pcsxx_tx_rx_states_reg_s cn61xx;
struct cvmx_pcsxx_tx_rx_states_reg_s cn63xx;
struct cvmx_pcsxx_tx_rx_states_reg_s cn63xxp1;
struct cvmx_pcsxx_tx_rx_states_reg_s cn66xx;
struct cvmx_pcsxx_tx_rx_states_reg_s cn68xx;
struct cvmx_pcsxx_tx_rx_states_reg_s cn68xxp1;
};
#endif

288
arch/mips/include/asm/octeon/cvmx-pemx-defs.h
View File

@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2011 Cavium Networks
* Copyright (c) 2003-2012 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@ -54,11 +54,19 @@
union cvmx_pemx_bar1_indexx {
uint64_t u64;
struct cvmx_pemx_bar1_indexx_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63:44;
uint64_t addr_idx:16;
uint64_t ca:1;
uint64_t end_swp:2;
uint64_t addr_v:1;
#else
uint64_t addr_v:1;
uint64_t end_swp:2;
uint64_t ca:1;
uint64_t addr_idx:16;
uint64_t reserved_20_63:44;
#endif
} s;
struct cvmx_pemx_bar1_indexx_s cn61xx;
struct cvmx_pemx_bar1_indexx_s cn63xx;
@ -66,29 +74,45 @@ union cvmx_pemx_bar1_indexx {
struct cvmx_pemx_bar1_indexx_s cn66xx;
struct cvmx_pemx_bar1_indexx_s cn68xx;
struct cvmx_pemx_bar1_indexx_s cn68xxp1;
struct cvmx_pemx_bar1_indexx_s cnf71xx;
};
union cvmx_pemx_bar2_mask {
uint64_t u64;
struct cvmx_pemx_bar2_mask_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_38_63:26;
uint64_t mask:35;
uint64_t reserved_0_2:3;
#else
uint64_t reserved_0_2:3;
uint64_t mask:35;
uint64_t reserved_38_63:26;
#endif
} s;
struct cvmx_pemx_bar2_mask_s cn61xx;
struct cvmx_pemx_bar2_mask_s cn66xx;
struct cvmx_pemx_bar2_mask_s cn68xx;
struct cvmx_pemx_bar2_mask_s cn68xxp1;
struct cvmx_pemx_bar2_mask_s cnf71xx;
};
union cvmx_pemx_bar_ctl {
uint64_t u64;
struct cvmx_pemx_bar_ctl_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_7_63:57;
uint64_t bar1_siz:3;
uint64_t bar2_enb:1;
uint64_t bar2_esx:2;
uint64_t bar2_cax:1;
#else
uint64_t bar2_cax:1;
uint64_t bar2_esx:2;
uint64_t bar2_enb:1;
uint64_t bar1_siz:3;
uint64_t reserved_7_63:57;
#endif
} s;
struct cvmx_pemx_bar_ctl_s cn61xx;
struct cvmx_pemx_bar_ctl_s cn63xx;
@ -96,11 +120,13 @@ union cvmx_pemx_bar_ctl {
struct cvmx_pemx_bar_ctl_s cn66xx;
struct cvmx_pemx_bar_ctl_s cn68xx;
struct cvmx_pemx_bar_ctl_s cn68xxp1;
struct cvmx_pemx_bar_ctl_s cnf71xx;
};
union cvmx_pemx_bist_status {
uint64_t u64;
struct cvmx_pemx_bist_status_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63:56;
uint64_t retry:1;
uint64_t rqdata0:1;
@ -110,6 +136,17 @@ union cvmx_pemx_bist_status {
uint64_t rqhdr1:1;
uint64_t rqhdr0:1;
uint64_t sot:1;
#else
uint64_t sot:1;
uint64_t rqhdr0:1;
uint64_t rqhdr1:1;
uint64_t rqdata3:1;
uint64_t rqdata2:1;
uint64_t rqdata1:1;
uint64_t rqdata0:1;
uint64_t retry:1;
uint64_t reserved_8_63:56;
#endif
} s;
struct cvmx_pemx_bist_status_s cn61xx;
struct cvmx_pemx_bist_status_s cn63xx;
@ -117,11 +154,13 @@ union cvmx_pemx_bist_status {
struct cvmx_pemx_bist_status_s cn66xx;
struct cvmx_pemx_bist_status_s cn68xx;
struct cvmx_pemx_bist_status_s cn68xxp1;
struct cvmx_pemx_bist_status_s cnf71xx;
};
union cvmx_pemx_bist_status2 {
uint64_t u64;
struct cvmx_pemx_bist_status2_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_10_63:54;
uint64_t e2p_cpl:1;
uint64_t e2p_n:1;
@ -133,6 +172,19 @@ union cvmx_pemx_bist_status2 {
uint64_t pef_tcf1:1;
uint64_t pef_tc0:1;
uint64_t ppf:1;
#else
uint64_t ppf:1;
uint64_t pef_tc0:1;
uint64_t pef_tcf1:1;
uint64_t pef_tnf:1;
uint64_t pef_tpf0:1;
uint64_t pef_tpf1:1;
uint64_t peai_p2e:1;
uint64_t e2p_p:1;
uint64_t e2p_n:1;
uint64_t e2p_cpl:1;
uint64_t reserved_10_63:54;
#endif
} s;
struct cvmx_pemx_bist_status2_s cn61xx;
struct cvmx_pemx_bist_status2_s cn63xx;
@ -140,13 +192,19 @@ union cvmx_pemx_bist_status2 {
struct cvmx_pemx_bist_status2_s cn66xx;
struct cvmx_pemx_bist_status2_s cn68xx;
struct cvmx_pemx_bist_status2_s cn68xxp1;
struct cvmx_pemx_bist_status2_s cnf71xx;
};
union cvmx_pemx_cfg_rd {
uint64_t u64;
struct cvmx_pemx_cfg_rd_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t data:32;
uint64_t addr:32;
#else
uint64_t addr:32;
uint64_t data:32;
#endif
} s;
struct cvmx_pemx_cfg_rd_s cn61xx;
struct cvmx_pemx_cfg_rd_s cn63xx;
@ -154,13 +212,19 @@ union cvmx_pemx_cfg_rd {
struct cvmx_pemx_cfg_rd_s cn66xx;
struct cvmx_pemx_cfg_rd_s cn68xx;
struct cvmx_pemx_cfg_rd_s cn68xxp1;
struct cvmx_pemx_cfg_rd_s cnf71xx;
};
union cvmx_pemx_cfg_wr {
uint64_t u64;
struct cvmx_pemx_cfg_wr_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t data:32;
uint64_t addr:32;
#else
uint64_t addr:32;
uint64_t data:32;
#endif
} s;
struct cvmx_pemx_cfg_wr_s cn61xx;
struct cvmx_pemx_cfg_wr_s cn63xx;
@ -168,13 +232,19 @@ union cvmx_pemx_cfg_wr {
struct cvmx_pemx_cfg_wr_s cn66xx;
struct cvmx_pemx_cfg_wr_s cn68xx;
struct cvmx_pemx_cfg_wr_s cn68xxp1;
struct cvmx_pemx_cfg_wr_s cnf71xx;
};
union cvmx_pemx_cpl_lut_valid {
uint64_t u64;
struct cvmx_pemx_cpl_lut_valid_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
uint64_t tag:32;
#else
uint64_t tag:32;
uint64_t reserved_32_63:32;
#endif
} s;
struct cvmx_pemx_cpl_lut_valid_s cn61xx;
struct cvmx_pemx_cpl_lut_valid_s cn63xx;
@ -182,11 +252,13 @@ union cvmx_pemx_cpl_lut_valid {
struct cvmx_pemx_cpl_lut_valid_s cn66xx;
struct cvmx_pemx_cpl_lut_valid_s cn68xx;
struct cvmx_pemx_cpl_lut_valid_s cn68xxp1;
struct cvmx_pemx_cpl_lut_valid_s cnf71xx;
};
union cvmx_pemx_ctl_status {
uint64_t u64;
struct cvmx_pemx_ctl_status_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_48_63:16;
uint64_t auto_sd:1;
uint64_t dnum:5;
@ -205,6 +277,26 @@ union cvmx_pemx_ctl_status {
uint64_t fast_lm:1;
uint64_t inv_ecrc:1;
uint64_t inv_lcrc:1;
#else
uint64_t inv_lcrc:1;
uint64_t inv_ecrc:1;
uint64_t fast_lm:1;
uint64_t ro_ctlp:1;
uint64_t lnk_enb:1;
uint64_t dly_one:1;
uint64_t nf_ecrc:1;
uint64_t reserved_7_8:2;
uint64_t ob_p_cmd:1;
uint64_t pm_xpme:1;
uint64_t pm_xtoff:1;
uint64_t reserved_12_15:4;
uint64_t cfg_rtry:16;
uint64_t reserved_32_33:2;
uint64_t pbus:8;
uint64_t dnum:5;
uint64_t auto_sd:1;
uint64_t reserved_48_63:16;
#endif
} s;
struct cvmx_pemx_ctl_status_s cn61xx;
struct cvmx_pemx_ctl_status_s cn63xx;
@ -212,11 +304,13 @@ union cvmx_pemx_ctl_status {
struct cvmx_pemx_ctl_status_s cn66xx;
struct cvmx_pemx_ctl_status_s cn68xx;
struct cvmx_pemx_ctl_status_s cn68xxp1;
struct cvmx_pemx_ctl_status_s cnf71xx;
};
union cvmx_pemx_dbg_info {
uint64_t u64;
struct cvmx_pemx_dbg_info_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_31_63:33;
uint64_t ecrc_e:1;
uint64_t rawwpp:1;
@ -249,6 +343,40 @@ union cvmx_pemx_dbg_info {
uint64_t rtlplle:1;
uint64_t rtlpmal:1;
uint64_t spoison:1;
#else
uint64_t spoison:1;
uint64_t rtlpmal:1;
uint64_t rtlplle:1;
uint64_t recrce:1;
uint64_t rpoison:1;
uint64_t rcemrc:1;
uint64_t rnfemrc:1;
uint64_t rfemrc:1;
uint64_t rpmerc:1;
uint64_t rptamrc:1;
uint64_t rumep:1;
uint64_t rvdm:1;
uint64_t acto:1;
uint64_t rte:1;
uint64_t mre:1;
uint64_t rdwdle:1;
uint64_t rtwdle:1;
uint64_t dpeoosd:1;
uint64_t fcpvwt:1;
uint64_t rpe:1;
uint64_t fcuv:1;
uint64_t rqo:1;
uint64_t rauc:1;
uint64_t racur:1;
uint64_t racca:1;
uint64_t caar:1;
uint64_t rarwdns:1;
uint64_t ramtlp:1;
uint64_t racpp:1;
uint64_t rawwpp:1;
uint64_t ecrc_e:1;
uint64_t reserved_31_63:33;
#endif
} s;
struct cvmx_pemx_dbg_info_s cn61xx;
struct cvmx_pemx_dbg_info_s cn63xx;
@ -256,11 +384,13 @@ union cvmx_pemx_dbg_info {
struct cvmx_pemx_dbg_info_s cn66xx;
struct cvmx_pemx_dbg_info_s cn68xx;
struct cvmx_pemx_dbg_info_s cn68xxp1;
struct cvmx_pemx_dbg_info_s cnf71xx;
};
union cvmx_pemx_dbg_info_en {
uint64_t u64;
struct cvmx_pemx_dbg_info_en_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_31_63:33;
uint64_t ecrc_e:1;
uint64_t rawwpp:1;
@ -293,6 +423,40 @@ union cvmx_pemx_dbg_info_en {
uint64_t rtlplle:1;
uint64_t rtlpmal:1;
uint64_t spoison:1;
#else
uint64_t spoison:1;
uint64_t rtlpmal:1;
uint64_t rtlplle:1;
uint64_t recrce:1;
uint64_t rpoison:1;
uint64_t rcemrc:1;
uint64_t rnfemrc:1;
uint64_t rfemrc:1;
uint64_t rpmerc:1;
uint64_t rptamrc:1;
uint64_t rumep:1;
uint64_t rvdm:1;
uint64_t acto:1;
uint64_t rte:1;
uint64_t mre:1;
uint64_t rdwdle:1;
uint64_t rtwdle:1;
uint64_t dpeoosd:1;
uint64_t fcpvwt:1;
uint64_t rpe:1;
uint64_t fcuv:1;
uint64_t rqo:1;
uint64_t rauc:1;
uint64_t racur:1;
uint64_t racca:1;
uint64_t caar:1;
uint64_t rarwdns:1;
uint64_t ramtlp:1;
uint64_t racpp:1;
uint64_t rawwpp:1;
uint64_t ecrc_e:1;
uint64_t reserved_31_63:33;
#endif
} s;
struct cvmx_pemx_dbg_info_en_s cn61xx;
struct cvmx_pemx_dbg_info_en_s cn63xx;
@ -300,16 +464,25 @@ union cvmx_pemx_dbg_info_en {
struct cvmx_pemx_dbg_info_en_s cn66xx;
struct cvmx_pemx_dbg_info_en_s cn68xx;
struct cvmx_pemx_dbg_info_en_s cn68xxp1;
struct cvmx_pemx_dbg_info_en_s cnf71xx;
};
union cvmx_pemx_diag_status {
uint64_t u64;
struct cvmx_pemx_diag_status_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63:60;
uint64_t pm_dst:1;
uint64_t pm_stat:1;
uint64_t pm_en:1;
uint64_t aux_en:1;
#else
uint64_t aux_en:1;
uint64_t pm_en:1;
uint64_t pm_stat:1;
uint64_t pm_dst:1;
uint64_t reserved_4_63:60;
#endif
} s;
struct cvmx_pemx_diag_status_s cn61xx;
struct cvmx_pemx_diag_status_s cn63xx;
@ -317,22 +490,30 @@ union cvmx_pemx_diag_status {
struct cvmx_pemx_diag_status_s cn66xx;
struct cvmx_pemx_diag_status_s cn68xx;
struct cvmx_pemx_diag_status_s cn68xxp1;
struct cvmx_pemx_diag_status_s cnf71xx;
};
union cvmx_pemx_inb_read_credits {
uint64_t u64;
struct cvmx_pemx_inb_read_credits_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_6_63:58;
uint64_t num:6;
#else
uint64_t num:6;
uint64_t reserved_6_63:58;
#endif
} s;
struct cvmx_pemx_inb_read_credits_s cn61xx;
struct cvmx_pemx_inb_read_credits_s cn66xx;
struct cvmx_pemx_inb_read_credits_s cn68xx;
struct cvmx_pemx_inb_read_credits_s cnf71xx;
};
union cvmx_pemx_int_enb {
uint64_t u64;
struct cvmx_pemx_int_enb_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_14_63:50;
uint64_t crs_dr:1;
uint64_t crs_er:1;
@ -348,6 +529,23 @@ union cvmx_pemx_int_enb {
uint64_t pmei:1;
uint64_t se:1;
uint64_t aeri:1;
#else
uint64_t aeri:1;
uint64_t se:1;
uint64_t pmei:1;
uint64_t pmem:1;
uint64_t up_b1:1;
uint64_t up_b2:1;
uint64_t up_bx:1;
uint64_t un_b1:1;
uint64_t un_b2:1;
uint64_t un_bx:1;
uint64_t exc:1;
uint64_t rdlk:1;
uint64_t crs_er:1;
uint64_t crs_dr:1;
uint64_t reserved_14_63:50;
#endif
} s;
struct cvmx_pemx_int_enb_s cn61xx;
struct cvmx_pemx_int_enb_s cn63xx;
@ -355,11 +553,13 @@ union cvmx_pemx_int_enb {
struct cvmx_pemx_int_enb_s cn66xx;
struct cvmx_pemx_int_enb_s cn68xx;
struct cvmx_pemx_int_enb_s cn68xxp1;
struct cvmx_pemx_int_enb_s cnf71xx;
};
union cvmx_pemx_int_enb_int {
uint64_t u64;
struct cvmx_pemx_int_enb_int_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_14_63:50;
uint64_t crs_dr:1;
uint64_t crs_er:1;
@ -375,6 +575,23 @@ union cvmx_pemx_int_enb_int {
uint64_t pmei:1;
uint64_t se:1;
uint64_t aeri:1;
#else
uint64_t aeri:1;
uint64_t se:1;
uint64_t pmei:1;
uint64_t pmem:1;
uint64_t up_b1:1;
uint64_t up_b2:1;
uint64_t up_bx:1;
uint64_t un_b1:1;
uint64_t un_b2:1;
uint64_t un_bx:1;
uint64_t exc:1;
uint64_t rdlk:1;
uint64_t crs_er:1;
uint64_t crs_dr:1;
uint64_t reserved_14_63:50;
#endif
} s;
struct cvmx_pemx_int_enb_int_s cn61xx;
struct cvmx_pemx_int_enb_int_s cn63xx;
@ -382,11 +599,13 @@ union cvmx_pemx_int_enb_int {
struct cvmx_pemx_int_enb_int_s cn66xx;
struct cvmx_pemx_int_enb_int_s cn68xx;
struct cvmx_pemx_int_enb_int_s cn68xxp1;
struct cvmx_pemx_int_enb_int_s cnf71xx;
};
union cvmx_pemx_int_sum {
uint64_t u64;
struct cvmx_pemx_int_sum_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_14_63:50;
uint64_t crs_dr:1;
uint64_t crs_er:1;
@ -402,6 +621,23 @@ union cvmx_pemx_int_sum {
uint64_t pmei:1;
uint64_t se:1;
uint64_t aeri:1;
#else
uint64_t aeri:1;
uint64_t se:1;
uint64_t pmei:1;
uint64_t pmem:1;
uint64_t up_b1:1;
uint64_t up_b2:1;
uint64_t up_bx:1;
uint64_t un_b1:1;
uint64_t un_b2:1;
uint64_t un_bx:1;
uint64_t exc:1;
uint64_t rdlk:1;
uint64_t crs_er:1;
uint64_t crs_dr:1;
uint64_t reserved_14_63:50;
#endif
} s;
struct cvmx_pemx_int_sum_s cn61xx;
struct cvmx_pemx_int_sum_s cn63xx;
@ -409,13 +645,19 @@ union cvmx_pemx_int_sum {
struct cvmx_pemx_int_sum_s cn66xx;
struct cvmx_pemx_int_sum_s cn68xx;
struct cvmx_pemx_int_sum_s cn68xxp1;
struct cvmx_pemx_int_sum_s cnf71xx;
};
union cvmx_pemx_p2n_bar0_start {
uint64_t u64;
struct cvmx_pemx_p2n_bar0_start_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t addr:50;
uint64_t reserved_0_13:14;
#else
uint64_t reserved_0_13:14;
uint64_t addr:50;
#endif
} s;
struct cvmx_pemx_p2n_bar0_start_s cn61xx;
struct cvmx_pemx_p2n_bar0_start_s cn63xx;
@ -423,13 +665,19 @@ union cvmx_pemx_p2n_bar0_start {
struct cvmx_pemx_p2n_bar0_start_s cn66xx;
struct cvmx_pemx_p2n_bar0_start_s cn68xx;
struct cvmx_pemx_p2n_bar0_start_s cn68xxp1;
struct cvmx_pemx_p2n_bar0_start_s cnf71xx;
};
union cvmx_pemx_p2n_bar1_start {
uint64_t u64;
struct cvmx_pemx_p2n_bar1_start_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t addr:38;
uint64_t reserved_0_25:26;
#else
uint64_t reserved_0_25:26;
uint64_t addr:38;
#endif
} s;
struct cvmx_pemx_p2n_bar1_start_s cn61xx;
struct cvmx_pemx_p2n_bar1_start_s cn63xx;
@ -437,13 +685,19 @@ union cvmx_pemx_p2n_bar1_start {
struct cvmx_pemx_p2n_bar1_start_s cn66xx;
struct cvmx_pemx_p2n_bar1_start_s cn68xx;
struct cvmx_pemx_p2n_bar1_start_s cn68xxp1;
struct cvmx_pemx_p2n_bar1_start_s cnf71xx;
};
union cvmx_pemx_p2n_bar2_start {
uint64_t u64;
struct cvmx_pemx_p2n_bar2_start_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t addr:23;
uint64_t reserved_0_40:41;
#else
uint64_t reserved_0_40:41;
uint64_t addr:23;
#endif
} s;
struct cvmx_pemx_p2n_bar2_start_s cn61xx;
struct cvmx_pemx_p2n_bar2_start_s cn63xx;
@ -451,13 +705,19 @@ union cvmx_pemx_p2n_bar2_start {
struct cvmx_pemx_p2n_bar2_start_s cn66xx;
struct cvmx_pemx_p2n_bar2_start_s cn68xx;
struct cvmx_pemx_p2n_bar2_start_s cn68xxp1;
struct cvmx_pemx_p2n_bar2_start_s cnf71xx;
};
union cvmx_pemx_p2p_barx_end {
uint64_t u64;
struct cvmx_pemx_p2p_barx_end_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t addr:52;
uint64_t reserved_0_11:12;
#else
uint64_t reserved_0_11:12;
uint64_t addr:52;
#endif
} s;
struct cvmx_pemx_p2p_barx_end_s cn63xx;
struct cvmx_pemx_p2p_barx_end_s cn63xxp1;
@ -469,8 +729,13 @@ union cvmx_pemx_p2p_barx_end {
union cvmx_pemx_p2p_barx_start {
uint64_t u64;
struct cvmx_pemx_p2p_barx_start_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t addr:52;
uint64_t reserved_0_11:12;
#else
uint64_t reserved_0_11:12;
uint64_t addr:52;
#endif
} s;
struct cvmx_pemx_p2p_barx_start_s cn63xx;
struct cvmx_pemx_p2p_barx_start_s cn63xxp1;
@ -482,6 +747,7 @@ union cvmx_pemx_p2p_barx_start {
union cvmx_pemx_tlp_credits {
uint64_t u64;
struct cvmx_pemx_tlp_credits_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_56_63:8;
uint64_t peai_ppf:8;
uint64_t pem_cpl:8;
@ -490,20 +756,40 @@ union cvmx_pemx_tlp_credits {
uint64_t sli_cpl:8;
uint64_t sli_np:8;
uint64_t sli_p:8;
#else
uint64_t sli_p:8;
uint64_t sli_np:8;
uint64_t sli_cpl:8;
uint64_t pem_p:8;
uint64_t pem_np:8;
uint64_t pem_cpl:8;
uint64_t peai_ppf:8;
uint64_t reserved_56_63:8;
#endif
} s;
struct cvmx_pemx_tlp_credits_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_56_63:8;
uint64_t peai_ppf:8;
uint64_t reserved_24_47:24;
uint64_t sli_cpl:8;
uint64_t sli_np:8;
uint64_t sli_p:8;
#else
uint64_t sli_p:8;
uint64_t sli_np:8;
uint64_t sli_cpl:8;
uint64_t reserved_24_47:24;
uint64_t peai_ppf:8;
uint64_t reserved_56_63:8;
#endif
} cn61xx;
struct cvmx_pemx_tlp_credits_s cn63xx;
struct cvmx_pemx_tlp_credits_s cn63xxp1;
struct cvmx_pemx_tlp_credits_s cn66xx;
struct cvmx_pemx_tlp_credits_s cn68xx;
struct cvmx_pemx_tlp_credits_s cn68xxp1;
struct cvmx_pemx_tlp_credits_cn61xx cnf71xx;
};
#endif

246
arch/mips/include/asm/octeon/cvmx-pescx-defs.h
View File

@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2010 Cavium Networks
* Copyright (c) 2003-2012 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@ -48,6 +48,7 @@
union cvmx_pescx_bist_status {
uint64_t u64;
struct cvmx_pescx_bist_status_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_13_63:51;
uint64_t rqdata5:1;
uint64_t ctlp_or:1;
@ -62,9 +63,26 @@ union cvmx_pescx_bist_status {
uint64_t rqhdr1:1;
uint64_t rqhdr0:1;
uint64_t sot:1;
#else
uint64_t sot:1;
uint64_t rqhdr0:1;
uint64_t rqhdr1:1;
uint64_t rqdata4:1;
uint64_t rqdata3:1;
uint64_t rqdata2:1;
uint64_t rqdata1:1;
uint64_t rqdata0:1;
uint64_t retry:1;
uint64_t ptlp_or:1;
uint64_t ntlp_or:1;
uint64_t ctlp_or:1;
uint64_t rqdata5:1;
uint64_t reserved_13_63:51;
#endif
} s;
struct cvmx_pescx_bist_status_s cn52xx;
struct cvmx_pescx_bist_status_cn52xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63:52;
uint64_t ctlp_or:1;
uint64_t ntlp_or:1;
@ -78,6 +96,21 @@ union cvmx_pescx_bist_status {
uint64_t rqhdr1:1;
uint64_t rqhdr0:1;
uint64_t sot:1;
#else
uint64_t sot:1;
uint64_t rqhdr0:1;
uint64_t rqhdr1:1;
uint64_t rqdata4:1;
uint64_t rqdata3:1;
uint64_t rqdata2:1;
uint64_t rqdata1:1;
uint64_t rqdata0:1;
uint64_t retry:1;
uint64_t ptlp_or:1;
uint64_t ntlp_or:1;
uint64_t ctlp_or:1;
uint64_t reserved_12_63:52;
#endif
} cn52xxp1;
struct cvmx_pescx_bist_status_s cn56xx;
struct cvmx_pescx_bist_status_cn52xxp1 cn56xxp1;
@ -86,6 +119,7 @@ union cvmx_pescx_bist_status {
union cvmx_pescx_bist_status2 {
uint64_t u64;
struct cvmx_pescx_bist_status2_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_14_63:50;
uint64_t cto_p2e:1;
uint64_t e2p_cpl:1;
@ -101,6 +135,23 @@ union cvmx_pescx_bist_status2 {
uint64_t pef_tcf1:1;
uint64_t pef_tc0:1;
uint64_t ppf:1;
#else
uint64_t ppf:1;
uint64_t pef_tc0:1;
uint64_t pef_tcf1:1;
uint64_t pef_tnf:1;
uint64_t pef_tpf0:1;
uint64_t pef_tpf1:1;
uint64_t rsl_p2e:1;
uint64_t peai_p2e:1;
uint64_t dbg_p2e:1;
uint64_t e2p_rsl:1;
uint64_t e2p_p:1;
uint64_t e2p_n:1;
uint64_t e2p_cpl:1;
uint64_t cto_p2e:1;
uint64_t reserved_14_63:50;
#endif
} s;
struct cvmx_pescx_bist_status2_s cn52xx;
struct cvmx_pescx_bist_status2_s cn52xxp1;
@ -111,8 +162,13 @@ union cvmx_pescx_bist_status2 {
union cvmx_pescx_cfg_rd {
uint64_t u64;
struct cvmx_pescx_cfg_rd_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t data:32;
uint64_t addr:32;
#else
uint64_t addr:32;
uint64_t data:32;
#endif
} s;
struct cvmx_pescx_cfg_rd_s cn52xx;
struct cvmx_pescx_cfg_rd_s cn52xxp1;
@ -123,8 +179,13 @@ union cvmx_pescx_cfg_rd {
union cvmx_pescx_cfg_wr {
uint64_t u64;
struct cvmx_pescx_cfg_wr_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t data:32;
uint64_t addr:32;
#else
uint64_t addr:32;
uint64_t data:32;
#endif
} s;
struct cvmx_pescx_cfg_wr_s cn52xx;
struct cvmx_pescx_cfg_wr_s cn52xxp1;
@ -135,8 +196,13 @@ union cvmx_pescx_cfg_wr {
union cvmx_pescx_cpl_lut_valid {
uint64_t u64;
struct cvmx_pescx_cpl_lut_valid_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
uint64_t tag:32;
#else
uint64_t tag:32;
uint64_t reserved_32_63:32;
#endif
} s;
struct cvmx_pescx_cpl_lut_valid_s cn52xx;
struct cvmx_pescx_cpl_lut_valid_s cn52xxp1;
@ -147,6 +213,7 @@ union cvmx_pescx_cpl_lut_valid {
union cvmx_pescx_ctl_status {
uint64_t u64;
struct cvmx_pescx_ctl_status_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_28_63:36;
uint64_t dnum:5;
uint64_t pbus:8;
@ -163,10 +230,29 @@ union cvmx_pescx_ctl_status {
uint64_t reserved_2_2:1;
uint64_t inv_ecrc:1;
uint64_t inv_lcrc:1;
#else
uint64_t inv_lcrc:1;
uint64_t inv_ecrc:1;
uint64_t reserved_2_2:1;
uint64_t ro_ctlp:1;
uint64_t lnk_enb:1;
uint64_t dly_one:1;
uint64_t nf_ecrc:1;
uint64_t reserved_7_8:2;
uint64_t ob_p_cmd:1;
uint64_t pm_xpme:1;
uint64_t pm_xtoff:1;
uint64_t lane_swp:1;
uint64_t qlm_cfg:2;
uint64_t pbus:8;
uint64_t dnum:5;
uint64_t reserved_28_63:36;
#endif
} s;
struct cvmx_pescx_ctl_status_s cn52xx;
struct cvmx_pescx_ctl_status_s cn52xxp1;
struct cvmx_pescx_ctl_status_cn56xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_28_63:36;
uint64_t dnum:5;
uint64_t pbus:8;
@ -183,6 +269,24 @@ union cvmx_pescx_ctl_status {
uint64_t reserved_2_2:1;
uint64_t inv_ecrc:1;
uint64_t inv_lcrc:1;
#else
uint64_t inv_lcrc:1;
uint64_t inv_ecrc:1;
uint64_t reserved_2_2:1;
uint64_t ro_ctlp:1;
uint64_t lnk_enb:1;
uint64_t dly_one:1;
uint64_t nf_ecrc:1;
uint64_t reserved_7_8:2;
uint64_t ob_p_cmd:1;
uint64_t pm_xpme:1;
uint64_t pm_xtoff:1;
uint64_t reserved_12_12:1;
uint64_t qlm_cfg:2;
uint64_t pbus:8;
uint64_t dnum:5;
uint64_t reserved_28_63:36;
#endif
} cn56xx;
struct cvmx_pescx_ctl_status_cn56xx cn56xxp1;
};
@ -190,14 +294,25 @@ union cvmx_pescx_ctl_status {
union cvmx_pescx_ctl_status2 {
uint64_t u64;
struct cvmx_pescx_ctl_status2_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63:62;
uint64_t pclk_run:1;
uint64_t pcierst:1;
#else
uint64_t pcierst:1;
uint64_t pclk_run:1;
uint64_t reserved_2_63:62;
#endif
} s;
struct cvmx_pescx_ctl_status2_s cn52xx;
struct cvmx_pescx_ctl_status2_cn52xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63:63;
uint64_t pcierst:1;
#else
uint64_t pcierst:1;
uint64_t reserved_1_63:63;
#endif
} cn52xxp1;
struct cvmx_pescx_ctl_status2_s cn56xx;
struct cvmx_pescx_ctl_status2_cn52xxp1 cn56xxp1;
@ -206,6 +321,7 @@ union cvmx_pescx_ctl_status2 {
union cvmx_pescx_dbg_info {
uint64_t u64;
struct cvmx_pescx_dbg_info_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_31_63:33;
uint64_t ecrc_e:1;
uint64_t rawwpp:1;
@ -238,6 +354,40 @@ union cvmx_pescx_dbg_info {
uint64_t rtlplle:1;
uint64_t rtlpmal:1;
uint64_t spoison:1;
#else
uint64_t spoison:1;
uint64_t rtlpmal:1;
uint64_t rtlplle:1;
uint64_t recrce:1;
uint64_t rpoison:1;
uint64_t rcemrc:1;
uint64_t rnfemrc:1;
uint64_t rfemrc:1;
uint64_t rpmerc:1;
uint64_t rptamrc:1;
uint64_t rumep:1;
uint64_t rvdm:1;
uint64_t acto:1;
uint64_t rte:1;
uint64_t mre:1;
uint64_t rdwdle:1;
uint64_t rtwdle:1;
uint64_t dpeoosd:1;
uint64_t fcpvwt:1;
uint64_t rpe:1;
uint64_t fcuv:1;
uint64_t rqo:1;
uint64_t rauc:1;
uint64_t racur:1;
uint64_t racca:1;
uint64_t caar:1;
uint64_t rarwdns:1;
uint64_t ramtlp:1;
uint64_t racpp:1;
uint64_t rawwpp:1;
uint64_t ecrc_e:1;
uint64_t reserved_31_63:33;
#endif
} s;
struct cvmx_pescx_dbg_info_s cn52xx;
struct cvmx_pescx_dbg_info_s cn52xxp1;
@ -248,6 +398,7 @@ union cvmx_pescx_dbg_info {
union cvmx_pescx_dbg_info_en {
uint64_t u64;
struct cvmx_pescx_dbg_info_en_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_31_63:33;
uint64_t ecrc_e:1;
uint64_t rawwpp:1;
@ -280,6 +431,40 @@ union cvmx_pescx_dbg_info_en {
uint64_t rtlplle:1;
uint64_t rtlpmal:1;
uint64_t spoison:1;
#else
uint64_t spoison:1;
uint64_t rtlpmal:1;
uint64_t rtlplle:1;
uint64_t recrce:1;
uint64_t rpoison:1;
uint64_t rcemrc:1;
uint64_t rnfemrc:1;
uint64_t rfemrc:1;
uint64_t rpmerc:1;
uint64_t rptamrc:1;
uint64_t rumep:1;
uint64_t rvdm:1;
uint64_t acto:1;
uint64_t rte:1;
uint64_t mre:1;
uint64_t rdwdle:1;
uint64_t rtwdle:1;
uint64_t dpeoosd:1;
uint64_t fcpvwt:1;
uint64_t rpe:1;
uint64_t fcuv:1;
uint64_t rqo:1;
uint64_t rauc:1;
uint64_t racur:1;
uint64_t racca:1;
uint64_t caar:1;
uint64_t rarwdns:1;
uint64_t ramtlp:1;
uint64_t racpp:1;
uint64_t rawwpp:1;
uint64_t ecrc_e:1;
uint64_t reserved_31_63:33;
#endif
} s;
struct cvmx_pescx_dbg_info_en_s cn52xx;
struct cvmx_pescx_dbg_info_en_s cn52xxp1;
@ -290,11 +475,19 @@ union cvmx_pescx_dbg_info_en {
union cvmx_pescx_diag_status {
uint64_t u64;
struct cvmx_pescx_diag_status_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63:60;
uint64_t pm_dst:1;
uint64_t pm_stat:1;
uint64_t pm_en:1;
uint64_t aux_en:1;
#else
uint64_t aux_en:1;
uint64_t pm_en:1;
uint64_t pm_stat:1;
uint64_t pm_dst:1;
uint64_t reserved_4_63:60;
#endif
} s;
struct cvmx_pescx_diag_status_s cn52xx;
struct cvmx_pescx_diag_status_s cn52xxp1;
@ -305,8 +498,13 @@ union cvmx_pescx_diag_status {
union cvmx_pescx_p2n_bar0_start {
uint64_t u64;
struct cvmx_pescx_p2n_bar0_start_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t addr:50;
uint64_t reserved_0_13:14;
#else
uint64_t reserved_0_13:14;
uint64_t addr:50;
#endif
} s;
struct cvmx_pescx_p2n_bar0_start_s cn52xx;
struct cvmx_pescx_p2n_bar0_start_s cn52xxp1;
@ -317,8 +515,13 @@ union cvmx_pescx_p2n_bar0_start {
union cvmx_pescx_p2n_bar1_start {
uint64_t u64;
struct cvmx_pescx_p2n_bar1_start_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t addr:38;
uint64_t reserved_0_25:26;
#else
uint64_t reserved_0_25:26;
uint64_t addr:38;
#endif
} s;
struct cvmx_pescx_p2n_bar1_start_s cn52xx;
struct cvmx_pescx_p2n_bar1_start_s cn52xxp1;
@ -329,8 +532,13 @@ union cvmx_pescx_p2n_bar1_start {
union cvmx_pescx_p2n_bar2_start {
uint64_t u64;
struct cvmx_pescx_p2n_bar2_start_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t addr:25;
uint64_t reserved_0_38:39;
#else
uint64_t reserved_0_38:39;
uint64_t addr:25;
#endif
} s;
struct cvmx_pescx_p2n_bar2_start_s cn52xx;
struct cvmx_pescx_p2n_bar2_start_s cn52xxp1;
@ -341,8 +549,13 @@ union cvmx_pescx_p2n_bar2_start {
union cvmx_pescx_p2p_barx_end {
uint64_t u64;
struct cvmx_pescx_p2p_barx_end_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t addr:52;
uint64_t reserved_0_11:12;
#else
uint64_t reserved_0_11:12;
uint64_t addr:52;
#endif
} s;
struct cvmx_pescx_p2p_barx_end_s cn52xx;
struct cvmx_pescx_p2p_barx_end_s cn52xxp1;
@ -353,8 +566,13 @@ union cvmx_pescx_p2p_barx_end {
union cvmx_pescx_p2p_barx_start {
uint64_t u64;
struct cvmx_pescx_p2p_barx_start_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t addr:52;
uint64_t reserved_0_11:12;
#else
uint64_t reserved_0_11:12;
uint64_t addr:52;
#endif
} s;
struct cvmx_pescx_p2p_barx_start_s cn52xx;
struct cvmx_pescx_p2p_barx_start_s cn52xxp1;
@ -365,9 +583,14 @@ union cvmx_pescx_p2p_barx_start {
union cvmx_pescx_tlp_credits {
uint64_t u64;
struct cvmx_pescx_tlp_credits_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_0_63:64;
#else
uint64_t reserved_0_63:64;
#endif
} s;
struct cvmx_pescx_tlp_credits_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_56_63:8;
uint64_t peai_ppf:8;
uint64_t pesc_cpl:8;
@ -376,8 +599,19 @@ union cvmx_pescx_tlp_credits {
uint64_t npei_cpl:8;
uint64_t npei_np:8;
uint64_t npei_p:8;
#else
uint64_t npei_p:8;
uint64_t npei_np:8;
uint64_t npei_cpl:8;
uint64_t pesc_p:8;
uint64_t pesc_np:8;
uint64_t pesc_cpl:8;
uint64_t peai_ppf:8;
uint64_t reserved_56_63:8;
#endif
} cn52xx;
struct cvmx_pescx_tlp_credits_cn52xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_38_63:26;
uint64_t peai_ppf:8;
uint64_t pesc_cpl:5;
@ -386,6 +620,16 @@ union cvmx_pescx_tlp_credits {
uint64_t npei_cpl:5;
uint64_t npei_np:5;
uint64_t npei_p:5;
#else
uint64_t npei_p:5;
uint64_t npei_np:5;
uint64_t npei_cpl:5;
uint64_t pesc_p:5;
uint64_t pesc_np:5;
uint64_t pesc_cpl:5;
uint64_t peai_ppf:8;
uint64_t reserved_38_63:26;
#endif
} cn52xxp1;
struct cvmx_pescx_tlp_credits_cn52xx cn56xx;
struct cvmx_pescx_tlp_credits_cn52xxp1 cn56xxp1;

2
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
View File

@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2011 Cavium Networks
* Copyright (c) 2003-2012 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as

2543
arch/mips/include/asm/octeon/cvmx-pip-defs.h
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File diff suppressed because it is too large Load Diff

1965
arch/mips/include/asm/octeon/cvmx-pko-defs.h
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File diff suppressed because it is too large Load Diff

530
arch/mips/include/asm/octeon/cvmx-pow-defs.h
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File diff suppressed because it is too large Load Diff

153
arch/mips/include/asm/octeon/cvmx-rnm-defs.h
View File

@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2010 Cavium Networks
* Copyright (c) 2003-2012 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@ -28,8 +28,6 @@
#ifndef __CVMX_RNM_DEFS_H__
#define __CVMX_RNM_DEFS_H__
#include <linux/types.h>
#define CVMX_RNM_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001180040000008ull))
#define CVMX_RNM_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180040000000ull))
#define CVMX_RNM_EER_DBG (CVMX_ADD_IO_SEG(0x0001180040000018ull))
@ -39,9 +37,15 @@
union cvmx_rnm_bist_status {
uint64_t u64;
struct cvmx_rnm_bist_status_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63:62;
uint64_t rrc:1;
uint64_t mem:1;
#else
uint64_t mem:1;
uint64_t rrc:1;
uint64_t reserved_2_63:62;
#endif
} s;
struct cvmx_rnm_bist_status_s cn30xx;
struct cvmx_rnm_bist_status_s cn31xx;
@ -54,13 +58,88 @@ union cvmx_rnm_bist_status {
struct cvmx_rnm_bist_status_s cn56xxp1;
struct cvmx_rnm_bist_status_s cn58xx;
struct cvmx_rnm_bist_status_s cn58xxp1;
struct cvmx_rnm_bist_status_s cn61xx;
struct cvmx_rnm_bist_status_s cn63xx;
struct cvmx_rnm_bist_status_s cn63xxp1;
struct cvmx_rnm_bist_status_s cn66xx;
struct cvmx_rnm_bist_status_s cn68xx;
struct cvmx_rnm_bist_status_s cn68xxp1;
struct cvmx_rnm_bist_status_s cnf71xx;
};
union cvmx_rnm_ctl_status {
uint64_t u64;
struct cvmx_rnm_ctl_status_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63:52;
uint64_t dis_mak:1;
uint64_t eer_lck:1;
uint64_t eer_val:1;
uint64_t ent_sel:4;
uint64_t exp_ent:1;
uint64_t rng_rst:1;
uint64_t rnm_rst:1;
uint64_t rng_en:1;
uint64_t ent_en:1;
#else
uint64_t ent_en:1;
uint64_t rng_en:1;
uint64_t rnm_rst:1;
uint64_t rng_rst:1;
uint64_t exp_ent:1;
uint64_t ent_sel:4;
uint64_t eer_val:1;
uint64_t eer_lck:1;
uint64_t dis_mak:1;
uint64_t reserved_12_63:52;
#endif
} s;
struct cvmx_rnm_ctl_status_cn30xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63:60;
uint64_t rng_rst:1;
uint64_t rnm_rst:1;
uint64_t rng_en:1;
uint64_t ent_en:1;
#else
uint64_t ent_en:1;
uint64_t rng_en:1;
uint64_t rnm_rst:1;
uint64_t rng_rst:1;
uint64_t reserved_4_63:60;
#endif
} cn30xx;
struct cvmx_rnm_ctl_status_cn30xx cn31xx;
struct cvmx_rnm_ctl_status_cn30xx cn38xx;
struct cvmx_rnm_ctl_status_cn30xx cn38xxp2;
struct cvmx_rnm_ctl_status_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_9_63:55;
uint64_t ent_sel:4;
uint64_t exp_ent:1;
uint64_t rng_rst:1;
uint64_t rnm_rst:1;
uint64_t rng_en:1;
uint64_t ent_en:1;
#else
uint64_t ent_en:1;
uint64_t rng_en:1;
uint64_t rnm_rst:1;
uint64_t rng_rst:1;
uint64_t exp_ent:1;
uint64_t ent_sel:4;
uint64_t reserved_9_63:55;
#endif
} cn50xx;
struct cvmx_rnm_ctl_status_cn50xx cn52xx;
struct cvmx_rnm_ctl_status_cn50xx cn52xxp1;
struct cvmx_rnm_ctl_status_cn50xx cn56xx;
struct cvmx_rnm_ctl_status_cn50xx cn56xxp1;
struct cvmx_rnm_ctl_status_cn50xx cn58xx;
struct cvmx_rnm_ctl_status_cn50xx cn58xxp1;
struct cvmx_rnm_ctl_status_s cn61xx;
struct cvmx_rnm_ctl_status_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_11_63:53;
uint64_t eer_lck:1;
uint64_t eer_val:1;
@ -70,60 +149,76 @@ union cvmx_rnm_ctl_status {
uint64_t rnm_rst:1;
uint64_t rng_en:1;
uint64_t ent_en:1;
} s;
struct cvmx_rnm_ctl_status_cn30xx {
uint64_t reserved_4_63:60;
uint64_t rng_rst:1;
uint64_t rnm_rst:1;
uint64_t rng_en:1;
#else
uint64_t ent_en:1;
} cn30xx;
struct cvmx_rnm_ctl_status_cn30xx cn31xx;
struct cvmx_rnm_ctl_status_cn30xx cn38xx;
struct cvmx_rnm_ctl_status_cn30xx cn38xxp2;
struct cvmx_rnm_ctl_status_cn50xx {
uint64_t reserved_9_63:55;
uint64_t ent_sel:4;
uint64_t rng_en:1;
uint64_t rnm_rst:1;
uint64_t rng_rst:1;
uint64_t exp_ent:1;
uint64_t rng_rst:1;
uint64_t rnm_rst:1;
uint64_t rng_en:1;
uint64_t ent_en:1;
} cn50xx;
struct cvmx_rnm_ctl_status_cn50xx cn52xx;
struct cvmx_rnm_ctl_status_cn50xx cn52xxp1;
struct cvmx_rnm_ctl_status_cn50xx cn56xx;
struct cvmx_rnm_ctl_status_cn50xx cn56xxp1;
struct cvmx_rnm_ctl_status_cn50xx cn58xx;
struct cvmx_rnm_ctl_status_cn50xx cn58xxp1;
struct cvmx_rnm_ctl_status_s cn63xx;
struct cvmx_rnm_ctl_status_s cn63xxp1;
uint64_t ent_sel:4;
uint64_t eer_val:1;
uint64_t eer_lck:1;
uint64_t reserved_11_63:53;
#endif
} cn63xx;
struct cvmx_rnm_ctl_status_cn63xx cn63xxp1;
struct cvmx_rnm_ctl_status_s cn66xx;
struct cvmx_rnm_ctl_status_cn63xx cn68xx;
struct cvmx_rnm_ctl_status_cn63xx cn68xxp1;
struct cvmx_rnm_ctl_status_s cnf71xx;
};
union cvmx_rnm_eer_dbg {
uint64_t u64;
struct cvmx_rnm_eer_dbg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t dat:64;
#else
uint64_t dat:64;
#endif
} s;
struct cvmx_rnm_eer_dbg_s cn61xx;
struct cvmx_rnm_eer_dbg_s cn63xx;
struct cvmx_rnm_eer_dbg_s cn63xxp1;
struct cvmx_rnm_eer_dbg_s cn66xx;
struct cvmx_rnm_eer_dbg_s cn68xx;
struct cvmx_rnm_eer_dbg_s cn68xxp1;
struct cvmx_rnm_eer_dbg_s cnf71xx;
};
union cvmx_rnm_eer_key {
uint64_t u64;
struct cvmx_rnm_eer_key_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t key:64;
#else
uint64_t key:64;
#endif
} s;
struct cvmx_rnm_eer_key_s cn61xx;
struct cvmx_rnm_eer_key_s cn63xx;
struct cvmx_rnm_eer_key_s cn63xxp1;
struct cvmx_rnm_eer_key_s cn66xx;
struct cvmx_rnm_eer_key_s cn68xx;
struct cvmx_rnm_eer_key_s cn68xxp1;
struct cvmx_rnm_eer_key_s cnf71xx;
};
union cvmx_rnm_serial_num {
uint64_t u64;
struct cvmx_rnm_serial_num_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t dat:64;
#else
uint64_t dat:64;
#endif
} s;
struct cvmx_rnm_serial_num_s cn61xx;
struct cvmx_rnm_serial_num_s cn63xx;
struct cvmx_rnm_serial_num_s cn66xx;
struct cvmx_rnm_serial_num_s cn68xx;
struct cvmx_rnm_serial_num_s cn68xxp1;
struct cvmx_rnm_serial_num_s cnf71xx;
};
#endif

1351
arch/mips/include/asm/octeon/cvmx-sli-defs.h
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File diff suppressed because it is too large Load Diff

202
arch/mips/include/asm/octeon/cvmx-smix-defs.h
View File

@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2010 Cavium Networks
* Copyright (c) 2003-2012 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@ -28,15 +28,120 @@
#ifndef __CVMX_SMIX_DEFS_H__
#define __CVMX_SMIX_DEFS_H__
#define CVMX_SMIX_CLK(offset) (CVMX_ADD_IO_SEG(0x0001180000001818ull) + ((offset) & 1) * 256)
#define CVMX_SMIX_CMD(offset) (CVMX_ADD_IO_SEG(0x0001180000001800ull) + ((offset) & 1) * 256)
#define CVMX_SMIX_EN(offset) (CVMX_ADD_IO_SEG(0x0001180000001820ull) + ((offset) & 1) * 256)
#define CVMX_SMIX_RD_DAT(offset) (CVMX_ADD_IO_SEG(0x0001180000001810ull) + ((offset) & 1) * 256)
#define CVMX_SMIX_WR_DAT(offset) (CVMX_ADD_IO_SEG(0x0001180000001808ull) + ((offset) & 1) * 256)
static inline uint64_t CVMX_SMIX_CLK(unsigned long offset)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256;
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180000003818ull) + (offset) * 128;
}
return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256;
}
static inline uint64_t CVMX_SMIX_CMD(unsigned long offset)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256;
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180000003800ull) + (offset) * 128;
}
return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256;
}
static inline uint64_t CVMX_SMIX_EN(unsigned long offset)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256;
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180000003820ull) + (offset) * 128;
}
return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256;
}
static inline uint64_t CVMX_SMIX_RD_DAT(unsigned long offset)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256;
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180000003810ull) + (offset) * 128;
}
return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256;
}
static inline uint64_t CVMX_SMIX_WR_DAT(unsigned long offset)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256;
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180000003808ull) + (offset) * 128;
}
return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256;
}
union cvmx_smix_clk {
uint64_t u64;
struct cvmx_smix_clk_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_25_63:39;
uint64_t mode:1;
uint64_t reserved_21_23:3;
@ -47,8 +152,21 @@ union cvmx_smix_clk {
uint64_t preamble:1;
uint64_t sample:4;
uint64_t phase:8;
#else
uint64_t phase:8;
uint64_t sample:4;
uint64_t preamble:1;
uint64_t clk_idle:1;
uint64_t reserved_14_14:1;
uint64_t sample_mode:1;
uint64_t sample_hi:5;
uint64_t reserved_21_23:3;
uint64_t mode:1;
uint64_t reserved_25_63:39;
#endif
} s;
struct cvmx_smix_clk_cn30xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_21_63:43;
uint64_t sample_hi:5;
uint64_t sample_mode:1;
@ -57,6 +175,16 @@ union cvmx_smix_clk {
uint64_t preamble:1;
uint64_t sample:4;
uint64_t phase:8;
#else
uint64_t phase:8;
uint64_t sample:4;
uint64_t preamble:1;
uint64_t clk_idle:1;
uint64_t reserved_14_14:1;
uint64_t sample_mode:1;
uint64_t sample_hi:5;
uint64_t reserved_21_63:43;
#endif
} cn30xx;
struct cvmx_smix_clk_cn30xx cn31xx;
struct cvmx_smix_clk_cn30xx cn38xx;
@ -68,27 +196,50 @@ union cvmx_smix_clk {
struct cvmx_smix_clk_s cn56xxp1;
struct cvmx_smix_clk_cn30xx cn58xx;
struct cvmx_smix_clk_cn30xx cn58xxp1;
struct cvmx_smix_clk_s cn61xx;
struct cvmx_smix_clk_s cn63xx;
struct cvmx_smix_clk_s cn63xxp1;
struct cvmx_smix_clk_s cn66xx;
struct cvmx_smix_clk_s cn68xx;
struct cvmx_smix_clk_s cn68xxp1;
struct cvmx_smix_clk_s cnf71xx;
};
union cvmx_smix_cmd {
uint64_t u64;
struct cvmx_smix_cmd_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_18_63:46;
uint64_t phy_op:2;
uint64_t reserved_13_15:3;
uint64_t phy_adr:5;
uint64_t reserved_5_7:3;
uint64_t reg_adr:5;
#else
uint64_t reg_adr:5;
uint64_t reserved_5_7:3;
uint64_t phy_adr:5;
uint64_t reserved_13_15:3;
uint64_t phy_op:2;
uint64_t reserved_18_63:46;
#endif
} s;
struct cvmx_smix_cmd_cn30xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_17_63:47;
uint64_t phy_op:1;
uint64_t reserved_13_15:3;
uint64_t phy_adr:5;
uint64_t reserved_5_7:3;
uint64_t reg_adr:5;
#else
uint64_t reg_adr:5;
uint64_t reserved_5_7:3;
uint64_t phy_adr:5;
uint64_t reserved_13_15:3;
uint64_t phy_op:1;
uint64_t reserved_17_63:47;
#endif
} cn30xx;
struct cvmx_smix_cmd_cn30xx cn31xx;
struct cvmx_smix_cmd_cn30xx cn38xx;
@ -100,15 +251,25 @@ union cvmx_smix_cmd {
struct cvmx_smix_cmd_s cn56xxp1;
struct cvmx_smix_cmd_cn30xx cn58xx;
struct cvmx_smix_cmd_cn30xx cn58xxp1;
struct cvmx_smix_cmd_s cn61xx;
struct cvmx_smix_cmd_s cn63xx;
struct cvmx_smix_cmd_s cn63xxp1;
struct cvmx_smix_cmd_s cn66xx;
struct cvmx_smix_cmd_s cn68xx;
struct cvmx_smix_cmd_s cn68xxp1;
struct cvmx_smix_cmd_s cnf71xx;
};
union cvmx_smix_en {
uint64_t u64;
struct cvmx_smix_en_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63:63;
uint64_t en:1;
#else
uint64_t en:1;
uint64_t reserved_1_63:63;
#endif
} s;
struct cvmx_smix_en_s cn30xx;
struct cvmx_smix_en_s cn31xx;
@ -121,17 +282,29 @@ union cvmx_smix_en {
struct cvmx_smix_en_s cn56xxp1;
struct cvmx_smix_en_s cn58xx;
struct cvmx_smix_en_s cn58xxp1;
struct cvmx_smix_en_s cn61xx;
struct cvmx_smix_en_s cn63xx;
struct cvmx_smix_en_s cn63xxp1;
struct cvmx_smix_en_s cn66xx;
struct cvmx_smix_en_s cn68xx;
struct cvmx_smix_en_s cn68xxp1;
struct cvmx_smix_en_s cnf71xx;
};
union cvmx_smix_rd_dat {
uint64_t u64;
struct cvmx_smix_rd_dat_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_18_63:46;
uint64_t pending:1;
uint64_t val:1;
uint64_t dat:16;
#else
uint64_t dat:16;
uint64_t val:1;
uint64_t pending:1;
uint64_t reserved_18_63:46;
#endif
} s;
struct cvmx_smix_rd_dat_s cn30xx;
struct cvmx_smix_rd_dat_s cn31xx;
@ -144,17 +317,29 @@ union cvmx_smix_rd_dat {
struct cvmx_smix_rd_dat_s cn56xxp1;
struct cvmx_smix_rd_dat_s cn58xx;
struct cvmx_smix_rd_dat_s cn58xxp1;
struct cvmx_smix_rd_dat_s cn61xx;
struct cvmx_smix_rd_dat_s cn63xx;
struct cvmx_smix_rd_dat_s cn63xxp1;
struct cvmx_smix_rd_dat_s cn66xx;
struct cvmx_smix_rd_dat_s cn68xx;
struct cvmx_smix_rd_dat_s cn68xxp1;
struct cvmx_smix_rd_dat_s cnf71xx;
};
union cvmx_smix_wr_dat {
uint64_t u64;
struct cvmx_smix_wr_dat_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_18_63:46;
uint64_t pending:1;
uint64_t val:1;
uint64_t dat:16;
#else
uint64_t dat:16;
uint64_t val:1;
uint64_t pending:1;
uint64_t reserved_18_63:46;
#endif
} s;
struct cvmx_smix_wr_dat_s cn30xx;
struct cvmx_smix_wr_dat_s cn31xx;
@ -167,8 +352,13 @@ union cvmx_smix_wr_dat {
struct cvmx_smix_wr_dat_s cn56xxp1;
struct cvmx_smix_wr_dat_s cn58xx;
struct cvmx_smix_wr_dat_s cn58xxp1;
struct cvmx_smix_wr_dat_s cn61xx;
struct cvmx_smix_wr_dat_s cn63xx;
struct cvmx_smix_wr_dat_s cn63xxp1;
struct cvmx_smix_wr_dat_s cn66xx;
struct cvmx_smix_wr_dat_s cn68xx;
struct cvmx_smix_wr_dat_s cn68xxp1;
struct cvmx_smix_wr_dat_s cnf71xx;
};
#endif

225
arch/mips/include/asm/octeon/cvmx-spxx-defs.h
View File

@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2008 Cavium Networks
* Copyright (c) 2003-2012 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@ -28,44 +28,33 @@
#ifndef __CVMX_SPXX_DEFS_H__
#define __CVMX_SPXX_DEFS_H__
#define CVMX_SPXX_BCKPRS_CNT(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000340ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_SPXX_BIST_STAT(block_id) \
CVMX_ADD_IO_SEG(0x00011800900007F8ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_SPXX_CLK_CTL(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000348ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_SPXX_CLK_STAT(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000350ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_SPXX_DBG_DESKEW_CTL(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000368ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_SPXX_DBG_DESKEW_STATE(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000370ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_SPXX_DRV_CTL(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000358ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_SPXX_ERR_CTL(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000320ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_SPXX_INT_DAT(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000318ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_SPXX_INT_MSK(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000308ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_SPXX_INT_REG(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000300ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_SPXX_INT_SYNC(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000310ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_SPXX_TPA_ACC(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000338ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_SPXX_TPA_MAX(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000330ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_SPXX_TPA_SEL(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000328ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_SPXX_TRN4_CTL(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000360ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_SPXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000340ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_BIST_STAT(block_id) (CVMX_ADD_IO_SEG(0x00011800900007F8ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000348ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_CLK_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000350ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_DBG_DESKEW_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000368ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_DBG_DESKEW_STATE(block_id) (CVMX_ADD_IO_SEG(0x0001180090000370ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_DRV_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000358ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_ERR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000320ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_INT_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000318ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180090000308ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000300ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000310ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_TPA_ACC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000338ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_TPA_MAX(block_id) (CVMX_ADD_IO_SEG(0x0001180090000330ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_TPA_SEL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000328ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_TRN4_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000360ull) + ((block_id) & 1) * 0x8000000ull)
union cvmx_spxx_bckprs_cnt {
uint64_t u64;
struct cvmx_spxx_bckprs_cnt_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
uint64_t cnt:32;
#else
uint64_t cnt:32;
uint64_t reserved_32_63:32;
#endif
} s;
struct cvmx_spxx_bckprs_cnt_s cn38xx;
struct cvmx_spxx_bckprs_cnt_s cn38xxp2;
@ -76,10 +65,17 @@ union cvmx_spxx_bckprs_cnt {
union cvmx_spxx_bist_stat {
uint64_t u64;
struct cvmx_spxx_bist_stat_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_3_63:61;
uint64_t stat2:1;
uint64_t stat1:1;
uint64_t stat0:1;
#else
uint64_t stat0:1;
uint64_t stat1:1;
uint64_t stat2:1;
uint64_t reserved_3_63:61;
#endif
} s;
struct cvmx_spxx_bist_stat_s cn38xx;
struct cvmx_spxx_bist_stat_s cn38xxp2;
@ -90,6 +86,7 @@ union cvmx_spxx_bist_stat {
union cvmx_spxx_clk_ctl {
uint64_t u64;
struct cvmx_spxx_clk_ctl_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_17_63:47;
uint64_t seetrn:1;
uint64_t reserved_12_15:4;
@ -101,6 +98,19 @@ union cvmx_spxx_clk_ctl {
uint64_t drptrn:1;
uint64_t rcvtrn:1;
uint64_t srxdlck:1;
#else
uint64_t srxdlck:1;
uint64_t rcvtrn:1;
uint64_t drptrn:1;
uint64_t sndtrn:1;
uint64_t statrcv:1;
uint64_t statdrv:1;
uint64_t runbist:1;
uint64_t clkdly:5;
uint64_t reserved_12_15:4;
uint64_t seetrn:1;
uint64_t reserved_17_63:47;
#endif
} s;
struct cvmx_spxx_clk_ctl_s cn38xx;
struct cvmx_spxx_clk_ctl_s cn38xxp2;
@ -111,6 +121,7 @@ union cvmx_spxx_clk_ctl {
union cvmx_spxx_clk_stat {
uint64_t u64;
struct cvmx_spxx_clk_stat_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_11_63:53;
uint64_t stxcal:1;
uint64_t reserved_9_9:1;
@ -120,6 +131,17 @@ union cvmx_spxx_clk_stat {
uint64_t d4clk1:1;
uint64_t d4clk0:1;
uint64_t reserved_0_3:4;
#else
uint64_t reserved_0_3:4;
uint64_t d4clk0:1;
uint64_t d4clk1:1;
uint64_t s4clk0:1;
uint64_t s4clk1:1;
uint64_t srxtrn:1;
uint64_t reserved_9_9:1;
uint64_t stxcal:1;
uint64_t reserved_11_63:53;
#endif
} s;
struct cvmx_spxx_clk_stat_s cn38xx;
struct cvmx_spxx_clk_stat_s cn38xxp2;
@ -130,6 +152,7 @@ union cvmx_spxx_clk_stat {
union cvmx_spxx_dbg_deskew_ctl {
uint64_t u64;
struct cvmx_spxx_dbg_deskew_ctl_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_30_63:34;
uint64_t fallnop:1;
uint64_t fall8:1;
@ -146,6 +169,24 @@ union cvmx_spxx_dbg_deskew_ctl {
uint64_t offdly:6;
uint64_t dllfrc:1;
uint64_t dlldis:1;
#else
uint64_t dlldis:1;
uint64_t dllfrc:1;
uint64_t offdly:6;
uint64_t bitsel:5;
uint64_t offset:5;
uint64_t mux:1;
uint64_t inc:1;
uint64_t dec:1;
uint64_t clrdly:1;
uint64_t reserved_22_23:2;
uint64_t sstep:1;
uint64_t sstep_go:1;
uint64_t reserved_26_27:2;
uint64_t fall8:1;
uint64_t fallnop:1;
uint64_t reserved_30_63:34;
#endif
} s;
struct cvmx_spxx_dbg_deskew_ctl_s cn38xx;
struct cvmx_spxx_dbg_deskew_ctl_s cn38xxp2;
@ -156,11 +197,19 @@ union cvmx_spxx_dbg_deskew_ctl {
union cvmx_spxx_dbg_deskew_state {
uint64_t u64;
struct cvmx_spxx_dbg_deskew_state_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_9_63:55;
uint64_t testres:1;
uint64_t unxterm:1;
uint64_t muxsel:2;
uint64_t offset:5;
#else
uint64_t offset:5;
uint64_t muxsel:2;
uint64_t unxterm:1;
uint64_t testres:1;
uint64_t reserved_9_63:55;
#endif
} s;
struct cvmx_spxx_dbg_deskew_state_s cn38xx;
struct cvmx_spxx_dbg_deskew_state_s cn38xxp2;
@ -171,21 +220,40 @@ union cvmx_spxx_dbg_deskew_state {
union cvmx_spxx_drv_ctl {
uint64_t u64;
struct cvmx_spxx_drv_ctl_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_0_63:64;
#else
uint64_t reserved_0_63:64;
#endif
} s;
struct cvmx_spxx_drv_ctl_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t stx4ncmp:4;
uint64_t stx4pcmp:4;
uint64_t srx4cmp:8;
#else
uint64_t srx4cmp:8;
uint64_t stx4pcmp:4;
uint64_t stx4ncmp:4;
uint64_t reserved_16_63:48;
#endif
} cn38xx;
struct cvmx_spxx_drv_ctl_cn38xx cn38xxp2;
struct cvmx_spxx_drv_ctl_cn58xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_24_63:40;
uint64_t stx4ncmp:4;
uint64_t stx4pcmp:4;
uint64_t reserved_10_15:6;
uint64_t srx4cmp:10;
#else
uint64_t srx4cmp:10;
uint64_t reserved_10_15:6;
uint64_t stx4pcmp:4;
uint64_t stx4ncmp:4;
uint64_t reserved_24_63:40;
#endif
} cn58xx;
struct cvmx_spxx_drv_ctl_cn58xx cn58xxp1;
};
@ -193,12 +261,21 @@ union cvmx_spxx_drv_ctl {
union cvmx_spxx_err_ctl {
uint64_t u64;
struct cvmx_spxx_err_ctl_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_9_63:55;
uint64_t prtnxa:1;
uint64_t dipcls:1;
uint64_t dippay:1;
uint64_t reserved_4_5:2;
uint64_t errcnt:4;
#else
uint64_t errcnt:4;
uint64_t reserved_4_5:2;
uint64_t dippay:1;
uint64_t dipcls:1;
uint64_t prtnxa:1;
uint64_t reserved_9_63:55;
#endif
} s;
struct cvmx_spxx_err_ctl_s cn38xx;
struct cvmx_spxx_err_ctl_s cn38xxp2;
@ -209,12 +286,21 @@ union cvmx_spxx_err_ctl {
union cvmx_spxx_int_dat {
uint64_t u64;
struct cvmx_spxx_int_dat_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
uint64_t mul:1;
uint64_t reserved_14_30:17;
uint64_t calbnk:2;
uint64_t rsvop:4;
uint64_t prt:8;
#else
uint64_t prt:8;
uint64_t rsvop:4;
uint64_t calbnk:2;
uint64_t reserved_14_30:17;
uint64_t mul:1;
uint64_t reserved_32_63:32;
#endif
} s;
struct cvmx_spxx_int_dat_s cn38xx;
struct cvmx_spxx_int_dat_s cn38xxp2;
@ -225,6 +311,7 @@ union cvmx_spxx_int_dat {
union cvmx_spxx_int_msk {
uint64_t u64;
struct cvmx_spxx_int_msk_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63:52;
uint64_t calerr:1;
uint64_t syncerr:1;
@ -237,6 +324,20 @@ union cvmx_spxx_int_msk {
uint64_t reserved_2_3:2;
uint64_t abnorm:1;
uint64_t prtnxa:1;
#else
uint64_t prtnxa:1;
uint64_t abnorm:1;
uint64_t reserved_2_3:2;
uint64_t spiovr:1;
uint64_t clserr:1;
uint64_t drwnng:1;
uint64_t rsverr:1;
uint64_t tpaovr:1;
uint64_t diperr:1;
uint64_t syncerr:1;
uint64_t calerr:1;
uint64_t reserved_12_63:52;
#endif
} s;
struct cvmx_spxx_int_msk_s cn38xx;
struct cvmx_spxx_int_msk_s cn38xxp2;
@ -247,6 +348,7 @@ union cvmx_spxx_int_msk {
union cvmx_spxx_int_reg {
uint64_t u64;
struct cvmx_spxx_int_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
uint64_t spf:1;
uint64_t reserved_12_30:19;
@ -261,6 +363,22 @@ union cvmx_spxx_int_reg {
uint64_t reserved_2_3:2;
uint64_t abnorm:1;
uint64_t prtnxa:1;
#else
uint64_t prtnxa:1;
uint64_t abnorm:1;
uint64_t reserved_2_3:2;
uint64_t spiovr:1;
uint64_t clserr:1;
uint64_t drwnng:1;
uint64_t rsverr:1;
uint64_t tpaovr:1;
uint64_t diperr:1;
uint64_t syncerr:1;
uint64_t calerr:1;
uint64_t reserved_12_30:19;
uint64_t spf:1;
uint64_t reserved_32_63:32;
#endif
} s;
struct cvmx_spxx_int_reg_s cn38xx;
struct cvmx_spxx_int_reg_s cn38xxp2;
@ -271,6 +389,7 @@ union cvmx_spxx_int_reg {
union cvmx_spxx_int_sync {
uint64_t u64;
struct cvmx_spxx_int_sync_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63:52;
uint64_t calerr:1;
uint64_t syncerr:1;
@ -283,6 +402,20 @@ union cvmx_spxx_int_sync {
uint64_t reserved_2_3:2;
uint64_t abnorm:1;
uint64_t prtnxa:1;
#else
uint64_t prtnxa:1;
uint64_t abnorm:1;
uint64_t reserved_2_3:2;
uint64_t spiovr:1;
uint64_t clserr:1;
uint64_t drwnng:1;
uint64_t rsverr:1;
uint64_t tpaovr:1;
uint64_t diperr:1;
uint64_t syncerr:1;
uint64_t calerr:1;
uint64_t reserved_12_63:52;
#endif
} s;
struct cvmx_spxx_int_sync_s cn38xx;
struct cvmx_spxx_int_sync_s cn38xxp2;
@ -293,8 +426,13 @@ union cvmx_spxx_int_sync {
union cvmx_spxx_tpa_acc {
uint64_t u64;
struct cvmx_spxx_tpa_acc_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
uint64_t cnt:32;
#else
uint64_t cnt:32;
uint64_t reserved_32_63:32;
#endif
} s;
struct cvmx_spxx_tpa_acc_s cn38xx;
struct cvmx_spxx_tpa_acc_s cn38xxp2;
@ -305,8 +443,13 @@ union cvmx_spxx_tpa_acc {
union cvmx_spxx_tpa_max {
uint64_t u64;
struct cvmx_spxx_tpa_max_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
uint64_t max:32;
#else
uint64_t max:32;
uint64_t reserved_32_63:32;
#endif
} s;
struct cvmx_spxx_tpa_max_s cn38xx;
struct cvmx_spxx_tpa_max_s cn38xxp2;
@ -317,8 +460,13 @@ union cvmx_spxx_tpa_max {
union cvmx_spxx_tpa_sel {
uint64_t u64;
struct cvmx_spxx_tpa_sel_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63:60;
uint64_t prtsel:4;
#else
uint64_t prtsel:4;
uint64_t reserved_4_63:60;
#endif
} s;
struct cvmx_spxx_tpa_sel_s cn38xx;
struct cvmx_spxx_tpa_sel_s cn38xxp2;
@ -329,6 +477,7 @@ union cvmx_spxx_tpa_sel {
union cvmx_spxx_trn4_ctl {
uint64_t u64;
struct cvmx_spxx_trn4_ctl_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_13_63:51;
uint64_t trntest:1;
uint64_t jitter:3;
@ -337,6 +486,16 @@ union cvmx_spxx_trn4_ctl {
uint64_t maxdist:5;
uint64_t macro_en:1;
uint64_t mux_en:1;
#else
uint64_t mux_en:1;
uint64_t macro_en:1;
uint64_t maxdist:5;
uint64_t set_boot:1;
uint64_t clr_boot:1;
uint64_t jitter:3;
uint64_t trntest:1;
uint64_t reserved_13_63:51;
#endif
} s;
struct cvmx_spxx_trn4_ctl_s cn38xx;
struct cvmx_spxx_trn4_ctl_s cn38xxp2;

703
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
View File

File diff suppressed because it is too large Load Diff

62
arch/mips/include/asm/octeon/cvmx-srxx-defs.h
View File

@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2008 Cavium Networks
* Copyright (c) 2003-2012 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@ -28,27 +28,29 @@
#ifndef __CVMX_SRXX_DEFS_H__
#define __CVMX_SRXX_DEFS_H__
#define CVMX_SRXX_COM_CTL(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000200ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_SRXX_IGN_RX_FULL(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000218ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_SRXX_SPI4_CALX(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180090000000ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_SRXX_SPI4_STAT(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000208ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_SRXX_SW_TICK_CTL(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000220ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_SRXX_SW_TICK_DAT(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000228ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_SRXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SRXX_IGN_RX_FULL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000218ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SRXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000000ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
#define CVMX_SRXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000208ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SRXX_SW_TICK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000220ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SRXX_SW_TICK_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000228ull) + ((block_id) & 1) * 0x8000000ull)
union cvmx_srxx_com_ctl {
uint64_t u64;
struct cvmx_srxx_com_ctl_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63:56;
uint64_t prts:4;
uint64_t st_en:1;
uint64_t reserved_1_2:2;
uint64_t inf_en:1;
#else
uint64_t inf_en:1;
uint64_t reserved_1_2:2;
uint64_t st_en:1;
uint64_t prts:4;
uint64_t reserved_8_63:56;
#endif
} s;
struct cvmx_srxx_com_ctl_s cn38xx;
struct cvmx_srxx_com_ctl_s cn38xxp2;
@ -59,8 +61,13 @@ union cvmx_srxx_com_ctl {
union cvmx_srxx_ign_rx_full {
uint64_t u64;
struct cvmx_srxx_ign_rx_full_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t ignore:16;
#else
uint64_t ignore:16;
uint64_t reserved_16_63:48;
#endif
} s;
struct cvmx_srxx_ign_rx_full_s cn38xx;
struct cvmx_srxx_ign_rx_full_s cn38xxp2;
@ -71,12 +78,21 @@ union cvmx_srxx_ign_rx_full {
union cvmx_srxx_spi4_calx {
uint64_t u64;
struct cvmx_srxx_spi4_calx_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_17_63:47;
uint64_t oddpar:1;
uint64_t prt3:4;
uint64_t prt2:4;
uint64_t prt1:4;
uint64_t prt0:4;
#else
uint64_t prt0:4;
uint64_t prt1:4;
uint64_t prt2:4;
uint64_t prt3:4;
uint64_t oddpar:1;
uint64_t reserved_17_63:47;
#endif
} s;
struct cvmx_srxx_spi4_calx_s cn38xx;
struct cvmx_srxx_spi4_calx_s cn38xxp2;
@ -87,10 +103,17 @@ union cvmx_srxx_spi4_calx {
union cvmx_srxx_spi4_stat {
uint64_t u64;
struct cvmx_srxx_spi4_stat_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t m:8;
uint64_t reserved_7_7:1;
uint64_t len:7;
#else
uint64_t len:7;
uint64_t reserved_7_7:1;
uint64_t m:8;
uint64_t reserved_16_63:48;
#endif
} s;
struct cvmx_srxx_spi4_stat_s cn38xx;
struct cvmx_srxx_spi4_stat_s cn38xxp2;
@ -101,12 +124,21 @@ union cvmx_srxx_spi4_stat {
union cvmx_srxx_sw_tick_ctl {
uint64_t u64;
struct cvmx_srxx_sw_tick_ctl_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_14_63:50;
uint64_t eop:1;
uint64_t sop:1;
uint64_t mod:4;
uint64_t opc:4;
uint64_t adr:4;
#else
uint64_t adr:4;
uint64_t opc:4;
uint64_t mod:4;
uint64_t sop:1;
uint64_t eop:1;
uint64_t reserved_14_63:50;
#endif
} s;
struct cvmx_srxx_sw_tick_ctl_s cn38xx;
struct cvmx_srxx_sw_tick_ctl_s cn58xx;
@ -116,7 +148,11 @@ union cvmx_srxx_sw_tick_ctl {
union cvmx_srxx_sw_tick_dat {
uint64_t u64;
struct cvmx_srxx_sw_tick_dat_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t dat:64;
#else
uint64_t dat:64;
#endif
} s;
struct cvmx_srxx_sw_tick_dat_s cn38xx;
struct cvmx_srxx_sw_tick_dat_s cn58xx;

166
arch/mips/include/asm/octeon/cvmx-stxx-defs.h
View File

@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2008 Cavium Networks
* Copyright (c) 2003-2012 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@ -28,47 +28,39 @@
#ifndef __CVMX_STXX_DEFS_H__
#define __CVMX_STXX_DEFS_H__
#define CVMX_STXX_ARB_CTL(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000608ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_STXX_BCKPRS_CNT(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000688ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_STXX_COM_CTL(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000600ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_STXX_DIP_CNT(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000690ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_STXX_IGN_CAL(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000610ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_STXX_INT_MSK(block_id) \
CVMX_ADD_IO_SEG(0x00011800900006A0ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_STXX_INT_REG(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000698ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_STXX_INT_SYNC(block_id) \
CVMX_ADD_IO_SEG(0x00011800900006A8ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_STXX_MIN_BST(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000618ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_STXX_SPI4_CALX(offset, block_id) \
CVMX_ADD_IO_SEG(0x0001180090000400ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_STXX_SPI4_DAT(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000628ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_STXX_SPI4_STAT(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000630ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_STXX_STAT_BYTES_HI(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000648ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_STXX_STAT_BYTES_LO(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000680ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_STXX_STAT_CTL(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000638ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_STXX_STAT_PKT_XMT(block_id) \
CVMX_ADD_IO_SEG(0x0001180090000640ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_STXX_ARB_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_STXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_STXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_STXX_DIP_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_STXX_IGN_CAL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000610ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_STXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A0ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_STXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000698ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_STXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A8ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_STXX_MIN_BST(block_id) (CVMX_ADD_IO_SEG(0x0001180090000618ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_STXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000400ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
#define CVMX_STXX_SPI4_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000628ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_STXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000630ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_STXX_STAT_BYTES_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180090000648ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_STXX_STAT_BYTES_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180090000680ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_STXX_STAT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000638ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_STXX_STAT_PKT_XMT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000640ull) + ((block_id) & 1) * 0x8000000ull)
union cvmx_stxx_arb_ctl {
uint64_t u64;
struct cvmx_stxx_arb_ctl_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_6_63:58;
uint64_t mintrn:1;
uint64_t reserved_4_4:1;
uint64_t igntpa:1;
uint64_t reserved_0_2:3;
#else
uint64_t reserved_0_2:3;
uint64_t igntpa:1;
uint64_t reserved_4_4:1;
uint64_t mintrn:1;
uint64_t reserved_6_63:58;
#endif
} s;
struct cvmx_stxx_arb_ctl_s cn38xx;
struct cvmx_stxx_arb_ctl_s cn38xxp2;
@ -79,8 +71,13 @@ union cvmx_stxx_arb_ctl {
union cvmx_stxx_bckprs_cnt {
uint64_t u64;
struct cvmx_stxx_bckprs_cnt_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
uint64_t cnt:32;
#else
uint64_t cnt:32;
uint64_t reserved_32_63:32;
#endif
} s;
struct cvmx_stxx_bckprs_cnt_s cn38xx;
struct cvmx_stxx_bckprs_cnt_s cn38xxp2;
@ -91,10 +88,17 @@ union cvmx_stxx_bckprs_cnt {
union cvmx_stxx_com_ctl {
uint64_t u64;
struct cvmx_stxx_com_ctl_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63:60;
uint64_t st_en:1;
uint64_t reserved_1_2:2;
uint64_t inf_en:1;
#else
uint64_t inf_en:1;
uint64_t reserved_1_2:2;
uint64_t st_en:1;
uint64_t reserved_4_63:60;
#endif
} s;
struct cvmx_stxx_com_ctl_s cn38xx;
struct cvmx_stxx_com_ctl_s cn38xxp2;
@ -105,9 +109,15 @@ union cvmx_stxx_com_ctl {
union cvmx_stxx_dip_cnt {
uint64_t u64;
struct cvmx_stxx_dip_cnt_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63:56;
uint64_t frmmax:4;
uint64_t dipmax:4;
#else
uint64_t dipmax:4;
uint64_t frmmax:4;
uint64_t reserved_8_63:56;
#endif
} s;
struct cvmx_stxx_dip_cnt_s cn38xx;
struct cvmx_stxx_dip_cnt_s cn38xxp2;
@ -118,8 +128,13 @@ union cvmx_stxx_dip_cnt {
union cvmx_stxx_ign_cal {
uint64_t u64;
struct cvmx_stxx_ign_cal_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t igntpa:16;
#else
uint64_t igntpa:16;
uint64_t reserved_16_63:48;
#endif
} s;
struct cvmx_stxx_ign_cal_s cn38xx;
struct cvmx_stxx_ign_cal_s cn38xxp2;
@ -130,6 +145,7 @@ union cvmx_stxx_ign_cal {
union cvmx_stxx_int_msk {
uint64_t u64;
struct cvmx_stxx_int_msk_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63:56;
uint64_t frmerr:1;
uint64_t unxfrm:1;
@ -139,6 +155,17 @@ union cvmx_stxx_int_msk {
uint64_t ovrbst:1;
uint64_t calpar1:1;
uint64_t calpar0:1;
#else
uint64_t calpar0:1;
uint64_t calpar1:1;
uint64_t ovrbst:1;
uint64_t datovr:1;
uint64_t diperr:1;
uint64_t nosync:1;
uint64_t unxfrm:1;
uint64_t frmerr:1;
uint64_t reserved_8_63:56;
#endif
} s;
struct cvmx_stxx_int_msk_s cn38xx;
struct cvmx_stxx_int_msk_s cn38xxp2;
@ -149,6 +176,7 @@ union cvmx_stxx_int_msk {
union cvmx_stxx_int_reg {
uint64_t u64;
struct cvmx_stxx_int_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_9_63:55;
uint64_t syncerr:1;
uint64_t frmerr:1;
@ -159,6 +187,18 @@ union cvmx_stxx_int_reg {
uint64_t ovrbst:1;
uint64_t calpar1:1;
uint64_t calpar0:1;
#else
uint64_t calpar0:1;
uint64_t calpar1:1;
uint64_t ovrbst:1;
uint64_t datovr:1;
uint64_t diperr:1;
uint64_t nosync:1;
uint64_t unxfrm:1;
uint64_t frmerr:1;
uint64_t syncerr:1;
uint64_t reserved_9_63:55;
#endif
} s;
struct cvmx_stxx_int_reg_s cn38xx;
struct cvmx_stxx_int_reg_s cn38xxp2;
@ -169,6 +209,7 @@ union cvmx_stxx_int_reg {
union cvmx_stxx_int_sync {
uint64_t u64;
struct cvmx_stxx_int_sync_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63:56;
uint64_t frmerr:1;
uint64_t unxfrm:1;
@ -178,6 +219,17 @@ union cvmx_stxx_int_sync {
uint64_t ovrbst:1;
uint64_t calpar1:1;
uint64_t calpar0:1;
#else
uint64_t calpar0:1;
uint64_t calpar1:1;
uint64_t ovrbst:1;
uint64_t datovr:1;
uint64_t diperr:1;
uint64_t nosync:1;
uint64_t unxfrm:1;
uint64_t frmerr:1;
uint64_t reserved_8_63:56;
#endif
} s;
struct cvmx_stxx_int_sync_s cn38xx;
struct cvmx_stxx_int_sync_s cn38xxp2;
@ -188,8 +240,13 @@ union cvmx_stxx_int_sync {
union cvmx_stxx_min_bst {
uint64_t u64;
struct cvmx_stxx_min_bst_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_9_63:55;
uint64_t minb:9;
#else
uint64_t minb:9;
uint64_t reserved_9_63:55;
#endif
} s;
struct cvmx_stxx_min_bst_s cn38xx;
struct cvmx_stxx_min_bst_s cn38xxp2;
@ -200,12 +257,21 @@ union cvmx_stxx_min_bst {
union cvmx_stxx_spi4_calx {
uint64_t u64;
struct cvmx_stxx_spi4_calx_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_17_63:47;
uint64_t oddpar:1;
uint64_t prt3:4;
uint64_t prt2:4;
uint64_t prt1:4;
uint64_t prt0:4;
#else
uint64_t prt0:4;
uint64_t prt1:4;
uint64_t prt2:4;
uint64_t prt3:4;
uint64_t oddpar:1;
uint64_t reserved_17_63:47;
#endif
} s;
struct cvmx_stxx_spi4_calx_s cn38xx;
struct cvmx_stxx_spi4_calx_s cn38xxp2;
@ -216,9 +282,15 @@ union cvmx_stxx_spi4_calx {
union cvmx_stxx_spi4_dat {
uint64_t u64;
struct cvmx_stxx_spi4_dat_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
uint64_t alpha:16;
uint64_t max_t:16;
#else
uint64_t max_t:16;
uint64_t alpha:16;
uint64_t reserved_32_63:32;
#endif
} s;
struct cvmx_stxx_spi4_dat_s cn38xx;
struct cvmx_stxx_spi4_dat_s cn38xxp2;
@ -229,10 +301,17 @@ union cvmx_stxx_spi4_dat {
union cvmx_stxx_spi4_stat {
uint64_t u64;
struct cvmx_stxx_spi4_stat_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t m:8;
uint64_t reserved_7_7:1;
uint64_t len:7;
#else
uint64_t len:7;
uint64_t reserved_7_7:1;
uint64_t m:8;
uint64_t reserved_16_63:48;
#endif
} s;
struct cvmx_stxx_spi4_stat_s cn38xx;
struct cvmx_stxx_spi4_stat_s cn38xxp2;
@ -243,8 +322,13 @@ union cvmx_stxx_spi4_stat {
union cvmx_stxx_stat_bytes_hi {
uint64_t u64;
struct cvmx_stxx_stat_bytes_hi_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
uint64_t cnt:32;
#else
uint64_t cnt:32;
uint64_t reserved_32_63:32;
#endif
} s;
struct cvmx_stxx_stat_bytes_hi_s cn38xx;
struct cvmx_stxx_stat_bytes_hi_s cn38xxp2;
@ -255,8 +339,13 @@ union cvmx_stxx_stat_bytes_hi {
union cvmx_stxx_stat_bytes_lo {
uint64_t u64;
struct cvmx_stxx_stat_bytes_lo_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
uint64_t cnt:32;
#else
uint64_t cnt:32;
uint64_t reserved_32_63:32;
#endif
} s;
struct cvmx_stxx_stat_bytes_lo_s cn38xx;
struct cvmx_stxx_stat_bytes_lo_s cn38xxp2;
@ -267,9 +356,15 @@ union cvmx_stxx_stat_bytes_lo {
union cvmx_stxx_stat_ctl {
uint64_t u64;
struct cvmx_stxx_stat_ctl_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63:59;
uint64_t clr:1;
uint64_t bckprs:4;
#else
uint64_t bckprs:4;
uint64_t clr:1;
uint64_t reserved_5_63:59;
#endif
} s;
struct cvmx_stxx_stat_ctl_s cn38xx;
struct cvmx_stxx_stat_ctl_s cn38xxp2;
@ -280,8 +375,13 @@ union cvmx_stxx_stat_ctl {
union cvmx_stxx_stat_pkt_xmt {
uint64_t u64;
struct cvmx_stxx_stat_pkt_xmt_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
uint64_t cnt:32;
#else
uint64_t cnt:32;
uint64_t reserved_32_63:32;
#endif
} s;
struct cvmx_stxx_stat_pkt_xmt_s cn38xx;
struct cvmx_stxx_stat_pkt_xmt_s cn38xxp2;

268
arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
View File

@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2010 Cavium Networks
* Copyright (c) 2003-2012 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@ -25,8 +25,8 @@
* Contact Cavium Networks for more information
***********************license end**************************************/
#ifndef __CVMX_UCTLX_TYPEDEFS_H__
#define __CVMX_UCTLX_TYPEDEFS_H__
#ifndef __CVMX_UCTLX_DEFS_H__
#define __CVMX_UCTLX_DEFS_H__
#define CVMX_UCTLX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A0ull))
#define CVMX_UCTLX_CLK_RST_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000000ull))
@ -45,6 +45,7 @@
union cvmx_uctlx_bist_status {
uint64_t u64;
struct cvmx_uctlx_bist_status_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_6_63:58;
uint64_t data_bis:1;
uint64_t desc_bis:1;
@ -52,14 +53,29 @@ union cvmx_uctlx_bist_status {
uint64_t orbm_bis:1;
uint64_t wrbm_bis:1;
uint64_t ppaf_bis:1;
#else
uint64_t ppaf_bis:1;
uint64_t wrbm_bis:1;
uint64_t orbm_bis:1;
uint64_t erbm_bis:1;
uint64_t desc_bis:1;
uint64_t data_bis:1;
uint64_t reserved_6_63:58;
#endif
} s;
struct cvmx_uctlx_bist_status_s cn63xx;
struct cvmx_uctlx_bist_status_s cn63xxp1;
struct cvmx_uctlx_bist_status_s cn61xx;
struct cvmx_uctlx_bist_status_s cn63xx;
struct cvmx_uctlx_bist_status_s cn63xxp1;
struct cvmx_uctlx_bist_status_s cn66xx;
struct cvmx_uctlx_bist_status_s cn68xx;
struct cvmx_uctlx_bist_status_s cn68xxp1;
struct cvmx_uctlx_bist_status_s cnf71xx;
};
union cvmx_uctlx_clk_rst_ctl {
uint64_t u64;
struct cvmx_uctlx_clk_rst_ctl_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_25_63:39;
uint64_t clear_bist:1;
uint64_t start_bist:1;
@ -81,14 +97,43 @@ union cvmx_uctlx_clk_rst_ctl {
uint64_t p_por:1;
uint64_t p_prst:1;
uint64_t hrst:1;
#else
uint64_t hrst:1;
uint64_t p_prst:1;
uint64_t p_por:1;
uint64_t p_com_on:1;
uint64_t reserved_4_4:1;
uint64_t p_refclk_div:2;
uint64_t p_refclk_sel:2;
uint64_t h_div:4;
uint64_t o_clkdiv_en:1;
uint64_t h_clkdiv_en:1;
uint64_t h_clkdiv_rst:1;
uint64_t h_clkdiv_byp:1;
uint64_t o_clkdiv_rst:1;
uint64_t app_start_clk:1;
uint64_t ohci_susp_lgcy:1;
uint64_t ohci_sm:1;
uint64_t ohci_clkcktrst:1;
uint64_t ehci_sm:1;
uint64_t start_bist:1;
uint64_t clear_bist:1;
uint64_t reserved_25_63:39;
#endif
} s;
struct cvmx_uctlx_clk_rst_ctl_s cn63xx;
struct cvmx_uctlx_clk_rst_ctl_s cn63xxp1;
struct cvmx_uctlx_clk_rst_ctl_s cn61xx;
struct cvmx_uctlx_clk_rst_ctl_s cn63xx;
struct cvmx_uctlx_clk_rst_ctl_s cn63xxp1;
struct cvmx_uctlx_clk_rst_ctl_s cn66xx;
struct cvmx_uctlx_clk_rst_ctl_s cn68xx;
struct cvmx_uctlx_clk_rst_ctl_s cn68xxp1;
struct cvmx_uctlx_clk_rst_ctl_s cnf71xx;
};
union cvmx_uctlx_ehci_ctl {
uint64_t u64;
struct cvmx_uctlx_ehci_ctl_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63:44;
uint64_t desc_rbm:1;
uint64_t reg_nb:1;
@ -101,45 +146,96 @@ union cvmx_uctlx_ehci_ctl {
uint64_t inv_reg_a2:1;
uint64_t ehci_64b_addr_en:1;
uint64_t l2c_addr_msb:8;
#else
uint64_t l2c_addr_msb:8;
uint64_t ehci_64b_addr_en:1;
uint64_t inv_reg_a2:1;
uint64_t l2c_desc_emod:2;
uint64_t l2c_buff_emod:2;
uint64_t l2c_stt:1;
uint64_t l2c_0pag:1;
uint64_t l2c_bc:1;
uint64_t l2c_dc:1;
uint64_t reg_nb:1;
uint64_t desc_rbm:1;
uint64_t reserved_20_63:44;
#endif
} s;
struct cvmx_uctlx_ehci_ctl_s cn63xx;
struct cvmx_uctlx_ehci_ctl_s cn63xxp1;
struct cvmx_uctlx_ehci_ctl_s cn61xx;
struct cvmx_uctlx_ehci_ctl_s cn63xx;
struct cvmx_uctlx_ehci_ctl_s cn63xxp1;
struct cvmx_uctlx_ehci_ctl_s cn66xx;
struct cvmx_uctlx_ehci_ctl_s cn68xx;
struct cvmx_uctlx_ehci_ctl_s cn68xxp1;
struct cvmx_uctlx_ehci_ctl_s cnf71xx;
};
union cvmx_uctlx_ehci_fla {
uint64_t u64;
struct cvmx_uctlx_ehci_fla_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_6_63:58;
uint64_t fla:6;
#else
uint64_t fla:6;
uint64_t reserved_6_63:58;
#endif
} s;
struct cvmx_uctlx_ehci_fla_s cn63xx;
struct cvmx_uctlx_ehci_fla_s cn63xxp1;
struct cvmx_uctlx_ehci_fla_s cn61xx;
struct cvmx_uctlx_ehci_fla_s cn63xx;
struct cvmx_uctlx_ehci_fla_s cn63xxp1;
struct cvmx_uctlx_ehci_fla_s cn66xx;
struct cvmx_uctlx_ehci_fla_s cn68xx;
struct cvmx_uctlx_ehci_fla_s cn68xxp1;
struct cvmx_uctlx_ehci_fla_s cnf71xx;
};
union cvmx_uctlx_erto_ctl {
uint64_t u64;
struct cvmx_uctlx_erto_ctl_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
uint64_t to_val:27;
uint64_t reserved_0_4:5;
#else
uint64_t reserved_0_4:5;
uint64_t to_val:27;
uint64_t reserved_32_63:32;
#endif
} s;
struct cvmx_uctlx_erto_ctl_s cn63xx;
struct cvmx_uctlx_erto_ctl_s cn63xxp1;
struct cvmx_uctlx_erto_ctl_s cn61xx;
struct cvmx_uctlx_erto_ctl_s cn63xx;
struct cvmx_uctlx_erto_ctl_s cn63xxp1;
struct cvmx_uctlx_erto_ctl_s cn66xx;
struct cvmx_uctlx_erto_ctl_s cn68xx;
struct cvmx_uctlx_erto_ctl_s cn68xxp1;
struct cvmx_uctlx_erto_ctl_s cnf71xx;
};
union cvmx_uctlx_if_ena {
uint64_t u64;
struct cvmx_uctlx_if_ena_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63:63;
uint64_t en:1;
#else
uint64_t en:1;
uint64_t reserved_1_63:63;
#endif
} s;
struct cvmx_uctlx_if_ena_s cn63xx;
struct cvmx_uctlx_if_ena_s cn63xxp1;
struct cvmx_uctlx_if_ena_s cn61xx;
struct cvmx_uctlx_if_ena_s cn63xx;
struct cvmx_uctlx_if_ena_s cn63xxp1;
struct cvmx_uctlx_if_ena_s cn66xx;
struct cvmx_uctlx_if_ena_s cn68xx;
struct cvmx_uctlx_if_ena_s cn68xxp1;
struct cvmx_uctlx_if_ena_s cnf71xx;
};
union cvmx_uctlx_int_ena {
uint64_t u64;
struct cvmx_uctlx_int_ena_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63:56;
uint64_t ec_ovf_e:1;
uint64_t oc_ovf_e:1;
@ -149,14 +245,31 @@ union cvmx_uctlx_int_ena {
uint64_t or_psh_f:1;
uint64_t er_psh_f:1;
uint64_t pp_psh_f:1;
#else
uint64_t pp_psh_f:1;
uint64_t er_psh_f:1;
uint64_t or_psh_f:1;
uint64_t cf_psh_f:1;
uint64_t wb_psh_f:1;
uint64_t wb_pop_e:1;
uint64_t oc_ovf_e:1;
uint64_t ec_ovf_e:1;
uint64_t reserved_8_63:56;
#endif
} s;
struct cvmx_uctlx_int_ena_s cn63xx;
struct cvmx_uctlx_int_ena_s cn63xxp1;
struct cvmx_uctlx_int_ena_s cn61xx;
struct cvmx_uctlx_int_ena_s cn63xx;
struct cvmx_uctlx_int_ena_s cn63xxp1;
struct cvmx_uctlx_int_ena_s cn66xx;
struct cvmx_uctlx_int_ena_s cn68xx;
struct cvmx_uctlx_int_ena_s cn68xxp1;
struct cvmx_uctlx_int_ena_s cnf71xx;
};
union cvmx_uctlx_int_reg {
uint64_t u64;
struct cvmx_uctlx_int_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63:56;
uint64_t ec_ovf_e:1;
uint64_t oc_ovf_e:1;
@ -166,14 +279,31 @@ union cvmx_uctlx_int_reg {
uint64_t or_psh_f:1;
uint64_t er_psh_f:1;
uint64_t pp_psh_f:1;
#else
uint64_t pp_psh_f:1;
uint64_t er_psh_f:1;
uint64_t or_psh_f:1;
uint64_t cf_psh_f:1;
uint64_t wb_psh_f:1;
uint64_t wb_pop_e:1;
uint64_t oc_ovf_e:1;
uint64_t ec_ovf_e:1;
uint64_t reserved_8_63:56;
#endif
} s;
struct cvmx_uctlx_int_reg_s cn63xx;
struct cvmx_uctlx_int_reg_s cn63xxp1;
struct cvmx_uctlx_int_reg_s cn61xx;
struct cvmx_uctlx_int_reg_s cn63xx;
struct cvmx_uctlx_int_reg_s cn63xxp1;
struct cvmx_uctlx_int_reg_s cn66xx;
struct cvmx_uctlx_int_reg_s cn68xx;
struct cvmx_uctlx_int_reg_s cn68xxp1;
struct cvmx_uctlx_int_reg_s cnf71xx;
};
union cvmx_uctlx_ohci_ctl {
uint64_t u64;
struct cvmx_uctlx_ohci_ctl_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_19_63:45;
uint64_t reg_nb:1;
uint64_t l2c_dc:1;
@ -185,35 +315,73 @@ union cvmx_uctlx_ohci_ctl {
uint64_t inv_reg_a2:1;
uint64_t reserved_8_8:1;
uint64_t l2c_addr_msb:8;
#else
uint64_t l2c_addr_msb:8;
uint64_t reserved_8_8:1;
uint64_t inv_reg_a2:1;
uint64_t l2c_desc_emod:2;
uint64_t l2c_buff_emod:2;
uint64_t l2c_stt:1;
uint64_t l2c_0pag:1;
uint64_t l2c_bc:1;
uint64_t l2c_dc:1;
uint64_t reg_nb:1;
uint64_t reserved_19_63:45;
#endif
} s;
struct cvmx_uctlx_ohci_ctl_s cn63xx;
struct cvmx_uctlx_ohci_ctl_s cn63xxp1;
struct cvmx_uctlx_ohci_ctl_s cn61xx;
struct cvmx_uctlx_ohci_ctl_s cn63xx;
struct cvmx_uctlx_ohci_ctl_s cn63xxp1;
struct cvmx_uctlx_ohci_ctl_s cn66xx;
struct cvmx_uctlx_ohci_ctl_s cn68xx;
struct cvmx_uctlx_ohci_ctl_s cn68xxp1;
struct cvmx_uctlx_ohci_ctl_s cnf71xx;
};
union cvmx_uctlx_orto_ctl {
uint64_t u64;
struct cvmx_uctlx_orto_ctl_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
uint64_t to_val:24;
uint64_t reserved_0_7:8;
#else
uint64_t reserved_0_7:8;
uint64_t to_val:24;
uint64_t reserved_32_63:32;
#endif
} s;
struct cvmx_uctlx_orto_ctl_s cn63xx;
struct cvmx_uctlx_orto_ctl_s cn63xxp1;
struct cvmx_uctlx_orto_ctl_s cn61xx;
struct cvmx_uctlx_orto_ctl_s cn63xx;
struct cvmx_uctlx_orto_ctl_s cn63xxp1;
struct cvmx_uctlx_orto_ctl_s cn66xx;
struct cvmx_uctlx_orto_ctl_s cn68xx;
struct cvmx_uctlx_orto_ctl_s cn68xxp1;
struct cvmx_uctlx_orto_ctl_s cnf71xx;
};
union cvmx_uctlx_ppaf_wm {
uint64_t u64;
struct cvmx_uctlx_ppaf_wm_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63:59;
uint64_t wm:5;
#else
uint64_t wm:5;
uint64_t reserved_5_63:59;
#endif
} s;
struct cvmx_uctlx_ppaf_wm_s cn63xx;
struct cvmx_uctlx_ppaf_wm_s cn63xxp1;
struct cvmx_uctlx_ppaf_wm_s cn61xx;
struct cvmx_uctlx_ppaf_wm_s cn63xx;
struct cvmx_uctlx_ppaf_wm_s cn63xxp1;
struct cvmx_uctlx_ppaf_wm_s cn66xx;
struct cvmx_uctlx_ppaf_wm_s cnf71xx;
};
union cvmx_uctlx_uphy_ctl_status {
uint64_t u64;
struct cvmx_uctlx_uphy_ctl_status_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_10_63:54;
uint64_t bist_done:1;
uint64_t bist_err:1;
@ -225,14 +393,33 @@ union cvmx_uctlx_uphy_ctl_status {
uint64_t uphy_bist:1;
uint64_t bist_en:1;
uint64_t ate_reset:1;
#else
uint64_t ate_reset:1;
uint64_t bist_en:1;
uint64_t uphy_bist:1;
uint64_t vtest_en:1;
uint64_t siddq:1;
uint64_t lsbist:1;
uint64_t fsbist:1;
uint64_t hsbist:1;
uint64_t bist_err:1;
uint64_t bist_done:1;
uint64_t reserved_10_63:54;
#endif
} s;
struct cvmx_uctlx_uphy_ctl_status_s cn63xx;
struct cvmx_uctlx_uphy_ctl_status_s cn63xxp1;
struct cvmx_uctlx_uphy_ctl_status_s cn61xx;
struct cvmx_uctlx_uphy_ctl_status_s cn63xx;
struct cvmx_uctlx_uphy_ctl_status_s cn63xxp1;
struct cvmx_uctlx_uphy_ctl_status_s cn66xx;
struct cvmx_uctlx_uphy_ctl_status_s cn68xx;
struct cvmx_uctlx_uphy_ctl_status_s cn68xxp1;
struct cvmx_uctlx_uphy_ctl_status_s cnf71xx;
};
union cvmx_uctlx_uphy_portx_ctl_status {
uint64_t u64;
struct cvmx_uctlx_uphy_portx_ctl_status_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_43_63:21;
uint64_t tdata_out:4;
uint64_t txbiststuffenh:1;
@ -253,9 +440,36 @@ union cvmx_uctlx_uphy_portx_ctl_status {
uint64_t tdata_sel:1;
uint64_t taddr_in:4;
uint64_t tdata_in:8;
#else
uint64_t tdata_in:8;
uint64_t taddr_in:4;
uint64_t tdata_sel:1;
uint64_t tclk:1;
uint64_t loop_en:1;
uint64_t compdistune:3;
uint64_t sqrxtune:3;
uint64_t txfslstune:4;
uint64_t txpreemphasistune:1;
uint64_t txrisetune:1;
uint64_t txvreftune:4;
uint64_t txhsvxtune:2;
uint64_t portreset:1;
uint64_t vbusvldext:1;
uint64_t dppulldown:1;
uint64_t dmpulldown:1;
uint64_t txbiststuffen:1;
uint64_t txbiststuffenh:1;
uint64_t tdata_out:4;
uint64_t reserved_43_63:21;
#endif
} s;
struct cvmx_uctlx_uphy_portx_ctl_status_s cn61xx;
struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xx;
struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xxp1;
struct cvmx_uctlx_uphy_portx_ctl_status_s cn66xx;
struct cvmx_uctlx_uphy_portx_ctl_status_s cn68xx;
struct cvmx_uctlx_uphy_portx_ctl_status_s cn68xxp1;
struct cvmx_uctlx_uphy_portx_ctl_status_s cnf71xx;
};
#endif