forked from Minki/linux
[ARM] pxa: add preliminary suspend/resume code for pxa3xx
1. clear RDH bit after resuming back from D3, otherwise, the multi function pins will retain the low power state 2. save/restore essential system registers Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
eric miao
Russell King
parent
16dfdbf038
commit
c4d1fb627f
@ -22,6 +22,7 @@
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#include <asm/hardware.h>
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#include <asm/arch/mfp.h>
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#include <asm/arch/mfp-pxa3xx.h>
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#include <asm/arch/pxa3xx-regs.h>
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/* mfp_spin_lock is used to ensure that MFP register configuration
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* (most likely a read-modify-write operation) is atomic, and that
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@ -223,6 +224,14 @@ static int pxa3xx_mfp_resume(struct sys_device *d)
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struct pxa3xx_mfp_pin *p = &mfp_table[pin];
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__mfp_config_run(p);
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}
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/* clear RDH bit when MFP settings are restored
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*
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* NOTE: the last 3 bits DxS are write-1-to-clear so carefully
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* preserve them here in case they will be referenced later
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*/
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ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
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return 0;
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}
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@ -40,6 +40,7 @@
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#define RO_CLK 60000000
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#define ACCR_D0CS (1 << 26)
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#define ACCR_PCCE (1 << 11)
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/* crystal frequency to static memory controller multiplier (SMCFS) */
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static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
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@ -204,7 +205,6 @@ static struct clk pxa3xx_clks[] = {
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};
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#ifdef CONFIG_PM
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#define SLEEP_SAVE_SIZE 4
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#define ISRAM_START 0x5c000000
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#define ISRAM_SIZE SZ_256K
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@ -212,25 +212,29 @@ static struct clk pxa3xx_clks[] = {
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static void __iomem *sram;
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static unsigned long wakeup_src;
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#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
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#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
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enum { SLEEP_SAVE_START = 0,
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SLEEP_SAVE_CKENA,
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SLEEP_SAVE_CKENB,
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SLEEP_SAVE_ACCR,
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SLEEP_SAVE_SIZE,
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};
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static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
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{
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pr_debug("PM: CKENA=%08x CKENB=%08x\n", CKENA, CKENB);
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if (CKENA & (1 << CKEN_USBH)) {
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printk(KERN_ERR "PM: USB host clock not stopped?\n");
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CKENA &= ~(1 << CKEN_USBH);
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}
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// CKENA |= 1 << (CKEN_ISC & 31);
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/*
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* Low power modes require the HSIO2 clock to be enabled.
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*/
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CKENB |= 1 << (CKEN_HSIO2 & 31);
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SAVE(CKENA);
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SAVE(CKENB);
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SAVE(ACCR);
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}
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static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
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{
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CKENB &= ~(1 << (CKEN_HSIO2 & 31));
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RESTORE(ACCR);
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RESTORE(CKENA);
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RESTORE(CKENB);
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}
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/*
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@ -266,6 +270,46 @@ static void pxa3xx_cpu_standby(unsigned int pwrmode)
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printk("PM: AD2D0SR=%08x ASCR=%08x\n", AD2D0SR, ASCR);
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}
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/*
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* NOTE: currently, the OBM (OEM Boot Module) binary comes along with
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* PXA3xx development kits assumes that the resuming process continues
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* with the address stored within the first 4 bytes of SDRAM. The PSPR
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* register is used privately by BootROM and OBM, and _must_ be set to
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* 0x5c014000 for the moment.
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*/
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static void pxa3xx_cpu_pm_suspend(void)
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{
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volatile unsigned long *p = (volatile void *)0xc0000000;
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unsigned long saved_data = *p;
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extern void pxa3xx_cpu_suspend(void);
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extern void pxa3xx_cpu_resume(void);
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/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
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CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
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CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
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/* clear and setup wakeup source */
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AD3SR = ~0;
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AD3ER = wakeup_src;
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ASCR = ASCR;
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ARSR = ARSR;
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PCFR |= (1u << 13); /* L1_DIS */
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PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */
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PSPR = 0x5c014000;
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/* overwrite with the resume address */
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*p = virt_to_phys(pxa3xx_cpu_resume);
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pxa3xx_cpu_suspend();
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*p = saved_data;
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AD3ER = 0;
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}
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static void pxa3xx_cpu_pm_enter(suspend_state_t state)
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{
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/*
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@ -280,6 +324,7 @@ static void pxa3xx_cpu_pm_enter(suspend_state_t state)
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break;
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case PM_SUSPEND_MEM:
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pxa3xx_cpu_pm_suspend();
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break;
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}
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}
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@ -50,6 +50,108 @@ pxa_cpu_save_sp:
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str r0, [r1]
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ldr pc, [sp], #4
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#ifdef CONFIG_PXA3xx
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/*
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* pxa3xx_cpu_suspend() - forces CPU into sleep state (S2D3C4)
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*
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* NOTE: unfortunately, pxa_cpu_save_cp can not be reused here since
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* the auxiliary control register address is different between pxa3xx
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* and pxa{25x,27x}
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*/
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ENTRY(pxa3xx_cpu_suspend)
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#ifndef CONFIG_IWMMXT
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mra r2, r3, acc0
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#endif
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stmfd sp!, {r2 - r12, lr} @ save registers on stack
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mrc p14, 0, r3, c6, c0, 0 @ clock configuration, for turbo mode
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mrc p15, 0, r4, c15, c1, 0 @ CP access reg
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mrc p15, 0, r5, c13, c0, 0 @ PID
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mrc p15, 0, r6, c3, c0, 0 @ domain ID
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mrc p15, 0, r7, c2, c0, 0 @ translation table base addr
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mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
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mrc p15, 0, r9, c1, c0, 0 @ control reg
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bic r3, r3, #2 @ clear frequency change bit
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@ store them plus current virtual stack ptr on stack
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mov r10, sp
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stmfd sp!, {r3 - r10}
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@ store physical address of stack pointer
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mov r0, sp
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bl sleep_phys_sp
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ldr r1, =sleep_save_sp
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str r0, [r1]
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@ clean data cache
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bl xsc3_flush_kern_cache_all
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mov r0, #0x06 @ S2D3C4 mode
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mcr p14, 0, r0, c7, c0, 0 @ enter sleep
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20: b 20b @ waiting for sleep
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.data
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.align 5
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/*
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* pxa3xx_cpu_resume
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*/
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ENTRY(pxa3xx_cpu_resume)
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mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE @ set SVC, irqs off
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msr cpsr_c, r0
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ldr r0, sleep_save_sp @ stack phys addr
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ldmfd r0, {r3 - r9, sp} @ CP regs + virt stack ptr
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mov r1, #0
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mcr p15, 0, r1, c7, c7, 0 @ invalidate I & D caches, BTB
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mcr p15, 0, r1, c7, c10, 4 @ drain write (&fill) buffer
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mcr p15, 0, r1, c7, c5, 4 @ flush prefetch buffer
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mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
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mcr p14, 0, r3, c6, c0, 0 @ clock configuration, turbo mode.
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mcr p15, 0, r4, c15, c1, 0 @ CP access reg
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mcr p15, 0, r5, c13, c0, 0 @ PID
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mcr p15, 0, r6, c3, c0, 0 @ domain ID
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mcr p15, 0, r7, c2, c0, 0 @ translation table base addr
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mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
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@ temporarily map resume_turn_on_mmu into the page table,
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@ otherwise prefetch abort occurs after MMU is turned on
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mov r1, r7
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bic r1, r1, #0x00ff
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bic r1, r1, #0x3f00
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ldr r2, =0x542e
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adr r3, resume_turn_on_mmu
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mov r3, r3, lsr #20
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orr r4, r2, r3, lsl #20
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ldr r5, [r1, r3, lsl #2]
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str r4, [r1, r3, lsl #2]
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@ Mapping page table address in the page table
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mov r6, r1, lsr #20
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orr r7, r2, r6, lsl #20
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ldr r8, [r1, r6, lsl #2]
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str r7, [r1, r6, lsl #2]
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ldr r2, =pxa3xx_resume_after_mmu @ absolute virtual address
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b resume_turn_on_mmu @ cache align execution
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.text
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pxa3xx_resume_after_mmu:
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/* restore the temporary mapping */
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str r5, [r1, r3, lsl #2]
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str r8, [r1, r6, lsl #2]
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b resume_after_mmu
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#endif /* CONFIG_PXA3xx */
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#ifdef CONFIG_PXA27x
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/*
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* pxa27x_cpu_suspend()
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@ -12,6 +12,19 @@
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#ifndef __ASM_ARCH_PXA3XX_REGS_H
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#define __ASM_ARCH_PXA3XX_REGS_H
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/*
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* Service Power Management Unit (MPMU)
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*/
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#define PMCR __REG(0x40F50000) /* Power Manager Control Register */
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#define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */
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#define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */
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#define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */
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#define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */
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#define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */
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#define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */
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#define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */
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#define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */
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#define PCMD(x) __REG(0x40F50110 + ((x) << 2))
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/*
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* Slave Power Managment Unit
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