forked from Minki/linux
Memory controller drivers for v6.1 - MediaTek
Add support for the mt8188 SMI memory controller. -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmMbWgUQHGtyemtAa2Vy bmVsLm9yZwAKCRDBN2bmhouD19CoD/0X2+d8EZymIdiLjRy1REtVVHbhvBuCepVp ZSDHgwIFY/qNuzQwYfqamwXAzUXdJM0ihPB+JO7AaU76oT+g9yToJaJQi4KbiAU6 A85HzTNFrQJiFlw6JOxoAN8uXcmF49sFzUlTe/X8YP+fQ+mn/T6/W2eupv9s3x6n zd5F3u/ECg+0BmGVJfqJdDtri1hzp8m/BREHOZdBJR1ZS+39lL/sSDn1yeQ8X9to MttIXwZV5kQHfWUEqewXWJCfcGCKPwg/+4XeZ49X8gbubBDRbGzZTCnsn3Ddni7x Xd12kZ2cLPjZrua3/QNiVmiazD2GAjR2pUXvDa//C66niXihPC6QnRkosl7tz9ak z8cgFv1FtUiOfY5W4SX7bWrVNyC1Pi581k+vOBwjcdkRTWHRRVSwxH+kTFbPzSVZ OrTG9YTTJhYWlwnxL/R8P+aqa1LD57D5uDB7lSH/QTAWZyp3jnbgIbjbMFs43DJ4 tn1F/Gbutoq6b1cXrtk50OML2moCpLbXRV3N/Jsqg7Mk7pSMXNBXzR7dNRxtomcx dyHsh30EzNbOcZg5VIlmDjrN/Wd5rkt1ArY0R3XO4UpA2XeCye6IQmY1+VBqzBtY 9PwsDFBDl4MIvsVy3z8jk4IjxlKZo4j3W87s7bGT5OaKcSEL/Q+2519oYadDEVJu e3B440yz0g== =KlXR -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmMfSm8ACgkQmmx57+YA GNkRsA/+M+3UrgZbN0OxA8BADhjYBbi4Ff2nUhDJPd0WdjypNwOsERP9gssSkK2M t6njFcInnQeHfjvRVhjVrzJz3zIwXJZvyZm75+/4ceu2oLzcN9QsXZCVAw1S8L5t 95sHRCKlC7HHre5pwwXPuXVKf9MdAhLGAxeVMzffntJ3z22pNve1az2gpXxiGzLZ Yb2mke2nlkg1D6t9UL9OORO2+XDFFoaoed9LTmgbKYC8Tn5igsxuqbPaVQ2/gn2M 5Y8ym9T/yGmjAuqXX3jKVNBoGVgWbi5rpjaJEwRkYtSIO72qr+sipuVmsr7ZErN/ dJKfXo0pK6rgB7P8mdc9k9idkqCY5euRCUvsvrQKF0WMJ6coMD05aVsDtI5xvrg4 aAWVAZVzrkQ2js1nVG0ERUQKTaOvp8et1v2pJS3n1P0zqRDxqoDBmyCiBEY625Wx fiJW9ZYoTHuQu2tElY6SaR1aMvOLI/GKiXt2qW5jUtlQYn6yEvc4ggMG1WuHgT2i cegCHD/XB/tbBsA1J4ibxmn4n+cdQ5BiGaQsTnBuQ07P1sykyCrXvNcJ5jqt+OAH ZFl3BRbWM2jY//E8LpXqEcbrBm7fF9D2R3Rv3a09PJgeU7NFeouZKlnHNP20atHa g1tKjWyUH6ef6wB2WCNwnj8f5P1EuAh/S65GL9woxDVQWDKiP70= =phpc -----END PGP SIGNATURE----- Merge tag 'memory-controller-drv-mediatek-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers Memory controller drivers for v6.1 - MediaTek Add support for the mt8188 SMI memory controller. * tag 'memory-controller-drv-mediatek-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl: memory: mtk-smi: mt8188: Add SMI Support memory: mtk-smi: Add enable IOMMU SMC command for MM master memory: mtk-smi: Add return value for configure port function dt-bindings: memory: mediatek: Add mt8188 smi binding Link: https://lore.kernel.org/r/20220909153037.824092-4-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
c457d9a580
@ -16,7 +16,7 @@ description: |
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MediaTek SMI have two generations of HW architecture, here is the list
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which generation the SoCs use:
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generation 1: mt2701 and mt7623.
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generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8186, mt8192 and mt8195.
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generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8186, mt8188, mt8192 and mt8195.
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There's slight differences between the two SMI, for generation 2, the
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register which control the iommu port is at each larb's register base. But
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@ -37,6 +37,8 @@ properties:
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- mediatek,mt8173-smi-common
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- mediatek,mt8183-smi-common
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- mediatek,mt8186-smi-common
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- mediatek,mt8188-smi-common-vdo
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- mediatek,mt8188-smi-common-vpp
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- mediatek,mt8192-smi-common
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- mediatek,mt8195-smi-common-vdo
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- mediatek,mt8195-smi-common-vpp
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@ -25,6 +25,7 @@ properties:
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- mediatek,mt8173-smi-larb
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- mediatek,mt8183-smi-larb
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- mediatek,mt8186-smi-larb
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- mediatek,mt8188-smi-larb
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- mediatek,mt8192-smi-larb
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- mediatek,mt8195-smi-larb
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@ -78,6 +79,7 @@ allOf:
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enum:
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- mediatek,mt8183-smi-larb
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- mediatek,mt8186-smi-larb
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- mediatek,mt8188-smi-larb
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- mediatek,mt8195-smi-larb
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then:
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@ -111,6 +113,7 @@ allOf:
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- mediatek,mt2712-smi-larb
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- mediatek,mt6779-smi-larb
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- mediatek,mt8186-smi-larb
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- mediatek,mt8188-smi-larb
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- mediatek,mt8192-smi-larb
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- mediatek,mt8195-smi-larb
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@ -3,6 +3,7 @@
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* Copyright (c) 2015-2016 MediaTek Inc.
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* Author: Yong Wu <yong.wu@mediatek.com>
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*/
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#include <linux/arm-smccc.h>
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/device.h>
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@ -14,6 +15,7 @@
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/soc/mediatek/mtk_sip_svc.h>
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#include <soc/mediatek/smi.h>
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#include <dt-bindings/memory/mt2701-larb-port.h>
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#include <dt-bindings/memory/mtk-memory-port.h>
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@ -89,6 +91,7 @@
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#define MTK_SMI_FLAG_THRT_UPDATE BIT(0)
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#define MTK_SMI_FLAG_SW_FLAG BIT(1)
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#define MTK_SMI_FLAG_SLEEP_CTL BIT(2)
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#define MTK_SMI_FLAG_CFG_PORT_SEC_CTL BIT(3)
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#define MTK_SMI_CAPS(flags, _x) (!!((flags) & (_x)))
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struct mtk_smi_reg_pair {
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@ -127,7 +130,7 @@ struct mtk_smi_common_plat {
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struct mtk_smi_larb_gen {
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int port_in_larb[MTK_LARB_NR_MAX + 1];
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void (*config_port)(struct device *dev);
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int (*config_port)(struct device *dev);
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unsigned int larb_direct_to_common_mask;
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unsigned int flags_general;
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const u8 (*ostd)[SMI_LARB_PORT_NR_MAX];
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@ -185,7 +188,7 @@ static const struct component_ops mtk_smi_larb_component_ops = {
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.unbind = mtk_smi_larb_unbind,
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};
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static void mtk_smi_larb_config_port_gen1(struct device *dev)
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static int mtk_smi_larb_config_port_gen1(struct device *dev)
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{
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struct mtk_smi_larb *larb = dev_get_drvdata(dev);
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const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
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@ -214,31 +217,35 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev)
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common->smi_ao_base
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+ REG_SMI_SECUR_CON_ADDR(m4u_port_id));
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}
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return 0;
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}
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static void mtk_smi_larb_config_port_mt8167(struct device *dev)
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static int mtk_smi_larb_config_port_mt8167(struct device *dev)
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{
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struct mtk_smi_larb *larb = dev_get_drvdata(dev);
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writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN);
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return 0;
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}
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static void mtk_smi_larb_config_port_mt8173(struct device *dev)
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static int mtk_smi_larb_config_port_mt8173(struct device *dev)
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{
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struct mtk_smi_larb *larb = dev_get_drvdata(dev);
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writel(*larb->mmu, larb->base + MT8173_SMI_LARB_MMU_EN);
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return 0;
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}
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static void mtk_smi_larb_config_port_gen2_general(struct device *dev)
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static int mtk_smi_larb_config_port_gen2_general(struct device *dev)
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{
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struct mtk_smi_larb *larb = dev_get_drvdata(dev);
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u32 reg, flags_general = larb->larb_gen->flags_general;
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const u8 *larbostd = larb->larb_gen->ostd ? larb->larb_gen->ostd[larb->larbid] : NULL;
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struct arm_smccc_res res;
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int i;
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if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask)
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return;
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return 0;
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if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_THRT_UPDATE)) {
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reg = readl_relaxed(larb->base + SMI_LARB_CMD_THRT_CON);
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@ -253,14 +260,78 @@ static void mtk_smi_larb_config_port_gen2_general(struct device *dev)
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for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++)
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writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i));
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/*
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* When mmu_en bits are in security world, the bank_sel still is in the
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* LARB_NONSEC_CON below. And the mmu_en bits of LARB_NONSEC_CON have no
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* effect in this case.
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*/
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if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_CFG_PORT_SEC_CTL)) {
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arm_smccc_smc(MTK_SIP_KERNEL_IOMMU_CONTROL, IOMMU_ATF_CMD_CONFIG_SMI_LARB,
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larb->larbid, *larb->mmu, 0, 0, 0, 0, &res);
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if (res.a0 != 0) {
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dev_err(dev, "Enable iommu fail, ret %ld\n", res.a0);
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return -EINVAL;
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}
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}
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for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
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reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));
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reg |= F_MMU_EN;
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reg |= BANK_SEL(larb->bank[i]);
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writel(reg, larb->base + SMI_LARB_NONSEC_CON(i));
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}
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return 0;
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}
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static const u8 mtk_smi_larb_mt8188_ostd[][SMI_LARB_PORT_NR_MAX] = {
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[0] = {0x02, 0x18, 0x22, 0x22, 0x01, 0x02, 0x0a,},
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[1] = {0x12, 0x02, 0x14, 0x14, 0x01, 0x18, 0x0a,},
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[2] = {0x12, 0x12, 0x12, 0x12, 0x0a,},
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[3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,},
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[4] = {0x06, 0x01, 0x17, 0x06, 0x0a, 0x07, 0x07,},
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[5] = {0x02, 0x01, 0x04, 0x02, 0x06, 0x01, 0x06, 0x0a,},
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[6] = {0x06, 0x01, 0x06, 0x0a,},
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[7] = {0x0c, 0x0c, 0x12,},
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[8] = {0x0c, 0x01, 0x0a, 0x05, 0x02, 0x03, 0x01, 0x01, 0x14, 0x14,
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0x0a, 0x14, 0x1e, 0x01, 0x0c, 0x0a, 0x05, 0x02, 0x02, 0x05,
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0x03, 0x01, 0x1e, 0x01, 0x05,},
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[9] = {0x1e, 0x01, 0x0a, 0x0a, 0x01, 0x01, 0x03, 0x1e, 0x1e, 0x10,
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0x07, 0x01, 0x0a, 0x06, 0x03, 0x03, 0x0e, 0x01, 0x04, 0x28,},
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[10] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c,
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0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14,
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0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,},
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[11] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c,
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0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14,
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0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,},
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[12] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c,
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0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14,
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0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,},
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[13] = {0x07, 0x02, 0x04, 0x02, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05,
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0x07, 0x02, 0x04, 0x02, 0x05, 0x05,},
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[14] = {0x02, 0x02, 0x0c, 0x0c, 0x0c, 0x0c, 0x01, 0x01, 0x02, 0x02,
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0x02, 0x02, 0x0c, 0x0c, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
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0x02, 0x02, 0x01, 0x01,},
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[15] = {0x0c, 0x0c, 0x02, 0x02, 0x02, 0x02, 0x01, 0x01, 0x0c, 0x0c,
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0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x01, 0x02,
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0x0c, 0x01, 0x01,},
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[16] = {0x28, 0x28, 0x03, 0x01, 0x01, 0x03, 0x14, 0x14, 0x0a, 0x0d,
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0x03, 0x05, 0x0e, 0x01, 0x01, 0x05, 0x06, 0x0d, 0x01,},
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[17] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a,
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0x12, 0x02, 0x02, 0x0a, 0x16, 0x02, 0x04,},
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[18] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a,
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0x12, 0x02, 0x02, 0x0a, 0x16, 0x02, 0x04,},
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[19] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
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[20] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
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[21] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01,
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0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06,
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0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,},
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[22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,
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0x01,},
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[23] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x18, 0x01, 0x01,},
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[24] = {0x12, 0x06, 0x12, 0x06,},
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[25] = {0x01},
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};
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static const u8 mtk_smi_larb_mt8195_ostd[][SMI_LARB_PORT_NR_MAX] = {
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[0] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb0 */
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[1] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb1 */
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@ -347,6 +418,13 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt8186 = {
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.flags_general = MTK_SMI_FLAG_SLEEP_CTL,
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};
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static const struct mtk_smi_larb_gen mtk_smi_larb_mt8188 = {
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.config_port = mtk_smi_larb_config_port_gen2_general,
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.flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG |
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MTK_SMI_FLAG_SLEEP_CTL | MTK_SMI_FLAG_CFG_PORT_SEC_CTL,
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.ostd = mtk_smi_larb_mt8188_ostd,
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};
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static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = {
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.config_port = mtk_smi_larb_config_port_gen2_general,
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};
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@ -367,6 +445,7 @@ static const struct of_device_id mtk_smi_larb_of_ids[] = {
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{.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173},
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{.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183},
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{.compatible = "mediatek,mt8186-smi-larb", .data = &mtk_smi_larb_mt8186},
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{.compatible = "mediatek,mt8188-smi-larb", .data = &mtk_smi_larb_mt8188},
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{.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192},
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{.compatible = "mediatek,mt8195-smi-larb", .data = &mtk_smi_larb_mt8195},
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{}
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@ -511,9 +590,7 @@ static int __maybe_unused mtk_smi_larb_resume(struct device *dev)
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mtk_smi_larb_sleep_ctrl_disable(larb);
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/* Configure the basic setting for this larb */
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larb_gen->config_port(dev);
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return 0;
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return larb_gen->config_port(dev);
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}
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static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
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@ -597,6 +674,18 @@ static const struct mtk_smi_common_plat mtk_smi_common_mt8186 = {
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.bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(4) | F_MMU1_LARB(7),
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};
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static const struct mtk_smi_common_plat mtk_smi_common_mt8188_vdo = {
|
||||
.type = MTK_SMI_GEN2,
|
||||
.bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(5) | F_MMU1_LARB(7),
|
||||
.init = mtk_smi_common_mt8195_init,
|
||||
};
|
||||
|
||||
static const struct mtk_smi_common_plat mtk_smi_common_mt8188_vpp = {
|
||||
.type = MTK_SMI_GEN2,
|
||||
.bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7),
|
||||
.init = mtk_smi_common_mt8195_init,
|
||||
};
|
||||
|
||||
static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = {
|
||||
.type = MTK_SMI_GEN2,
|
||||
.has_gals = true,
|
||||
@ -633,6 +722,8 @@ static const struct of_device_id mtk_smi_common_of_ids[] = {
|
||||
{.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2},
|
||||
{.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183},
|
||||
{.compatible = "mediatek,mt8186-smi-common", .data = &mtk_smi_common_mt8186},
|
||||
{.compatible = "mediatek,mt8188-smi-common-vdo", .data = &mtk_smi_common_mt8188_vdo},
|
||||
{.compatible = "mediatek,mt8188-smi-common-vpp", .data = &mtk_smi_common_mt8188_vpp},
|
||||
{.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192},
|
||||
{.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo},
|
||||
{.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp},
|
||||
|
||||
@ -22,4 +22,7 @@
|
||||
ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, MTK_SIP_SMC_CONVENTION, \
|
||||
ARM_SMCCC_OWNER_SIP, fn_id)
|
||||
|
||||
/* IOMMU related SMC call */
|
||||
#define MTK_SIP_KERNEL_IOMMU_CONTROL MTK_SIP_SMC_CMD(0x514)
|
||||
|
||||
#endif
|
||||
|
||||
@ -11,6 +11,11 @@
|
||||
|
||||
#if IS_ENABLED(CONFIG_MTK_SMI)
|
||||
|
||||
enum iommu_atf_cmd {
|
||||
IOMMU_ATF_CMD_CONFIG_SMI_LARB, /* For mm master to en/disable iommu */
|
||||
IOMMU_ATF_CMD_MAX,
|
||||
};
|
||||
|
||||
#define MTK_SMI_MMU_EN(port) BIT(port)
|
||||
|
||||
struct mtk_smi_larb_iommu {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user