drm/amd/powerplay: fix wrong clock adjust sequence
The clocks should be adjusted after display configuration changed. Otherwise, the socclk and memclk may be forced on an unnecessary higher level. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -265,19 +265,18 @@ int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip,
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if (skip)
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return 0;
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if (!hwmgr->ps)
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/*
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* for vega12/vega20 which does not support power state manager
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* DAL clock limits should also be honoured
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*/
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phm_apply_clock_adjust_rules(hwmgr);
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phm_pre_display_configuration_changed(hwmgr);
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phm_display_configuration_changed(hwmgr);
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if (hwmgr->ps)
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power_state_management(hwmgr, new_ps);
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else
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/*
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* for vega12/vega20 which does not support power state manager
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* DAL clock limits should also be honoured
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*/
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phm_apply_clock_adjust_rules(hwmgr);
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phm_notify_smc_display_config_after_ps_adjustment(hwmgr);
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