leandrof/linux
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

iw_cxgb4: Use memset_startat() for cpl_t5_pass_accept_rpl

Browse Source 
In preparation for FORTIFY_SOURCE performing compile-time and run-time
field bounds checking for memset(), avoid intentionally writing across
neighboring fields.

Use memset_startat() so memset() doesn't get confused about writing beyond
the destination member that is intended to be the starting point of
zeroing through the end of the struct. Additionally, since everything
appears to perform a roundup (including allocation), just change the size
of the struct itself and add a build-time check to validate the expected
size.

Link: https://lore.kernel.org/r/20211213223331.135412-13-keescook@chromium.org
Signed-off-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
This commit is contained in:
Kees Cook 2021-12-13 14:33:26 -08:00 committed by Jason Gunthorpe
parent e517f76a3c
commit c2ed5611af
2 changed files with 4 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/infiniband/hw/cxgb4/cm.c
View File

@ -2471,7 +2471,8 @@ static int accept_cr(struct c4iw_ep *ep, struct sk_buff *skb,
skb_get(skb); skb_get(skb);
rpl = cplhdr(skb); rpl = cplhdr(skb);
if (!is_t4(adapter_type)) { if (!is_t4(adapter_type)) {
skb_trim(skb, roundup(sizeof(*rpl5), 16)); BUILD_BUG_ON(sizeof(*rpl5) != roundup(sizeof(*rpl5), 16));
skb_trim(skb, sizeof(*rpl5));
rpl5 = (void *)rpl; rpl5 = (void *)rpl;
INIT_TP_WR(rpl5, ep->hwtid); INIT_TP_WR(rpl5, ep->hwtid);
} else { } else {
@ -2487,7 +2488,7 @@ static int accept_cr(struct c4iw_ep *ep, struct sk_buff *skb,
opt2 |= CONG_CNTRL_V(CONG_ALG_TAHOE); opt2 |= CONG_CNTRL_V(CONG_ALG_TAHOE);
opt2 |= T5_ISS_F; opt2 |= T5_ISS_F;
rpl5 = (void *)rpl; rpl5 = (void *)rpl;
memset(&rpl5->iss, 0, roundup(sizeof(*rpl5)-sizeof(*rpl), 16)); memset_after(rpl5, 0, iss);
if (peer2peer) if (peer2peer)
isn += 4; isn += 4;
rpl5->iss = cpu_to_be32(isn); rpl5->iss = cpu_to_be32(isn);

2
drivers/net/ethernet/chelsio/cxgb4/t4_msg.h
View File

@ -497,7 +497,7 @@ struct cpl_t5_pass_accept_rpl {
__be32 opt2; __be32 opt2;
__be64 opt0; __be64 opt0;
__be32 iss; __be32 iss;
__be32 rsvd; __be32 rsvd[3];
}; };
struct cpl_act_open_req { struct cpl_act_open_req {