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drm/nouveau/disp/nv50-: simplify definition of overlay immediate channels

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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2018-05-08 20:39:46 +10:00
parent 46f74a8ad7
commit c2c3a00310
21 changed files with 52 additions and 183 deletions
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3
drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild
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@ -111,8 +111,5 @@ nvkm-y += nvkm/engine/disp/cursgk104.o
nvkm-y += nvkm/engine/disp/cursgp102.o nvkm-y += nvkm/engine/disp/cursgp102.o
nvkm-y += nvkm/engine/disp/oimmnv50.o nvkm-y += nvkm/engine/disp/oimmnv50.o
nvkm-y += nvkm/engine/disp/oimmg84.o
nvkm-y += nvkm/engine/disp/oimmgt215.o
nvkm-y += nvkm/engine/disp/oimmgf119.o nvkm-y += nvkm/engine/disp/oimmgf119.o
nvkm-y += nvkm/engine/disp/oimmgk104.o
nvkm-y += nvkm/engine/disp/oimmgp102.o nvkm-y += nvkm/engine/disp/oimmgp102.o

21
drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h
View File

@ -50,12 +50,18 @@ void nv50_disp_chan_uevent_send(struct nv50_disp *, int);
extern const struct nvkm_event_func gf119_disp_chan_uevent; extern const struct nvkm_event_func gf119_disp_chan_uevent;
int nv50_disp_oimm_new_(const struct nv50_disp_chan_func *,
struct nv50_disp *, int ctrl, int user,
const struct nvkm_oclass *, void *argv, u32 argc,
struct nvkm_object **);
int nv50_disp_ovly_new_(const struct nv50_disp_dmac_func *, int nv50_disp_ovly_new_(const struct nv50_disp_dmac_func *,
const struct nv50_disp_chan_mthd *, const struct nv50_disp_chan_mthd *,
struct nv50_disp *, int chid, struct nv50_disp *, int chid,
const struct nvkm_oclass *, void *argv, u32 argc, const struct nvkm_oclass *, void *argv, u32 argc,
struct nvkm_object **); struct nvkm_object **);
int nv50_disp_oimm_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
int nv50_disp_ovly_new(const struct nvkm_oclass *, void *, u32, int nv50_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **); struct nv50_disp *, struct nvkm_object **);
@ -65,12 +71,16 @@ int g84_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
int gt200_disp_ovly_new(const struct nvkm_oclass *, void *, u32, int gt200_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **); struct nv50_disp *, struct nvkm_object **);
int gf119_disp_oimm_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
int gf119_disp_ovly_new(const struct nvkm_oclass *, void *, u32, int gf119_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **); struct nv50_disp *, struct nvkm_object **);
int gk104_disp_ovly_new(const struct nvkm_oclass *, void *, u32, int gk104_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **); struct nv50_disp *, struct nvkm_object **);
int gp102_disp_oimm_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
int gp102_disp_ovly_new(const struct nvkm_oclass *, void *, u32, int gp102_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **); struct nv50_disp *, struct nvkm_object **);
@ -133,22 +143,16 @@ struct nv50_disp_pioc_oclass {
} chid; } chid;
}; };
extern const struct nv50_disp_pioc_oclass nv50_disp_oimm_oclass;
extern const struct nv50_disp_pioc_oclass nv50_disp_curs_oclass; extern const struct nv50_disp_pioc_oclass nv50_disp_curs_oclass;
extern const struct nv50_disp_pioc_oclass g84_disp_oimm_oclass;
extern const struct nv50_disp_pioc_oclass g84_disp_curs_oclass; extern const struct nv50_disp_pioc_oclass g84_disp_curs_oclass;
extern const struct nv50_disp_pioc_oclass gt215_disp_oimm_oclass;
extern const struct nv50_disp_pioc_oclass gt215_disp_curs_oclass; extern const struct nv50_disp_pioc_oclass gt215_disp_curs_oclass;
extern const struct nv50_disp_pioc_oclass gf119_disp_oimm_oclass;
extern const struct nv50_disp_pioc_oclass gf119_disp_curs_oclass; extern const struct nv50_disp_pioc_oclass gf119_disp_curs_oclass;
extern const struct nv50_disp_pioc_oclass gk104_disp_oimm_oclass;
extern const struct nv50_disp_pioc_oclass gk104_disp_curs_oclass; extern const struct nv50_disp_pioc_oclass gk104_disp_curs_oclass;
extern const struct nv50_disp_pioc_oclass gp102_disp_oimm_oclass;
extern const struct nv50_disp_pioc_oclass gp102_disp_curs_oclass; extern const struct nv50_disp_pioc_oclass gp102_disp_curs_oclass;
int nv50_disp_curs_new(const struct nv50_disp_chan_func *, int nv50_disp_curs_new(const struct nv50_disp_chan_func *,
@ -156,9 +160,4 @@ int nv50_disp_curs_new(const struct nv50_disp_chan_func *,
struct nv50_disp_root *, int ctrl, int user, struct nv50_disp_root *, int ctrl, int user,
const struct nvkm_oclass *, void *data, u32 size, const struct nvkm_oclass *, void *data, u32 size,
struct nvkm_object **); struct nvkm_object **);
int nv50_disp_oimm_new(const struct nv50_disp_chan_func *,
const struct nv50_disp_chan_mthd *,
struct nv50_disp_root *, int ctrl, int user,
const struct nvkm_oclass *, void *data, u32 size,
struct nvkm_object **);
#endif #endif

37
drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmg84.c
View File

@ -1,37 +0,0 @@
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "channv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_pioc_oclass
g84_disp_oimm_oclass = {
.base.oclass = G82_DISP_OVERLAY,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_oimm_new,
.func = &nv50_disp_pioc_func,
.chid = { 5, 5 },
};

19
drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmgf119.c
View File

@ -22,16 +22,11 @@
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#include "channv50.h" #include "channv50.h"
#include "rootnv50.h"
#include <nvif/class.h> int
gf119_disp_oimm_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
const struct nv50_disp_pioc_oclass struct nv50_disp *disp, struct nvkm_object **pobject)
gf119_disp_oimm_oclass = { {
.base.oclass = GF110_DISP_OVERLAY, return nv50_disp_oimm_new_(&gf119_disp_pioc_func, disp, 9, 9,
.base.minver = 0, oclass, argv, argc, pobject);
.base.maxver = 0, }
.ctor = nv50_disp_oimm_new,
.func = &gf119_disp_pioc_func,
.chid = { 9, 9 },
};

37
drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmgk104.c
View File

@ -1,37 +0,0 @@
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "channv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_pioc_oclass
gk104_disp_oimm_oclass = {
.base.oclass = GK104_DISP_OVERLAY,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_oimm_new,
.func = &gf119_disp_pioc_func,
.chid = { 9, 9 },
};

19
drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmgp102.c
View File

@ -22,16 +22,11 @@
* Authors: Ben Skeggs <bskeggs@redhat.com> * Authors: Ben Skeggs <bskeggs@redhat.com>
*/ */
#include "channv50.h" #include "channv50.h"
#include "rootnv50.h"
#include <nvif/class.h> int
gp102_disp_oimm_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
const struct nv50_disp_pioc_oclass struct nv50_disp *disp, struct nvkm_object **pobject)
gp102_disp_oimm_oclass = { {
.base.oclass = GK104_DISP_OVERLAY, return nv50_disp_oimm_new_(&gf119_disp_pioc_func, disp, 9, 13,
.base.minver = 0, oclass, argv, argc, pobject);
.base.maxver = 0, }
.ctor = nv50_disp_oimm_new,
.func = &gf119_disp_pioc_func,
.chid = { 9, 13 },
};

37
drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmgt215.c
View File

@ -1,37 +0,0 @@
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "channv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_pioc_oclass
gt215_disp_oimm_oclass = {
.base.oclass = GT214_DISP_OVERLAY,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_oimm_new,
.func = &nv50_disp_pioc_func,
.chid = { 5, 5 },
};

34
drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c
View File

@ -23,30 +23,26 @@
*/ */
#include "channv50.h" #include "channv50.h"
#include "head.h" #include "head.h"
#include "rootnv50.h"
#include <core/client.h> #include <core/client.h>
#include <nvif/class.h>
#include <nvif/cl507b.h> #include <nvif/cl507b.h>
#include <nvif/unpack.h> #include <nvif/unpack.h>
int int
nv50_disp_oimm_new(const struct nv50_disp_chan_func *func, nv50_disp_oimm_new_(const struct nv50_disp_chan_func *func,
const struct nv50_disp_chan_mthd *mthd, struct nv50_disp *disp, int ctrl, int user,
struct nv50_disp_root *root, int ctrl, int user, const struct nvkm_oclass *oclass, void *argv, u32 argc,
const struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject) struct nvkm_object **pobject)
{ {
union { union {
struct nv50_disp_overlay_v0 v0; struct nv50_disp_overlay_v0 v0;
} *args = data; } *args = argv;
struct nvkm_object *parent = oclass->parent; struct nvkm_object *parent = oclass->parent;
struct nv50_disp *disp = root->disp;
int head, ret = -ENOSYS; int head, ret = -ENOSYS;
nvif_ioctl(parent, "create disp overlay size %d\n", size); nvif_ioctl(parent, "create disp overlay size %d\n", argc);
if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
nvif_ioctl(parent, "create disp overlay vers %d head %d\n", nvif_ioctl(parent, "create disp overlay vers %d head %d\n",
args->v0.version, args->v0.head); args->v0.version, args->v0.head);
if (!nvkm_head_find(&disp->base, args->v0.head)) if (!nvkm_head_find(&disp->base, args->v0.head))
@ -55,16 +51,14 @@ nv50_disp_oimm_new(const struct nv50_disp_chan_func *func,
} else } else
return ret; return ret;
return nv50_disp_chan_new_(func, mthd, disp, ctrl + head, user + head, return nv50_disp_chan_new_(func, NULL, disp, ctrl + head, user + head,
head, oclass, pobject); head, oclass, pobject);
} }
const struct nv50_disp_pioc_oclass int
nv50_disp_oimm_oclass = { nv50_disp_oimm_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
.base.oclass = NV50_DISP_OVERLAY, struct nv50_disp *disp, struct nvkm_object **pobject)
.base.minver = 0, {
.base.maxver = 0, return nv50_disp_oimm_new_(&nv50_disp_pioc_func, disp, 5, 5,
.ctor = nv50_disp_oimm_new, oclass, argv, argc, pobject);
.func = &nv50_disp_pioc_func, }
.chid = { 5, 5 },
};

2
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg84.c
View File

@ -33,10 +33,10 @@ g84_disp_root = {
&g84_disp_base_oclass, &g84_disp_base_oclass,
}, },
.pioc = { .pioc = {
&g84_disp_oimm_oclass,
&g84_disp_curs_oclass, &g84_disp_curs_oclass,
}, },
.user = { .user = {
{{0,0,G82_DISP_OVERLAY }, nv50_disp_oimm_new },
{{0,0,G82_DISP_OVERLAY_CHANNEL_DMA}, g84_disp_ovly_new }, {{0,0,G82_DISP_OVERLAY_CHANNEL_DMA}, g84_disp_ovly_new },
{} {}
}, },

2
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg94.c
View File

@ -33,10 +33,10 @@ g94_disp_root = {
&gt200_disp_base_oclass, &gt200_disp_base_oclass,
}, },
.pioc = { .pioc = {
&g84_disp_oimm_oclass,
&g84_disp_curs_oclass, &g84_disp_curs_oclass,
}, },
.user = { .user = {
{{0,0, G82_DISP_OVERLAY }, nv50_disp_oimm_new },
{{0,0,GT200_DISP_OVERLAY_CHANNEL_DMA}, gt200_disp_ovly_new }, {{0,0,GT200_DISP_OVERLAY_CHANNEL_DMA}, gt200_disp_ovly_new },
{} {}
}, },

2
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgf119.c
View File

@ -33,10 +33,10 @@ gf119_disp_root = {
&gf119_disp_base_oclass, &gf119_disp_base_oclass,
}, },
.pioc = { .pioc = {
&gf119_disp_oimm_oclass,
&gf119_disp_curs_oclass, &gf119_disp_curs_oclass,
}, },
.user = { .user = {
{{0,0,GF110_DISP_OVERLAY }, gf119_disp_oimm_new },
{{0,0,GF110_DISP_OVERLAY_CONTROL_DMA}, gf119_disp_ovly_new }, {{0,0,GF110_DISP_OVERLAY_CONTROL_DMA}, gf119_disp_ovly_new },
{} {}
}, },

2
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk104.c
View File

@ -33,10 +33,10 @@ gk104_disp_root = {
&gk104_disp_base_oclass, &gk104_disp_base_oclass,
}, },
.pioc = { .pioc = {
&gk104_disp_oimm_oclass,
&gk104_disp_curs_oclass, &gk104_disp_curs_oclass,
}, },
.user = { .user = {
{{0,0,GK104_DISP_OVERLAY }, gf119_disp_oimm_new },
{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new }, {{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
{} {}
}, },

2
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk110.c
View File

@ -33,10 +33,10 @@ gk110_disp_root = {
&gk110_disp_base_oclass, &gk110_disp_base_oclass,
}, },
.pioc = { .pioc = {
&gk104_disp_oimm_oclass,
&gk104_disp_curs_oclass, &gk104_disp_curs_oclass,
}, },
.user = { .user = {
{{0,0,GK104_DISP_OVERLAY }, gf119_disp_oimm_new },
{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new }, {{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
{} {}
}, },

2
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm107.c
View File

@ -33,10 +33,10 @@ gm107_disp_root = {
&gk110_disp_base_oclass, &gk110_disp_base_oclass,
}, },
.pioc = { .pioc = {
&gk104_disp_oimm_oclass,
&gk104_disp_curs_oclass, &gk104_disp_curs_oclass,
}, },
.user = { .user = {
{{0,0,GK104_DISP_OVERLAY }, gf119_disp_oimm_new },
{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new }, {{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
{} {}
}, },

2
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm200.c
View File

@ -33,10 +33,10 @@ gm200_disp_root = {
&gk110_disp_base_oclass, &gk110_disp_base_oclass,
}, },
.pioc = { .pioc = {
&gk104_disp_oimm_oclass,
&gk104_disp_curs_oclass, &gk104_disp_curs_oclass,
}, },
.user = { .user = {
{{0,0,GK104_DISP_OVERLAY }, gf119_disp_oimm_new },
{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new }, {{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
{} {}
}, },

2
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp100.c
View File

@ -33,10 +33,10 @@ gp100_disp_root = {
&gk110_disp_base_oclass, &gk110_disp_base_oclass,
}, },
.pioc = { .pioc = {
&gk104_disp_oimm_oclass,
&gk104_disp_curs_oclass, &gk104_disp_curs_oclass,
}, },
.user = { .user = {
{{0,0,GK104_DISP_OVERLAY }, gf119_disp_oimm_new },
{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new }, {{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
{} {}
}, },

2
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp102.c
View File

@ -33,10 +33,10 @@ gp102_disp_root = {
&gp102_disp_base_oclass, &gp102_disp_base_oclass,
}, },
.pioc = { .pioc = {
&gp102_disp_oimm_oclass,
&gp102_disp_curs_oclass, &gp102_disp_curs_oclass,
}, },
.user = { .user = {
{{0,0,GK104_DISP_OVERLAY }, gp102_disp_oimm_new },
{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gp102_disp_ovly_new }, {{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gp102_disp_ovly_new },
{} {}
}, },

2
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt200.c
View File

@ -33,10 +33,10 @@ gt200_disp_root = {
&gt200_disp_base_oclass, &gt200_disp_base_oclass,
}, },
.pioc = { .pioc = {
&g84_disp_oimm_oclass,
&g84_disp_curs_oclass, &g84_disp_curs_oclass,
}, },
.user = { .user = {
{{0,0, G82_DISP_OVERLAY }, nv50_disp_oimm_new },
{{0,0,GT200_DISP_OVERLAY_CHANNEL_DMA}, gt200_disp_ovly_new }, {{0,0,GT200_DISP_OVERLAY_CHANNEL_DMA}, gt200_disp_ovly_new },
{} {}
}, },

2
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt215.c
View File

@ -33,10 +33,10 @@ gt215_disp_root = {
&gt215_disp_base_oclass, &gt215_disp_base_oclass,
}, },
.pioc = { .pioc = {
&gt215_disp_oimm_oclass,
&gt215_disp_curs_oclass, &gt215_disp_curs_oclass,
}, },
.user = { .user = {
{{0,0,GT214_DISP_OVERLAY }, nv50_disp_oimm_new },
{{0,0,GT214_DISP_OVERLAY_CHANNEL_DMA}, g84_disp_ovly_new }, {{0,0,GT214_DISP_OVERLAY_CHANNEL_DMA}, g84_disp_ovly_new },
{} {}
}, },

2
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c
View File

@ -371,10 +371,10 @@ nv50_disp_root = {
&nv50_disp_base_oclass, &nv50_disp_base_oclass,
}, },
.pioc = { .pioc = {
&nv50_disp_oimm_oclass,
&nv50_disp_curs_oclass, &nv50_disp_curs_oclass,
}, },
.user = { .user = {
{{0,0,NV50_DISP_OVERLAY }, nv50_disp_oimm_new },
{{0,0,NV50_DISP_OVERLAY_CHANNEL_DMA}, nv50_disp_ovly_new }, {{0,0,NV50_DISP_OVERLAY_CHANNEL_DMA}, nv50_disp_ovly_new },
{} {}
}, },

2
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.h
View File

@ -14,7 +14,7 @@ struct nv50_disp_root {
struct nv50_disp_root_func { struct nv50_disp_root_func {
const struct nv50_disp_dmac_oclass *dmac[2]; const struct nv50_disp_dmac_oclass *dmac[2];
const struct nv50_disp_pioc_oclass *pioc[2]; const struct nv50_disp_pioc_oclass *pioc[1];
struct nv50_disp_user { struct nv50_disp_user {
struct nvkm_sclass base; struct nvkm_sclass base;
int (*ctor)(const struct nvkm_oclass *, void *argv, u32 argc, int (*ctor)(const struct nvkm_oclass *, void *argv, u32 argc,