forked from Minki/linux
nfit: update block I/O path to use PMEM API
Update the nfit block I/O path to use the new PMEM API and to adhere to the read/write flows outlined in the "NVDIMM Block Window Driver Writer's Guide": http://pmem.io/documents/NVDIMM_Driver_Writers_Guide.pdf This includes adding support for targeted NVDIMM flushes called "flush hints" in the ACPI 6.0 specification: http://www.uefi.org/sites/default/files/resources/ACPI_6.0.pdf For performance and media durability the mapping for a BLK aperture is moved to a write-combining mapping which is consistent with memcpy_to_pmem() and wmb_blk(). Signed-off-by: Ross Zwisler <ross.zwisler@linux.intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Ross Zwisler
Dan Williams
parent
9d27a87ec9
commit
c2ad29540c
@ -18,6 +18,7 @@
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#include <linux/list.h>
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#include <linux/acpi.h>
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#include <linux/sort.h>
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#include <linux/pmem.h>
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#include <linux/io.h>
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#include "nfit.h"
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@ -305,6 +306,23 @@ static bool add_idt(struct acpi_nfit_desc *acpi_desc,
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return true;
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}
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static bool add_flush(struct acpi_nfit_desc *acpi_desc,
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struct acpi_nfit_flush_address *flush)
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{
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struct device *dev = acpi_desc->dev;
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struct nfit_flush *nfit_flush = devm_kzalloc(dev, sizeof(*nfit_flush),
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GFP_KERNEL);
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if (!nfit_flush)
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return false;
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INIT_LIST_HEAD(&nfit_flush->list);
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nfit_flush->flush = flush;
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list_add_tail(&nfit_flush->list, &acpi_desc->flushes);
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dev_dbg(dev, "%s: nfit_flush handle: %d hint_count: %d\n", __func__,
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flush->device_handle, flush->hint_count);
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return true;
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}
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static void *add_table(struct acpi_nfit_desc *acpi_desc, void *table,
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const void *end)
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{
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@ -338,7 +356,8 @@ static void *add_table(struct acpi_nfit_desc *acpi_desc, void *table,
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return err;
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break;
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case ACPI_NFIT_TYPE_FLUSH_ADDRESS:
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dev_dbg(dev, "%s: flush\n", __func__);
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if (!add_flush(acpi_desc, table))
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return err;
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break;
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case ACPI_NFIT_TYPE_SMBIOS:
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dev_dbg(dev, "%s: smbios\n", __func__);
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@ -389,6 +408,7 @@ static int nfit_mem_add(struct acpi_nfit_desc *acpi_desc,
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{
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u16 dcr = __to_nfit_memdev(nfit_mem)->region_index;
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struct nfit_memdev *nfit_memdev;
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struct nfit_flush *nfit_flush;
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struct nfit_dcr *nfit_dcr;
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struct nfit_bdw *nfit_bdw;
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struct nfit_idt *nfit_idt;
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@ -442,6 +462,14 @@ static int nfit_mem_add(struct acpi_nfit_desc *acpi_desc,
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nfit_mem->idt_bdw = nfit_idt->idt;
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break;
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}
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list_for_each_entry(nfit_flush, &acpi_desc->flushes, list) {
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if (nfit_flush->flush->device_handle !=
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nfit_memdev->memdev->device_handle)
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continue;
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nfit_mem->nfit_flush = nfit_flush;
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break;
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}
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break;
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}
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@ -978,6 +1006,24 @@ static u64 to_interleave_offset(u64 offset, struct nfit_blk_mmio *mmio)
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return mmio->base_offset + line_offset + table_offset + sub_line_offset;
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}
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static void wmb_blk(struct nfit_blk *nfit_blk)
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{
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if (nfit_blk->nvdimm_flush) {
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/*
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* The first wmb() is needed to 'sfence' all previous writes
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* such that they are architecturally visible for the platform
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* buffer flush. Note that we've already arranged for pmem
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* writes to avoid the cache via arch_memcpy_to_pmem(). The
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* final wmb() ensures ordering for the NVDIMM flush write.
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*/
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wmb();
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writeq(1, nfit_blk->nvdimm_flush);
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wmb();
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} else
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wmb_pmem();
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}
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static u64 read_blk_stat(struct nfit_blk *nfit_blk, unsigned int bw)
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{
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struct nfit_blk_mmio *mmio = &nfit_blk->mmio[DCR];
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@ -1012,6 +1058,7 @@ static void write_blk_ctl(struct nfit_blk *nfit_blk, unsigned int bw,
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offset = to_interleave_offset(offset, mmio);
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writeq(cmd, mmio->base + offset);
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wmb_blk(nfit_blk);
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/* FIXME: conditionally perform read-back if mandated by firmware */
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}
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@ -1026,7 +1073,6 @@ static int acpi_nfit_blk_single_io(struct nfit_blk *nfit_blk,
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base_offset = nfit_blk->bdw_offset + dpa % L1_CACHE_BYTES
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+ lane * mmio->size;
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/* TODO: non-temporal access, flush hints, cache management etc... */
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write_blk_ctl(nfit_blk, lane, dpa, len, rw);
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while (len) {
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unsigned int c;
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@ -1045,13 +1091,19 @@ static int acpi_nfit_blk_single_io(struct nfit_blk *nfit_blk,
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}
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if (rw)
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memcpy(mmio->aperture + offset, iobuf + copied, c);
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memcpy_to_pmem(mmio->aperture + offset,
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iobuf + copied, c);
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else
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memcpy(iobuf + copied, mmio->aperture + offset, c);
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memcpy_from_pmem(iobuf + copied,
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mmio->aperture + offset, c);
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copied += c;
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len -= c;
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}
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if (rw)
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wmb_blk(nfit_blk);
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rc = read_blk_stat(nfit_blk, lane) ? -EIO : 0;
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return rc;
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}
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@ -1124,7 +1176,7 @@ static void nfit_spa_unmap(struct acpi_nfit_desc *acpi_desc,
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}
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static void __iomem *__nfit_spa_map(struct acpi_nfit_desc *acpi_desc,
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struct acpi_nfit_system_address *spa)
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struct acpi_nfit_system_address *spa, enum spa_map_type type)
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{
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resource_size_t start = spa->address;
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resource_size_t n = spa->length;
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@ -1152,8 +1204,15 @@ static void __iomem *__nfit_spa_map(struct acpi_nfit_desc *acpi_desc,
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if (!res)
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goto err_mem;
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/* TODO: cacheability based on the spa type */
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spa_map->iomem = ioremap_nocache(start, n);
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if (type == SPA_MAP_APERTURE) {
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/*
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* TODO: memremap_pmem() support, but that requires cache
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* flushing when the aperture is moved.
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*/
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spa_map->iomem = ioremap_wc(start, n);
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} else
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spa_map->iomem = ioremap_nocache(start, n);
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if (!spa_map->iomem)
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goto err_map;
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@ -1171,6 +1230,7 @@ static void __iomem *__nfit_spa_map(struct acpi_nfit_desc *acpi_desc,
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* nfit_spa_map - interleave-aware managed-mappings of acpi_nfit_system_address ranges
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* @nvdimm_bus: NFIT-bus that provided the spa table entry
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* @nfit_spa: spa table to map
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* @type: aperture or control region
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*
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* In the case where block-data-window apertures and
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* dimm-control-regions are interleaved they will end up sharing a
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@ -1180,12 +1240,12 @@ static void __iomem *__nfit_spa_map(struct acpi_nfit_desc *acpi_desc,
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* unbound.
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*/
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static void __iomem *nfit_spa_map(struct acpi_nfit_desc *acpi_desc,
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struct acpi_nfit_system_address *spa)
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struct acpi_nfit_system_address *spa, enum spa_map_type type)
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{
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void __iomem *iomem;
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mutex_lock(&acpi_desc->spa_map_mutex);
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iomem = __nfit_spa_map(acpi_desc, spa);
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iomem = __nfit_spa_map(acpi_desc, spa, type);
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mutex_unlock(&acpi_desc->spa_map_mutex);
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return iomem;
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@ -1212,6 +1272,7 @@ static int acpi_nfit_blk_region_enable(struct nvdimm_bus *nvdimm_bus,
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struct nvdimm_bus_descriptor *nd_desc = to_nd_desc(nvdimm_bus);
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struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);
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struct nd_blk_region *ndbr = to_nd_blk_region(dev);
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struct nfit_flush *nfit_flush;
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struct nfit_blk_mmio *mmio;
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struct nfit_blk *nfit_blk;
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struct nfit_mem *nfit_mem;
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@ -1237,7 +1298,8 @@ static int acpi_nfit_blk_region_enable(struct nvdimm_bus *nvdimm_bus,
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/* map block aperture memory */
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nfit_blk->bdw_offset = nfit_mem->bdw->offset;
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mmio = &nfit_blk->mmio[BDW];
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mmio->base = nfit_spa_map(acpi_desc, nfit_mem->spa_bdw);
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mmio->base = nfit_spa_map(acpi_desc, nfit_mem->spa_bdw,
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SPA_MAP_APERTURE);
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if (!mmio->base) {
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dev_dbg(dev, "%s: %s failed to map bdw\n", __func__,
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nvdimm_name(nvdimm));
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@ -1259,7 +1321,8 @@ static int acpi_nfit_blk_region_enable(struct nvdimm_bus *nvdimm_bus,
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nfit_blk->cmd_offset = nfit_mem->dcr->command_offset;
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nfit_blk->stat_offset = nfit_mem->dcr->status_offset;
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mmio = &nfit_blk->mmio[DCR];
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mmio->base = nfit_spa_map(acpi_desc, nfit_mem->spa_dcr);
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mmio->base = nfit_spa_map(acpi_desc, nfit_mem->spa_dcr,
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SPA_MAP_CONTROL);
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if (!mmio->base) {
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dev_dbg(dev, "%s: %s failed to map dcr\n", __func__,
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nvdimm_name(nvdimm));
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@ -1277,6 +1340,17 @@ static int acpi_nfit_blk_region_enable(struct nvdimm_bus *nvdimm_bus,
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return rc;
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}
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nfit_flush = nfit_mem->nfit_flush;
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if (nfit_flush && nfit_flush->flush->hint_count != 0) {
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nfit_blk->nvdimm_flush = devm_ioremap_nocache(dev,
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nfit_flush->flush->hint_address[0], 8);
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if (!nfit_blk->nvdimm_flush)
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return -ENOMEM;
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}
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if (!arch_has_pmem_api() && !nfit_blk->nvdimm_flush)
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dev_warn(dev, "unable to guarantee persistence of writes\n");
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if (mmio->line_size == 0)
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return 0;
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@ -1459,6 +1533,7 @@ int acpi_nfit_init(struct acpi_nfit_desc *acpi_desc, acpi_size sz)
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INIT_LIST_HEAD(&acpi_desc->dcrs);
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INIT_LIST_HEAD(&acpi_desc->bdws);
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INIT_LIST_HEAD(&acpi_desc->idts);
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INIT_LIST_HEAD(&acpi_desc->flushes);
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INIT_LIST_HEAD(&acpi_desc->memdevs);
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INIT_LIST_HEAD(&acpi_desc->dimms);
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mutex_init(&acpi_desc->spa_map_mutex);
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@ -60,6 +60,11 @@ struct nfit_idt {
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struct list_head list;
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};
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struct nfit_flush {
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struct acpi_nfit_flush_address *flush;
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struct list_head list;
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};
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struct nfit_memdev {
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struct acpi_nfit_memory_map *memdev;
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struct list_head list;
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@ -77,6 +82,7 @@ struct nfit_mem {
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struct acpi_nfit_system_address *spa_bdw;
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struct acpi_nfit_interleave *idt_dcr;
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struct acpi_nfit_interleave *idt_bdw;
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struct nfit_flush *nfit_flush;
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struct list_head list;
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struct acpi_device *adev;
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unsigned long dsm_mask;
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@ -88,6 +94,7 @@ struct acpi_nfit_desc {
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struct mutex spa_map_mutex;
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struct list_head spa_maps;
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struct list_head memdevs;
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struct list_head flushes;
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struct list_head dimms;
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struct list_head spas;
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struct list_head dcrs;
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@ -109,7 +116,7 @@ struct nfit_blk {
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struct nfit_blk_mmio {
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union {
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void __iomem *base;
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void *aperture;
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void __pmem *aperture;
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};
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u64 size;
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u64 base_offset;
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@ -123,6 +130,12 @@ struct nfit_blk {
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u64 bdw_offset; /* post interleave offset */
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u64 stat_offset;
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u64 cmd_offset;
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void __iomem *nvdimm_flush;
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};
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enum spa_map_type {
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SPA_MAP_CONTROL,
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SPA_MAP_APERTURE,
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};
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struct nfit_spa_mapping {
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