drm/amd/display: Properly set DCF clock
[Why] If num_states == 0 we did update_bound_box which doesn't updated any max clocks if num_states == 0, therefore we need to do cap_soc_clocks instead, also SMU cannot set DCF clock to a higher than or equal to freq than SOC clock [How] Add a num_states != 0 check for update_bounding_box to be run, and after we run get_maximum_sustainable_clocks we now check if the reported max value of DCF is higher than SOC and if necessary set it to 1000 (becomes 1 after division by 1000) lower than SOC Signed-off-by: Aidan Wood <Aidan.Wood@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2611,11 +2611,14 @@ static bool init_soc_bounding_box(struct dc *dc,
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if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {
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status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
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(&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);
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/* SMU cannot set DCF clock to anything equal to or higher than SOC clock
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*/
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if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz)
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max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000;
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clock_limits_available = (status == PP_SMU_RESULT_OK);
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}
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if (clock_limits_available && uclk_states_available)
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if (clock_limits_available && uclk_states_available && num_states)
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update_bounding_box(dc, &dcn2_0_soc, &max_clocks, uclk_states, num_states);
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else if (clock_limits_available)
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cap_soc_clocks(&dcn2_0_soc, max_clocks);
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