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iommu/ipmmu-vmsa: Allow two bit SL0

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Introduce support for two bit SL0 bitfield in IMTTBCR
by using a separate feature flag.

Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
This commit is contained in:
Magnus Damm 2017-10-16 21:30:39 +09:00 committed by Alex Williamson
parent f5c858912a
commit c295f504fb
1 changed files with 13 additions and 1 deletions
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14
drivers/iommu/ipmmu-vmsa.c
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@ -45,6 +45,7 @@ struct ipmmu_features {
bool has_cache_leaf_nodes; bool has_cache_leaf_nodes;
unsigned int number_of_contexts; unsigned int number_of_contexts;
bool setup_imbuscr; bool setup_imbuscr;
bool twobit_imttbcr_sl0;
}; };
struct ipmmu_vmsa_device { struct ipmmu_vmsa_device {
@ -144,6 +145,10 @@ static struct ipmmu_vmsa_device *to_ipmmu(struct device *dev)
#define IMTTBCR_TSZ0_MASK (7 << 0) #define IMTTBCR_TSZ0_MASK (7 << 0)
#define IMTTBCR_TSZ0_SHIFT O #define IMTTBCR_TSZ0_SHIFT O
#define IMTTBCR_SL0_TWOBIT_LVL_3 (0 << 6)
#define IMTTBCR_SL0_TWOBIT_LVL_2 (1 << 6)
#define IMTTBCR_SL0_TWOBIT_LVL_1 (2 << 6)
#define IMBUSCR 0x000c #define IMBUSCR 0x000c
#define IMBUSCR_DVM (1 << 2) #define IMBUSCR_DVM (1 << 2)
#define IMBUSCR_BUSSEL_SYS (0 << 0) #define IMBUSCR_BUSSEL_SYS (0 << 0)
@ -396,6 +401,7 @@ static void ipmmu_domain_free_context(struct ipmmu_vmsa_device *mmu,
static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain) static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
{ {
u64 ttbr; u64 ttbr;
u32 tmp;
int ret; int ret;
/* /*
@ -449,9 +455,14 @@ static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
* We use long descriptors with inner-shareable WBWA tables and allocate * We use long descriptors with inner-shareable WBWA tables and allocate
* the whole 32-bit VA space to TTBR0. * the whole 32-bit VA space to TTBR0.
*/ */
if (domain->mmu->features->twobit_imttbcr_sl0)
tmp = IMTTBCR_SL0_TWOBIT_LVL_1;
else
tmp = IMTTBCR_SL0_LVL_1;
ipmmu_ctx_write_root(domain, IMTTBCR, IMTTBCR_EAE | ipmmu_ctx_write_root(domain, IMTTBCR, IMTTBCR_EAE |
IMTTBCR_SH0_INNER_SHAREABLE | IMTTBCR_ORGN0_WB_WA | IMTTBCR_SH0_INNER_SHAREABLE | IMTTBCR_ORGN0_WB_WA |
IMTTBCR_IRGN0_WB_WA | IMTTBCR_SL0_LVL_1); IMTTBCR_IRGN0_WB_WA | tmp);
/* MAIR0 */ /* MAIR0 */
ipmmu_ctx_write_root(domain, IMMAIR0, ipmmu_ctx_write_root(domain, IMMAIR0,
@ -889,6 +900,7 @@ static const struct ipmmu_features ipmmu_features_default = {
.has_cache_leaf_nodes = false, .has_cache_leaf_nodes = false,
.number_of_contexts = 1, /* software only tested with one context */ .number_of_contexts = 1, /* software only tested with one context */
.setup_imbuscr = true, .setup_imbuscr = true,
.twobit_imttbcr_sl0 = false,
}; };
static const struct of_device_id ipmmu_of_ids[] = { static const struct of_device_id ipmmu_of_ids[] = {