forked from Minki/linux
[ARM] 5540/1: 32-bit Thumb-2 {ld,st}{m,rd} alignment fault fixup support
From: Min Zhang <mzhang@mvista.com> Add alignment fault fixup support for 32-bit Thumb-2 LDM, LDRD, POP, PUSH, STM and STRD instructions. Alignment fault fixup support for the remaining 32-bit Thumb-2 load/store instruction cases is not included since ARMv6 and later processors include hardware support for loads and stores of unaligned words and halfwords. Signed-off-by: Min Zhang <mzhang@mvista.com> Signed-off-by: George G. Davis <gdavis@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
George G. Davis
Russell King
parent
41184f6a5e
commit
c2860d43f5
@ -62,6 +62,12 @@
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#define SHIFT_ASR 0x40
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#define SHIFT_RORRRX 0x60
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#define BAD_INSTR 0xdeadc0de
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/* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */
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#define IS_T32(hi16) \
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(((hi16) & 0xe000) == 0xe000 && ((hi16) & 0x1800))
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static unsigned long ai_user;
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static unsigned long ai_sys;
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static unsigned long ai_skipped;
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@ -332,38 +338,48 @@ do_alignment_ldrdstrd(unsigned long addr, unsigned long instr,
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struct pt_regs *regs)
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{
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unsigned int rd = RD_BITS(instr);
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unsigned int rd2;
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int load;
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if (((rd & 1) == 1) || (rd == 14))
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if ((instr & 0xfe000000) == 0xe8000000) {
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/* ARMv7 Thumb-2 32-bit LDRD/STRD */
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rd2 = (instr >> 8) & 0xf;
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load = !!(LDST_L_BIT(instr));
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} else if (((rd & 1) == 1) || (rd == 14))
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goto bad;
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else {
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load = ((instr & 0xf0) == 0xd0);
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rd2 = rd + 1;
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}
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ai_dword += 1;
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if (user_mode(regs))
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goto user;
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if ((instr & 0xf0) == 0xd0) {
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if (load) {
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unsigned long val;
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get32_unaligned_check(val, addr);
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regs->uregs[rd] = val;
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get32_unaligned_check(val, addr + 4);
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regs->uregs[rd + 1] = val;
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regs->uregs[rd2] = val;
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} else {
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put32_unaligned_check(regs->uregs[rd], addr);
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put32_unaligned_check(regs->uregs[rd + 1], addr + 4);
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put32_unaligned_check(regs->uregs[rd2], addr + 4);
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}
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return TYPE_LDST;
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user:
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if ((instr & 0xf0) == 0xd0) {
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if (load) {
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unsigned long val;
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get32t_unaligned_check(val, addr);
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regs->uregs[rd] = val;
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get32t_unaligned_check(val, addr + 4);
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regs->uregs[rd + 1] = val;
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regs->uregs[rd2] = val;
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} else {
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put32t_unaligned_check(regs->uregs[rd], addr);
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put32t_unaligned_check(regs->uregs[rd + 1], addr + 4);
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put32t_unaligned_check(regs->uregs[rd2], addr + 4);
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}
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return TYPE_LDST;
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@ -616,10 +632,74 @@ thumb2arm(u16 tinstr)
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/* Else fall through for illegal instruction case */
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default:
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return 0xdeadc0de;
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return BAD_INSTR;
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}
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}
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/*
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* Convert Thumb-2 32 bit LDM, STM, LDRD, STRD to equivalent instruction
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* handlable by ARM alignment handler, also find the corresponding handler,
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* so that we can reuse ARM userland alignment fault fixups for Thumb.
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*
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* @pinstr: original Thumb-2 instruction; returns new handlable instruction
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* @regs: register context.
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* @poffset: return offset from faulted addr for later writeback
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*
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* NOTES:
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* 1. Comments below refer to ARMv7 DDI0406A Thumb Instruction sections.
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* 2. Register name Rt from ARMv7 is same as Rd from ARMv6 (Rd is Rt)
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*/
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static void *
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do_alignment_t32_to_handler(unsigned long *pinstr, struct pt_regs *regs,
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union offset_union *poffset)
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{
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unsigned long instr = *pinstr;
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u16 tinst1 = (instr >> 16) & 0xffff;
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u16 tinst2 = instr & 0xffff;
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poffset->un = 0;
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switch (tinst1 & 0xffe0) {
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/* A6.3.5 Load/Store multiple */
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case 0xe880: /* STM/STMIA/STMEA,LDM/LDMIA, PUSH/POP T2 */
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case 0xe8a0: /* ...above writeback version */
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case 0xe900: /* STMDB/STMFD, LDMDB/LDMEA */
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case 0xe920: /* ...above writeback version */
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/* no need offset decision since handler calculates it */
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return do_alignment_ldmstm;
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case 0xf840: /* POP/PUSH T3 (single register) */
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if (RN_BITS(instr) == 13 && (tinst2 & 0x09ff) == 0x0904) {
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u32 L = !!(LDST_L_BIT(instr));
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const u32 subset[2] = {
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0xe92d0000, /* STMDB sp!,{registers} */
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0xe8bd0000, /* LDMIA sp!,{registers} */
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};
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*pinstr = subset[L] | (1<<RD_BITS(instr));
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return do_alignment_ldmstm;
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}
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/* Else fall through for illegal instruction case */
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break;
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/* A6.3.6 Load/store double, STRD/LDRD(immed, lit, reg) */
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case 0xe860:
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case 0xe960:
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case 0xe8e0:
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case 0xe9e0:
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poffset->un = (tinst2 & 0xff) << 2;
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case 0xe940:
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case 0xe9c0:
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return do_alignment_ldrdstrd;
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/*
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* No need to handle load/store instructions up to word size
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* since ARMv6 and later CPUs can perform unaligned accesses.
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*/
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default:
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break;
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}
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return NULL;
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}
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static int
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do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
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{
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@ -630,6 +710,8 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
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mm_segment_t fs;
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unsigned int fault;
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u16 tinstr = 0;
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int isize = 4;
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int thumb2_32b = 0;
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instrptr = instruction_pointer(regs);
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@ -637,8 +719,19 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
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set_fs(KERNEL_DS);
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if (thumb_mode(regs)) {
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fault = __get_user(tinstr, (u16 *)(instrptr & ~1));
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if (!(fault))
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instr = thumb2arm(tinstr);
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if (!fault) {
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if (cpu_architecture() >= CPU_ARCH_ARMv7 &&
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IS_T32(tinstr)) {
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/* Thumb-2 32-bit */
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u16 tinst2 = 0;
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fault = __get_user(tinst2, (u16 *)(instrptr+2));
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instr = (tinstr << 16) | tinst2;
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thumb2_32b = 1;
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} else {
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isize = 2;
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instr = thumb2arm(tinstr);
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}
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}
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} else
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fault = __get_user(instr, (u32 *)instrptr);
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set_fs(fs);
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@ -655,7 +748,7 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
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fixup:
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regs->ARM_pc += thumb_mode(regs) ? 2 : 4;
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regs->ARM_pc += isize;
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switch (CODING_BITS(instr)) {
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case 0x00000000: /* 3.13.4 load/store instruction extensions */
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@ -714,18 +807,25 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
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handler = do_alignment_ldrstr;
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break;
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case 0x08000000: /* ldm or stm */
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handler = do_alignment_ldmstm;
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case 0x08000000: /* ldm or stm, or thumb-2 32bit instruction */
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if (thumb2_32b)
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handler = do_alignment_t32_to_handler(&instr, regs, &offset);
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else
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handler = do_alignment_ldmstm;
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break;
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default:
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goto bad;
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}
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if (!handler)
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goto bad;
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type = handler(addr, instr, regs);
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if (type == TYPE_ERROR || type == TYPE_FAULT)
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if (type == TYPE_ERROR || type == TYPE_FAULT) {
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regs->ARM_pc -= isize;
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goto bad_or_fault;
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}
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if (type == TYPE_LDST)
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do_alignment_finish_ldst(addr, instr, regs, offset);
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@ -735,7 +835,6 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
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bad_or_fault:
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if (type == TYPE_ERROR)
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goto bad;
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regs->ARM_pc -= thumb_mode(regs) ? 2 : 4;
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/*
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* We got a fault - fix it up, or die.
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*/
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@ -751,8 +850,8 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
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*/
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printk(KERN_ERR "Alignment trap: not handling instruction "
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"%0*lx at [<%08lx>]\n",
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thumb_mode(regs) ? 4 : 8,
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thumb_mode(regs) ? tinstr : instr, instrptr);
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isize << 1,
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isize == 2 ? tinstr : instr, instrptr);
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ai_skipped += 1;
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return 1;
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@ -763,8 +862,8 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
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printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx "
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"Address=0x%08lx FSR 0x%03x\n", current->comm,
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task_pid_nr(current), instrptr,
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thumb_mode(regs) ? 4 : 8,
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thumb_mode(regs) ? tinstr : instr,
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isize << 1,
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isize == 2 ? tinstr : instr,
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addr, fsr);
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if (ai_usermode & UM_FIXUP)
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