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PCI: designware: Fix comment for setting number of lanes

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Corrects comment for setting number of lanes.

Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
This commit is contained in:
Mohit Kumar 2014-04-16 10:23:28 -06:00 committed by Bjorn Helgaas
parent 140ab6452c
commit c23fdc7da4
1 changed files with 1 additions and 1 deletions
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2
drivers/pci/host/pcie-designware.c
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@ -764,7 +764,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
u32 membase;
u32 memlimit;
/* set the number of lines as 4 */
/* set the number of lanes */
dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
val &= ~PORT_LINK_MODE_MASK;
switch (pp->lanes) {