forked from Minki/linux
can: xilinx_can: Add support for CANFD FD frames
CANFD IP supports both CAN and CAN FD frames, Existing driver supports only CAN frames, This patch adds support for CAN FD frames. Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
This commit is contained in:
Appana Durga Kedareswara rao
Marc Kleine-Budde
parent
8dce7ea41a
commit
c223da6893
@ -50,6 +50,10 @@ enum xcan_reg {
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XCAN_AFR_OFFSET = 0x60, /* Acceptance Filter */
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/* only on CAN FD cores */
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XCAN_F_BRPR_OFFSET = 0x088, /* Data Phase Baud Rate
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* Prescalar
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*/
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XCAN_F_BTR_OFFSET = 0x08C, /* Data Phase Bit Timing */
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XCAN_TRR_OFFSET = 0x0090, /* TX Buffer Ready Request */
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XCAN_AFR_EXT_OFFSET = 0x00E0, /* Acceptance Filter */
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XCAN_FSR_OFFSET = 0x00E8, /* RX FIFO Status */
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@ -62,6 +66,8 @@ enum xcan_reg {
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#define XCAN_FRAME_DLC_OFFSET(frame_base) ((frame_base) + 0x04)
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#define XCAN_FRAME_DW1_OFFSET(frame_base) ((frame_base) + 0x08)
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#define XCAN_FRAME_DW2_OFFSET(frame_base) ((frame_base) + 0x0C)
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#define XCANFD_FRAME_DW_OFFSET(frame_base, n) (((frame_base) + 0x08) + \
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((n) * XCAN_CANFD_FRAME_SIZE))
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#define XCAN_CANFD_FRAME_SIZE 0x48
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#define XCAN_TXMSG_FRAME_OFFSET(n) (XCAN_TXMSG_BASE_OFFSET + \
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@ -120,6 +126,8 @@ enum xcan_reg {
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#define XCAN_FSR_FL_MASK 0x00003F00 /* RX Fill Level */
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#define XCAN_FSR_IRI_MASK 0x00000080 /* RX Increment Read Index */
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#define XCAN_FSR_RI_MASK 0x0000001F /* RX Read Index */
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#define XCAN_DLCR_EDL_MASK 0x08000000 /* EDL Mask in DLC */
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#define XCAN_DLCR_BRS_MASK 0x04000000 /* BRS Mask in DLC */
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/* CAN register bit shift - XCAN_<REG>_<BIT>_SHIFT */
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#define XCAN_BTR_SJW_SHIFT 7 /* Synchronous jump width */
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@ -133,6 +141,7 @@ enum xcan_reg {
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/* CAN frame length constants */
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#define XCAN_FRAME_MAX_DATA_LEN 8
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#define XCANFD_DW_BYTES 4
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#define XCAN_TIMEOUT (1 * HZ)
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/* TX-FIFO-empty interrupt available */
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@ -213,6 +222,7 @@ static const struct can_bittiming_const xcan_bittiming_const = {
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.brp_inc = 1,
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};
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/* AXI CANFD Arbitration Bittiming constants as per AXI CANFD 1.0 spec */
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static const struct can_bittiming_const xcan_bittiming_const_canfd = {
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.name = DRIVER_NAME,
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.tseg1_min = 1,
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@ -225,6 +235,20 @@ static const struct can_bittiming_const xcan_bittiming_const_canfd = {
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.brp_inc = 1,
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};
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/* AXI CANFD Data Bittiming constants as per AXI CANFD 1.0 specs */
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static struct can_bittiming_const xcan_data_bittiming_const_canfd = {
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.name = DRIVER_NAME,
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.tseg1_min = 1,
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.tseg1_max = 16,
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.tseg2_min = 1,
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.tseg2_max = 8,
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.sjw_max = 8,
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.brp_min = 1,
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.brp_max = 256,
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.brp_inc = 1,
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};
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/* AXI CANFD 2.0 Arbitration Bittiming constants as per AXI CANFD 2.0 spec */
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static const struct can_bittiming_const xcan_bittiming_const_canfd2 = {
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.name = DRIVER_NAME,
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.tseg1_min = 1,
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@ -237,6 +261,19 @@ static const struct can_bittiming_const xcan_bittiming_const_canfd2 = {
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.brp_inc = 1,
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};
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/* AXI CANFD 2.0 Data Bittiming constants as per AXI CANFD 2.0 spec */
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static struct can_bittiming_const xcan_data_bittiming_const_canfd2 = {
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.name = DRIVER_NAME,
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.tseg1_min = 1,
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.tseg1_max = 32,
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.tseg2_min = 1,
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.tseg2_max = 16,
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.sjw_max = 16,
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.brp_min = 1,
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.brp_max = 256,
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.brp_inc = 1,
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};
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/**
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* xcan_write_reg_le - Write a value to the device register little endian
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* @priv: Driver private data structure
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@ -351,6 +388,7 @@ static int xcan_set_bittiming(struct net_device *ndev)
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{
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struct xcan_priv *priv = netdev_priv(ndev);
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struct can_bittiming *bt = &priv->can.bittiming;
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struct can_bittiming *dbt = &priv->can.data_bittiming;
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u32 btr0, btr1;
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u32 is_config_mode;
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@ -380,6 +418,24 @@ static int xcan_set_bittiming(struct net_device *ndev)
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priv->write_reg(priv, XCAN_BRPR_OFFSET, btr0);
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priv->write_reg(priv, XCAN_BTR_OFFSET, btr1);
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if (priv->devtype.cantype == XAXI_CANFD ||
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priv->devtype.cantype == XAXI_CANFD_2_0) {
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/* Setting Baud Rate prescalar value in F_BRPR Register */
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btr0 = dbt->brp - 1;
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/* Setting Time Segment 1 in BTR Register */
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btr1 = dbt->prop_seg + bt->phase_seg1 - 1;
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/* Setting Time Segment 2 in BTR Register */
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btr1 |= (dbt->phase_seg2 - 1) << priv->devtype.btr_ts2_shift;
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/* Setting Synchronous jump width in BTR Register */
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btr1 |= (dbt->sjw - 1) << priv->devtype.btr_sjw_shift;
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priv->write_reg(priv, XCAN_F_BRPR_OFFSET, btr0);
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priv->write_reg(priv, XCAN_F_BTR_OFFSET, btr1);
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}
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netdev_dbg(ndev, "BRPR=0x%08x, BTR=0x%08x\n",
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priv->read_reg(priv, XCAN_BRPR_OFFSET),
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priv->read_reg(priv, XCAN_BTR_OFFSET));
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@ -499,7 +555,8 @@ static void xcan_write_frame(struct xcan_priv *priv, struct sk_buff *skb,
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int frame_offset)
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{
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u32 id, dlc, data[2] = {0, 0};
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struct can_frame *cf = (struct can_frame *)skb->data;
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struct canfd_frame *cf = (struct canfd_frame *)skb->data;
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u32 ramoff, dwindex = 0, i;
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/* Watch carefully on the bit sequence */
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if (cf->can_id & CAN_EFF_FLAG) {
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@ -528,26 +585,44 @@ static void xcan_write_frame(struct xcan_priv *priv, struct sk_buff *skb,
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id |= XCAN_IDR_SRR_MASK;
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}
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dlc = cf->can_dlc << XCAN_DLCR_DLC_SHIFT;
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if (cf->can_dlc > 0)
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data[0] = be32_to_cpup((__be32 *)(cf->data + 0));
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if (cf->can_dlc > 4)
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data[1] = be32_to_cpup((__be32 *)(cf->data + 4));
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dlc = can_len2dlc(cf->len) << XCAN_DLCR_DLC_SHIFT;
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if (can_is_canfd_skb(skb)) {
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if (cf->flags & CANFD_BRS)
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dlc |= XCAN_DLCR_BRS_MASK;
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dlc |= XCAN_DLCR_EDL_MASK;
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}
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priv->write_reg(priv, XCAN_FRAME_ID_OFFSET(frame_offset), id);
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/* If the CAN frame is RTR frame this write triggers transmission
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* (not on CAN FD)
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*/
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priv->write_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_offset), dlc);
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if (!(cf->can_id & CAN_RTR_FLAG)) {
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priv->write_reg(priv, XCAN_FRAME_DW1_OFFSET(frame_offset),
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data[0]);
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/* If the CAN frame is Standard/Extended frame this
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* write triggers transmission (not on CAN FD)
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*/
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priv->write_reg(priv, XCAN_FRAME_DW2_OFFSET(frame_offset),
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data[1]);
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if (priv->devtype.cantype == XAXI_CANFD ||
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priv->devtype.cantype == XAXI_CANFD_2_0) {
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for (i = 0; i < cf->len; i += 4) {
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ramoff = XCANFD_FRAME_DW_OFFSET(frame_offset, dwindex) +
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(dwindex * XCANFD_DW_BYTES);
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priv->write_reg(priv, ramoff,
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be32_to_cpup((__be32 *)(cf->data + i)));
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dwindex++;
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}
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} else {
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if (cf->len > 0)
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data[0] = be32_to_cpup((__be32 *)(cf->data + 0));
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if (cf->len > 4)
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data[1] = be32_to_cpup((__be32 *)(cf->data + 4));
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if (!(cf->can_id & CAN_RTR_FLAG)) {
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priv->write_reg(priv,
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XCAN_FRAME_DW1_OFFSET(frame_offset),
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data[0]);
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/* If the CAN frame is Standard/Extended frame this
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* write triggers transmission (not on CAN FD)
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*/
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priv->write_reg(priv,
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XCAN_FRAME_DW2_OFFSET(frame_offset),
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data[1]);
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}
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}
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}
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@ -724,6 +799,113 @@ static int xcan_rx(struct net_device *ndev, int frame_base)
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return 1;
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}
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/**
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* xcanfd_rx - Is called from CAN isr to complete the received
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* frame processing
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* @ndev: Pointer to net_device structure
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* @frame_base: Register offset to the frame to be read
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*
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* This function is invoked from the CAN isr(poll) to process the Rx frames. It
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* does minimal processing and invokes "netif_receive_skb" to complete further
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* processing.
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* Return: 1 on success and 0 on failure.
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*/
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static int xcanfd_rx(struct net_device *ndev, int frame_base)
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{
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struct xcan_priv *priv = netdev_priv(ndev);
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struct net_device_stats *stats = &ndev->stats;
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struct canfd_frame *cf;
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struct sk_buff *skb;
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u32 id_xcan, dlc, data[2] = {0, 0}, dwindex = 0, i, fsr, readindex;
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fsr = priv->read_reg(priv, XCAN_FSR_OFFSET);
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if (fsr & XCAN_FSR_FL_MASK) {
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readindex = fsr & XCAN_FSR_RI_MASK;
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id_xcan = priv->read_reg(priv,
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XCAN_FRAME_ID_OFFSET(frame_base));
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dlc = priv->read_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_base));
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if (dlc & XCAN_DLCR_EDL_MASK)
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skb = alloc_canfd_skb(ndev, &cf);
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else
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skb = alloc_can_skb(ndev, (struct can_frame **)&cf);
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if (unlikely(!skb)) {
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stats->rx_dropped++;
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return 0;
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}
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/* Change Xilinx CANFD data length format to socketCAN data
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* format
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*/
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if (dlc & XCAN_DLCR_EDL_MASK)
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cf->len = can_dlc2len((dlc & XCAN_DLCR_DLC_MASK) >>
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XCAN_DLCR_DLC_SHIFT);
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else
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cf->len = get_can_dlc((dlc & XCAN_DLCR_DLC_MASK) >>
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XCAN_DLCR_DLC_SHIFT);
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/* Change Xilinx CAN ID format to socketCAN ID format */
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if (id_xcan & XCAN_IDR_IDE_MASK) {
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/* The received frame is an Extended format frame */
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cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 3;
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cf->can_id |= (id_xcan & XCAN_IDR_ID2_MASK) >>
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XCAN_IDR_ID2_SHIFT;
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cf->can_id |= CAN_EFF_FLAG;
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if (id_xcan & XCAN_IDR_RTR_MASK)
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cf->can_id |= CAN_RTR_FLAG;
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} else {
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/* The received frame is a standard format frame */
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cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >>
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XCAN_IDR_ID1_SHIFT;
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if (!(dlc & XCAN_DLCR_EDL_MASK) && (id_xcan &
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XCAN_IDR_SRR_MASK))
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cf->can_id |= CAN_RTR_FLAG;
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}
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/* Check the frame received is FD or not*/
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if (dlc & XCAN_DLCR_EDL_MASK) {
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for (i = 0; i < cf->len; i += 4) {
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if (priv->devtype.flags & XCAN_FLAG_CANFD_2)
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data[0] = priv->read_reg(priv,
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(XCAN_RXMSG_2_FRAME_OFFSET(readindex) +
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(dwindex * XCANFD_DW_BYTES)));
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else
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data[0] = priv->read_reg(priv,
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(XCAN_RXMSG_FRAME_OFFSET(readindex) +
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(dwindex * XCANFD_DW_BYTES)));
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*(__be32 *)(cf->data + i) =
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cpu_to_be32(data[0]);
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dwindex++;
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}
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} else {
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for (i = 0; i < cf->len; i += 4) {
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if (priv->devtype.flags & XCAN_FLAG_CANFD_2)
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data[0] = priv->read_reg(priv,
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XCAN_RXMSG_2_FRAME_OFFSET(readindex) + i);
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else
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data[0] = priv->read_reg(priv,
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XCAN_RXMSG_FRAME_OFFSET(readindex) + i);
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*(__be32 *)(cf->data + i) =
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cpu_to_be32(data[0]);
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}
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}
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/* Update FSR Register so that next packet will save to
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* buffer
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*/
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fsr = priv->read_reg(priv, XCAN_FSR_OFFSET);
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fsr |= XCAN_FSR_IRI_MASK;
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priv->write_reg(priv, XCAN_FSR_OFFSET, fsr);
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fsr = priv->read_reg(priv, XCAN_FSR_OFFSET);
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stats->rx_bytes += cf->len;
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stats->rx_packets++;
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netif_receive_skb(skb);
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return 1;
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}
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/* If FSR Register is not updated with fill level */
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return 0;
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}
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/**
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* xcan_current_error_state - Get current error state from HW
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* @ndev: Pointer to net_device structure
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@ -1035,7 +1217,10 @@ static int xcan_rx_poll(struct napi_struct *napi, int quota)
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while ((frame_offset = xcan_rx_fifo_get_next_frame(priv)) >= 0 &&
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(work_done < quota)) {
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work_done += xcan_rx(ndev, frame_offset);
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if (xcan_rx_int_mask(priv) & XCAN_IXR_RXOK_MASK)
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work_done += xcanfd_rx(ndev, frame_offset);
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else
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work_done += xcan_rx(ndev, frame_offset);
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if (priv->devtype.flags & XCAN_FLAG_RX_FIFO_MULTI)
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/* increment read index */
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@ -1577,6 +1762,19 @@ static int xcan_probe(struct platform_device *pdev)
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priv->can.do_get_berr_counter = xcan_get_berr_counter;
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priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
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CAN_CTRLMODE_BERR_REPORTING;
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if (devtype->cantype == XAXI_CANFD)
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priv->can.data_bittiming_const =
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&xcan_data_bittiming_const_canfd;
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if (devtype->cantype == XAXI_CANFD_2_0)
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priv->can.data_bittiming_const =
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&xcan_data_bittiming_const_canfd2;
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if (devtype->cantype == XAXI_CANFD ||
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devtype->cantype == XAXI_CANFD_2_0)
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priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD;
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priv->reg_base = addr;
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priv->tx_max = tx_max;
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priv->devtype = *devtype;
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