Amlogic 64-bit DT updates for v4.18
- AXG family: support more peripherals (wifi, eMMC, clocks) - GX family: add/enable USB host support -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEe4dGDhaSf6n1v/EMWTcYmtP7xmUFAlr7XJUACgkQWTcYmtP7 xmV6tRAAp+tlG3OiuKXraOeOJZDW9nqQbwCgH8tLl4feayOfIM0OEq1Xz2GbRM42 XZxa5mIifebtE6Is8ow33+O6Sm1G9MjRPzsEE0IVpK3X7pGu767xmMs1HiWe7ovU 9melof4TZBJzsD4WKA29ByU8Hhtt65/BWQOEdRciqhVdEUJ5pxyEdvrSa8zYIaWc brLr8P3oAA2lTO4Vmd1yEnxrhxVqLYBEQYojFEc7iRAVeTgCYCrYZE7diY20l6JZ vsJGK/K1goUuITnxeHnWWF3tAwLQcUb6SkH4tYk/m7sOJeFM3j2gqcXqqEUjjNOH AEn+vDFB7OmIIAJaJAPw5nTYIriTQGDGFmNZaBSlQXQGFi3FPZI//uupmeV/qUAB uonGJtAw90g8onhkjvg3fubd3UV1xNtgCSWhorZ5UN9ouCPKeFVvdU15cImdx/cC aR7K+X74kcr/ByChXAupJT1/1GtgHd8ol8WqKJHwZy2csllLyq9wzar73ytZA1Dz 3leLZxo07IkuhPxnBdjC/Kh63hqq1H01tmNmoUlQqOh2sngByeXsxhYyi1fTD9ui FPR4IGmgVL2aIpEXgzIn4VCTWAhPDV5a80gTIdyVhPzRSbvI1aPTQkFsvHyafalw 3fL5aKjOKNgSggLX+Qth9+LBnHUgsa5aNj/MQV9aK+99OML4Ffw= =7skA -----END PGP SIGNATURE----- Merge tag 'amlogic-dt64' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt Amlogic 64-bit DT updates for v4.18 - AXG family: support more peripherals (wifi, eMMC, clocks) - GX family: add/enable USB host support * tag 'amlogic-dt64' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: dt-bindings: arm: amlogic: add support for the Tronsmart MXIII Plus dt-bindings: arm: amlogic: add support for the Meson8m2 SoC ARM64: dts: meson-axg: enable AP6255 wifi module ARM64: dts: meson: add MMC resets ARM64: dts: meson-axg: add an 32K alt aoclk ARM64: dts: meson-axg: add tdm pins ARM64: dts: meson-axg: add GPIO interrupt controller support ARM64: dts: meson-axg: enable the eMMC controller ARM64: dts: meson-gx: fix gxl clock controller compatible ARM64: dts: meson-axg: use hhi syscon for the clock controller ARM64: dts: meson-gx: sysctrl is the parent of the clock controller dt-bindings: clock: meson: update documentation with hhi syscon Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
c1835bfdef
@ -25,6 +25,10 @@ Boards with the Amlogic Meson8b SoC shall have the following properties:
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Required root node property:
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compatible: "amlogic,meson8b";
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Boards with the Amlogic Meson8m2 SoC shall have the following properties:
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Required root node property:
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compatible: "amlogic,meson8m2";
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Boards with the Amlogic Meson GXBaby SoC shall have the following properties:
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Required root node property:
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compatible: "amlogic,meson-gxbb";
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@ -54,6 +58,8 @@ Board compatible values (alphabetically, grouped by SoC):
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- "hardkernel,odroid-c1" (Meson8b)
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- "tronfy,mxq" (Meson8b)
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- "tronsmart,mxiii-plus" (Meson8m2)
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- "amlogic,p200" (Meson gxbb)
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- "amlogic,p201" (Meson gxbb)
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- "friendlyarm,nanopi-k2" (Meson gxbb)
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@ -10,9 +10,6 @@ Required Properties:
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"amlogic,gxl-clkc" for GXL and GXM SoC,
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"amlogic,axg-clkc" for AXG SoC.
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- reg: physical base address of the clock controller and length of memory
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mapped region.
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- #clock-cells: should be 1.
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Each clock is assigned an identifier and client nodes can use this identifier
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@ -20,13 +17,22 @@ to specify the clock which they consume. All available clocks are defined as
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preprocessor macros in the dt-bindings/clock/gxbb-clkc.h header and can be
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used in device tree sources.
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Parent node should have the following properties :
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- compatible: "syscon", "simple-mfd, and "amlogic,meson-gx-hhi-sysctrl" or
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"amlogic,meson-axg-hhi-sysctrl"
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- reg: base address and size of the HHI system control register space.
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Example: Clock controller node:
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clkc: clock-controller@c883c000 {
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sysctrl: system-controller@0 {
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compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd";
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reg = <0 0 0 0x400>;
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clkc: clock-controller {
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#clock-cells = <1>;
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compatible = "amlogic,gxbb-clkc";
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reg = <0x0 0xc883c000 0x0 0x3db>;
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};
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};
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Example: UART controller node that consumes the clock generated by the clock
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controller:
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@ -15,6 +15,53 @@
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serial0 = &uart_AO;
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serial1 = &uart_A;
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};
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vddio_boot: regulator-vddio_boot {
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compatible = "regulator-fixed";
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regulator-name = "VDDIO_BOOT";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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vddao_3v3: regulator-vddao_3v3 {
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compatible = "regulator-fixed";
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regulator-name = "VDDAO_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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vddio_ao18: regulator-vddio_ao18 {
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compatible = "regulator-fixed";
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regulator-name = "VDDIO_AO18";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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vcc_3v3: regulator-vcc_3v3 {
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compatible = "regulator-fixed";
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regulator-name = "VCC_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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emmc_pwrseq: emmc-pwrseq {
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compatible = "mmc-pwrseq-emmc";
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reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
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};
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sdio_pwrseq: sdio-pwrseq {
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compatible = "mmc-pwrseq-simple";
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reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>;
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clocks = <&wifi32k>;
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clock-names = "ext_clock";
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};
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wifi32k: wifi32k {
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compatible = "pwm-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */
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};
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};
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ðmac {
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@ -47,3 +94,56 @@
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pinctrl-0 = <&i2c1_z_pins>;
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pinctrl-names = "default";
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};
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&pwm_ab {
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status = "okay";
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pinctrl-0 = <&pwm_a_x20_pins>;
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pinctrl-names = "default";
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};
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/* emmc storage */
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&sd_emmc_c {
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status = "okay";
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pinctrl-0 = <&emmc_pins>;
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pinctrl-1 = <&emmc_clk_gate_pins>;
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pinctrl-names = "default", "clk-gate";
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bus-width = <8>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <180000000>;
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non-removable;
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disable-wp;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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vmmc-supply = <&vcc_3v3>;
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vqmmc-supply = <&vddio_boot>;
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};
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/* wifi module */
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&sd_emmc_b {
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&sdio_pins>;
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pinctrl-1 = <&sdio_clk_gate_pins>;
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pinctrl-names = "default", "clk-gate";
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bus-width = <4>;
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cap-sd-highspeed;
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max-frequency = <100000000>;
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non-removable;
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disable-wp;
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mmc-pwrseq = <&sdio_pwrseq>;
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vmmc-supply = <&vddao_3v3>;
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vqmmc-supply = <&vddio_boot>;
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brcmf: wifi@1 {
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reg = <1>;
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compatible = "brcm,bcm4329-fmac";
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};
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};
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@ -7,6 +7,8 @@
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/axg-clkc.h>
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#include <dt-bindings/gpio/meson-axg-gpio.h>
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#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
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/ {
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compatible = "amlogic,meson-axg";
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@ -107,12 +109,51 @@
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#clock-cells = <0>;
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};
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ao_alt_xtal: ao_alt_xtal-clk {
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compatible = "fixed-clock";
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clock-frequency = <32000000>;
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clock-output-names = "ao_alt_xtal";
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#clock-cells = <0>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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apb: apb@ffe00000 {
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compatible = "simple-bus";
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reg = <0x0 0xffe00000 0x0 0x200000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
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sd_emmc_b: sd@5000 {
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compatible = "amlogic,meson-axg-mmc";
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reg = <0x0 0x5000 0x0 0x2000>;
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interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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clocks = <&clkc CLKID_SD_EMMC_B>,
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<&clkc CLKID_SD_EMMC_B_CLK0>,
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<&clkc CLKID_FCLK_DIV2>;
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clock-names = "core", "clkin0", "clkin1";
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resets = <&reset RESET_SD_EMMC_B>;
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};
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sd_emmc_c: mmc@7000 {
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compatible = "amlogic,meson-axg-mmc";
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reg = <0x0 0x7000 0x0 0x2000>;
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interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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clocks = <&clkc CLKID_SD_EMMC_C>,
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<&clkc CLKID_SD_EMMC_C_CLK0>,
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<&clkc CLKID_FCLK_DIV2>;
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clock-names = "core", "clkin0", "clkin1";
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resets = <&reset RESET_SD_EMMC_C>;
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};
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};
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cbus: bus@ffd00000 {
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compatible = "simple-bus";
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reg = <0x0 0xffd00000 0x0 0x25000>;
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@ -120,6 +161,15 @@
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
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gpio_intc: interrupt-controller@f080 {
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compatible = "amlogic,meson-gpio-intc";
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reg = <0x0 0xf080 0x0 0x10>;
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interrupt-controller;
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#interrupt-cells = <2>;
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amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
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status = "disabled";
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};
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pwm_ab: pwm@1b000 {
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compatible = "amlogic,meson-axg-ee-pwm";
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reg = <0x0 0x1b000 0x0 0x20>;
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@ -262,10 +312,14 @@
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
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clkc: clock-controller@0 {
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compatible = "amlogic,axg-clkc";
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#clock-cells = <1>;
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reg = <0x0 0x0 0x0 0x320>;
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sysctrl: system-controller@0 {
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compatible = "amlogic,meson-axg-hhi-sysctrl", "syscon", "simple-mfd";
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reg = <0 0 0 0x400>;
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clkc: clock-controller {
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compatible = "amlogic,axg-clkc";
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#clock-cells = <1>;
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};
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};
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};
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@ -309,6 +363,57 @@
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gpio-ranges = <&pinctrl_periphs 0 0 86>;
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};
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emmc_pins: emmc {
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mux {
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groups = "emmc_nand_d0",
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"emmc_nand_d1",
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"emmc_nand_d2",
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"emmc_nand_d3",
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"emmc_nand_d4",
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"emmc_nand_d5",
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"emmc_nand_d6",
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"emmc_nand_d7",
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"emmc_clk",
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"emmc_cmd",
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"emmc_ds";
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function = "emmc";
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};
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};
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emmc_clk_gate_pins: emmc_clk_gate {
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mux {
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groups = "BOOT_8";
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function = "gpio_periphs";
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};
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cfg-pull-down {
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pins = "BOOT_8";
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bias-pull-down;
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};
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};
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sdio_pins: sdio {
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mux {
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groups = "sdio_d0",
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"sdio_d1",
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"sdio_d2",
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"sdio_d3",
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"sdio_cmd",
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"sdio_clk";
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function = "sdio";
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};
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};
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sdio_clk_gate_pins: sdio_clk_gate {
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mux {
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groups = "GPIOX_4";
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function = "gpio_periphs";
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};
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cfg-pull-down {
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pins = "GPIOX_4";
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bias-pull-down;
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};
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};
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eth_rmii_x_pins: eth-x-rmii {
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mux {
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groups = "eth_mdio_x",
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@ -660,6 +765,251 @@
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function = "uart_ao_b_z";
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};
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};
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mclk_b_pins: mclk_b {
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mux {
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groups = "mclk_b";
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function = "mclk_b";
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};
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};
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mclk_c_pins: mclk_c {
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mux {
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groups = "mclk_c";
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function = "mclk_c";
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};
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};
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tdma_sclk_pins: tdma_sclk {
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mux {
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groups = "tdma_sclk";
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function = "tdma";
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};
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};
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tdma_sclk_slv_pins: tdma_sclk_slv {
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mux {
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groups = "tdma_sclk_slv";
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function = "tdma";
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};
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};
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tdma_fs_pins: tdma_fs {
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mux {
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groups = "tdma_fs";
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function = "tdma";
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};
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};
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tdma_fs_slv_pins: tdma_fs_slv {
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mux {
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groups = "tdma_fs_slv";
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function = "tdma";
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};
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};
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tdma_din0_pins: tdma_din0 {
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mux {
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groups = "tdma_din0";
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function = "tdma";
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};
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};
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tdma_dout0_x14_pins: tdma_dout0_x14 {
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mux {
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groups = "tdma_dout0_x14";
|
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function = "tdma";
|
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};
|
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};
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tdma_dout0_x15_pins: tdma_dout0_x15 {
|
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mux {
|
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groups = "tdma_dout0_x15";
|
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function = "tdma";
|
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};
|
||||
};
|
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tdma_dout1_pins: tdma_dout1 {
|
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mux {
|
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groups = "tdma_dout1";
|
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function = "tdma";
|
||||
};
|
||||
};
|
||||
|
||||
tdma_din1_pins: tdma_din1 {
|
||||
mux {
|
||||
groups = "tdma_din1";
|
||||
function = "tdma";
|
||||
};
|
||||
};
|
||||
|
||||
tdmb_sclk_pins: tdmb_sclk {
|
||||
mux {
|
||||
groups = "tdmb_sclk";
|
||||
function = "tdmb";
|
||||
};
|
||||
};
|
||||
|
||||
tdmb_sclk_slv_pins: tdmb_sclk_slv {
|
||||
mux {
|
||||
groups = "tdmb_sclk_slv";
|
||||
function = "tdmb";
|
||||
};
|
||||
};
|
||||
|
||||
tdmb_fs_pins: tdmb_fs {
|
||||
mux {
|
||||
groups = "tdmb_fs";
|
||||
function = "tdmb";
|
||||
};
|
||||
};
|
||||
|
||||
tdmb_fs_slv_pins: tdmb_fs_slv {
|
||||
mux {
|
||||
groups = "tdmb_fs_slv";
|
||||
function = "tdmb";
|
||||
};
|
||||
};
|
||||
|
||||
tdmb_din0_pins: tdmb_din0 {
|
||||
mux {
|
||||
groups = "tdmb_din0";
|
||||
function = "tdmb";
|
||||
};
|
||||
};
|
||||
|
||||
tdmb_dout0_pins: tdmb_dout0 {
|
||||
mux {
|
||||
groups = "tdmb_dout0";
|
||||
function = "tdmb";
|
||||
};
|
||||
};
|
||||
|
||||
tdmb_din1_pins: tdmb_din1 {
|
||||
mux {
|
||||
groups = "tdmb_din1";
|
||||
function = "tdmb";
|
||||
};
|
||||
};
|
||||
|
||||
tdmb_dout1_pins: tdmb_dout1 {
|
||||
mux {
|
||||
groups = "tdmb_dout1";
|
||||
function = "tdmb";
|
||||
};
|
||||
};
|
||||
|
||||
tdmb_din2_pins: tdmb_din2 {
|
||||
mux {
|
||||
groups = "tdmb_din2";
|
||||
function = "tdmb";
|
||||
};
|
||||
};
|
||||
|
||||
tdmb_dout2_pins: tdmb_dout2 {
|
||||
mux {
|
||||
groups = "tdmb_dout2";
|
||||
function = "tdmb";
|
||||
};
|
||||
};
|
||||
|
||||
tdmb_din3_pins: tdmb_din3 {
|
||||
mux {
|
||||
groups = "tdmb_din3";
|
||||
function = "tdmb";
|
||||
};
|
||||
};
|
||||
|
||||
tdmb_dout3_pins: tdmb_dout3 {
|
||||
mux {
|
||||
groups = "tdmb_dout3";
|
||||
function = "tdmb";
|
||||
};
|
||||
};
|
||||
|
||||
tdmc_sclk_pins: tdmc_sclk {
|
||||
mux {
|
||||
groups = "tdmc_sclk";
|
||||
function = "tdmc";
|
||||
};
|
||||
};
|
||||
|
||||
tdmc_sclk_slv_pins: tdmc_sclk_slv {
|
||||
mux {
|
||||
groups = "tdmc_sclk_slv";
|
||||
function = "tdmc";
|
||||
};
|
||||
};
|
||||
|
||||
tdmc_fs_pins: tdmc_fs {
|
||||
mux {
|
||||
groups = "tdmc_fs";
|
||||
function = "tdmc";
|
||||
};
|
||||
};
|
||||
|
||||
tdmc_fs_slv_pins: tdmc_fs_slv {
|
||||
mux {
|
||||
groups = "tdmc_fs_slv";
|
||||
function = "tdmc";
|
||||
};
|
||||
};
|
||||
|
||||
tdmc_din0_pins: tdmc_din0 {
|
||||
mux {
|
||||
groups = "tdmc_din0";
|
||||
function = "tdmc";
|
||||
};
|
||||
};
|
||||
|
||||
tdmc_dout0_pins: tdmc_dout0 {
|
||||
mux {
|
||||
groups = "tdmc_dout0";
|
||||
function = "tdmc";
|
||||
};
|
||||
};
|
||||
|
||||
tdmc_din1_pins: tdmc_din1 {
|
||||
mux {
|
||||
groups = "tdmc_din1";
|
||||
function = "tdmc";
|
||||
};
|
||||
};
|
||||
|
||||
tdmc_dout1_pins: tdmc_dout1 {
|
||||
mux {
|
||||
groups = "tdmc_dout1";
|
||||
function = "tdmc";
|
||||
};
|
||||
};
|
||||
|
||||
tdmc_din2_pins: tdmc_din2 {
|
||||
mux {
|
||||
groups = "tdmc_din2";
|
||||
function = "tdmc";
|
||||
};
|
||||
};
|
||||
|
||||
tdmc_dout2_pins: tdmc_dout2 {
|
||||
mux {
|
||||
groups = "tdmc_dout2";
|
||||
function = "tdmc";
|
||||
};
|
||||
};
|
||||
|
||||
tdmc_din3_pins: tdmc_din3 {
|
||||
mux {
|
||||
groups = "tdmc_din3";
|
||||
function = "tdmc";
|
||||
};
|
||||
};
|
||||
|
||||
tdmc_dout3_pins: tdmc_dout3 {
|
||||
mux {
|
||||
groups = "tdmc_dout3";
|
||||
function = "tdmc";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -307,11 +307,10 @@
|
||||
clock-names = "isfr", "iahb", "venci";
|
||||
};
|
||||
|
||||
&hiubus {
|
||||
clkc: clock-controller@0 {
|
||||
&sysctrl {
|
||||
clkc: clock-controller {
|
||||
compatible = "amlogic,gxbb-clkc";
|
||||
#clock-cells = <1>;
|
||||
reg = <0x0 0x0 0x0 0x3db>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -716,6 +715,7 @@
|
||||
<&clkc CLKID_SD_EMMC_A_CLK0>,
|
||||
<&clkc CLKID_FCLK_DIV2>;
|
||||
clock-names = "core", "clkin0", "clkin1";
|
||||
resets = <&reset RESET_SD_EMMC_A>;
|
||||
};
|
||||
|
||||
&sd_emmc_b {
|
||||
@ -723,6 +723,7 @@
|
||||
<&clkc CLKID_SD_EMMC_B_CLK0>,
|
||||
<&clkc CLKID_FCLK_DIV2>;
|
||||
clock-names = "core", "clkin0", "clkin1";
|
||||
resets = <&reset RESET_SD_EMMC_B>;
|
||||
};
|
||||
|
||||
&sd_emmc_c {
|
||||
@ -730,6 +731,7 @@
|
||||
<&clkc CLKID_SD_EMMC_C_CLK0>,
|
||||
<&clkc CLKID_FCLK_DIV2>;
|
||||
clock-names = "core", "clkin0", "clkin1";
|
||||
resets = <&reset RESET_SD_EMMC_C>;
|
||||
};
|
||||
|
||||
&spicc {
|
||||
|
||||
@ -267,11 +267,10 @@
|
||||
clock-names = "isfr", "iahb", "venci";
|
||||
};
|
||||
|
||||
&hiubus {
|
||||
clkc: clock-controller@0 {
|
||||
compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
|
||||
&sysctrl {
|
||||
clkc: clock-controller {
|
||||
compatible = "amlogic,gxl-clkc";
|
||||
#clock-cells = <1>;
|
||||
reg = <0x0 0x0 0x0 0x3db>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -725,13 +724,15 @@
|
||||
<&clkc CLKID_SD_EMMC_A_CLK0>,
|
||||
<&clkc CLKID_FCLK_DIV2>;
|
||||
clock-names = "core", "clkin0", "clkin1";
|
||||
resets = <&reset RESET_SD_EMMC_A>;
|
||||
};
|
||||
|
||||
&sd_emmc_b {
|
||||
clocks = <&clkc CLKID_SD_EMMC_B>,
|
||||
<&clkc CLKID_SD_EMMC_B_CLK0>,
|
||||
<&clkc CLKID_FCLK_DIV2>;
|
||||
clock-names = "core", "clkin0", "clkin1";
|
||||
clock-names = "core", "clkin0", "clkin1";
|
||||
resets = <&reset RESET_SD_EMMC_B>;
|
||||
};
|
||||
|
||||
&sd_emmc_c {
|
||||
@ -739,6 +740,7 @@
|
||||
<&clkc CLKID_SD_EMMC_C_CLK0>,
|
||||
<&clkc CLKID_FCLK_DIV2>;
|
||||
clock-names = "core", "clkin0", "clkin1";
|
||||
resets = <&reset RESET_SD_EMMC_C>;
|
||||
};
|
||||
|
||||
&spicc {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user