drm/i915: Move intel_plane_atomic_calc_changes() & co. out
Exfiltrate intel_plane_atomic_calc_changes() and its friends from intel_display.c to intel_atomic_plane.c since that is a much better fit. While at it also nuke the official looking kernel docs for intel_wm_need_update() and flag it for eventual destruction so that people don't get any wrong ideas about using it in new code. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220211090629.15555-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Ville Syrjälä
parent
a6e7a006f5
commit
c17897428e
@ -45,6 +45,7 @@
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#include "intel_fb_pin.h"
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#include "intel_fb_pin.h"
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#include "intel_pm.h"
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#include "intel_pm.h"
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#include "intel_sprite.h"
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#include "intel_sprite.h"
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#include "skl_scaler.h"
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static void intel_plane_state_reset(struct intel_plane_state *plane_state,
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static void intel_plane_state_reset(struct intel_plane_state *plane_state,
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struct intel_plane *plane)
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struct intel_plane *plane)
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@ -330,6 +331,185 @@ void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
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plane_state->uapi.visible = false;
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plane_state->uapi.visible = false;
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}
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}
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/* FIXME nuke when all wm code is atomic */
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static bool intel_wm_need_update(const struct intel_plane_state *cur,
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struct intel_plane_state *new)
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{
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/* Update watermarks on tiling or size changes. */
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if (new->uapi.visible != cur->uapi.visible)
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return true;
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if (!cur->hw.fb || !new->hw.fb)
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return false;
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if (cur->hw.fb->modifier != new->hw.fb->modifier ||
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cur->hw.rotation != new->hw.rotation ||
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drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
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drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
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drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
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drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
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return true;
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return false;
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}
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static bool intel_plane_is_scaled(const struct intel_plane_state *plane_state)
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{
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int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
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int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
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int dst_w = drm_rect_width(&plane_state->uapi.dst);
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int dst_h = drm_rect_height(&plane_state->uapi.dst);
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return src_w != dst_w || src_h != dst_h;
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}
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static bool intel_plane_do_async_flip(struct intel_plane *plane,
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const struct intel_crtc_state *old_crtc_state,
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const struct intel_crtc_state *new_crtc_state)
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{
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struct drm_i915_private *i915 = to_i915(plane->base.dev);
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if (!plane->async_flip)
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return false;
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if (!new_crtc_state->uapi.async_flip)
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return false;
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/*
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* In platforms after DISPLAY13, we might need to override
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* first async flip in order to change watermark levels
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* as part of optimization.
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* So for those, we are checking if this is a first async flip.
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* For platforms earlier than DISPLAY13 we always do async flip.
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*/
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return DISPLAY_VER(i915) < 13 || old_crtc_state->uapi.async_flip;
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}
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static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
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struct intel_crtc_state *new_crtc_state,
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const struct intel_plane_state *old_plane_state,
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struct intel_plane_state *new_plane_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
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struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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bool mode_changed = intel_crtc_needs_modeset(new_crtc_state);
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bool was_crtc_enabled = old_crtc_state->hw.active;
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bool is_crtc_enabled = new_crtc_state->hw.active;
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bool turn_off, turn_on, visible, was_visible;
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int ret;
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if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
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ret = skl_update_scaler_plane(new_crtc_state, new_plane_state);
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if (ret)
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return ret;
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}
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was_visible = old_plane_state->uapi.visible;
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visible = new_plane_state->uapi.visible;
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if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))
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was_visible = false;
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/*
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* Visibility is calculated as if the crtc was on, but
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* after scaler setup everything depends on it being off
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* when the crtc isn't active.
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*
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* FIXME this is wrong for watermarks. Watermarks should also
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* be computed as if the pipe would be active. Perhaps move
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* per-plane wm computation to the .check_plane() hook, and
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* only combine the results from all planes in the current place?
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*/
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if (!is_crtc_enabled) {
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intel_plane_set_invisible(new_crtc_state, new_plane_state);
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visible = false;
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}
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if (!was_visible && !visible)
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return 0;
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turn_off = was_visible && (!visible || mode_changed);
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turn_on = visible && (!was_visible || mode_changed);
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drm_dbg_atomic(&dev_priv->drm,
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"[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
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crtc->base.base.id, crtc->base.name,
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plane->base.base.id, plane->base.name,
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was_visible, visible,
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turn_off, turn_on, mode_changed);
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if (turn_on) {
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if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
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new_crtc_state->update_wm_pre = true;
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/* must disable cxsr around plane enable/disable */
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if (plane->id != PLANE_CURSOR)
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new_crtc_state->disable_cxsr = true;
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} else if (turn_off) {
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if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
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new_crtc_state->update_wm_post = true;
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/* must disable cxsr around plane enable/disable */
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if (plane->id != PLANE_CURSOR)
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new_crtc_state->disable_cxsr = true;
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} else if (intel_wm_need_update(old_plane_state, new_plane_state)) {
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if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) {
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/* FIXME bollocks */
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new_crtc_state->update_wm_pre = true;
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new_crtc_state->update_wm_post = true;
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}
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}
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if (visible || was_visible)
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new_crtc_state->fb_bits |= plane->frontbuffer_bit;
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/*
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* ILK/SNB DVSACNTR/Sprite Enable
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* IVB SPR_CTL/Sprite Enable
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* "When in Self Refresh Big FIFO mode, a write to enable the
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* plane will be internally buffered and delayed while Big FIFO
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* mode is exiting."
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*
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* Which means that enabling the sprite can take an extra frame
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* when we start in big FIFO mode (LP1+). Thus we need to drop
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* down to LP0 and wait for vblank in order to make sure the
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* sprite gets enabled on the next vblank after the register write.
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* Doing otherwise would risk enabling the sprite one frame after
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* we've already signalled flip completion. We can resume LP1+
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* once the sprite has been enabled.
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*
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*
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* WaCxSRDisabledForSpriteScaling:ivb
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* IVB SPR_SCALE/Scaling Enable
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* "Low Power watermarks must be disabled for at least one
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* frame before enabling sprite scaling, and kept disabled
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* until sprite scaling is disabled."
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*
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* ILK/SNB DVSASCALE/Scaling Enable
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* "When in Self Refresh Big FIFO mode, scaling enable will be
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* masked off while Big FIFO mode is exiting."
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*
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* Despite the w/a only being listed for IVB we assume that
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* the ILK/SNB note has similar ramifications, hence we apply
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* the w/a on all three platforms.
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*
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* With experimental results seems this is needed also for primary
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* plane, not only sprite plane.
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*/
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if (plane->id != PLANE_CURSOR &&
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(IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv) ||
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IS_IVYBRIDGE(dev_priv)) &&
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(turn_on || (!intel_plane_is_scaled(old_plane_state) &&
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intel_plane_is_scaled(new_plane_state))))
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new_crtc_state->disable_lp_wm = true;
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if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state))
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new_plane_state->do_async_flip = true;
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return 0;
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}
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int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
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int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
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struct intel_crtc_state *new_crtc_state,
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struct intel_crtc_state *new_crtc_state,
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const struct intel_plane_state *old_plane_state,
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const struct intel_plane_state *old_plane_state,
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@ -56,10 +56,6 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
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struct intel_plane_state *intel_state);
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struct intel_plane_state *intel_state);
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int intel_plane_atomic_check(struct intel_atomic_state *state,
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int intel_plane_atomic_check(struct intel_atomic_state *state,
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struct intel_plane *plane);
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struct intel_plane *plane);
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int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
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struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *old_plane_state,
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struct intel_plane_state *plane_state);
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int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
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int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
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struct intel_plane *plane,
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struct intel_plane *plane,
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bool *need_cdclk_calc);
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bool *need_cdclk_calc);
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@ -4668,194 +4668,6 @@ intel_encoder_current_mode(struct intel_encoder *encoder)
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return mode;
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return mode;
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}
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}
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/**
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* intel_wm_need_update - Check whether watermarks need updating
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* @cur: current plane state
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* @new: new plane state
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*
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* Check current plane state versus the new one to determine whether
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* watermarks need to be recalculated.
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*
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* Returns true or false.
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*/
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static bool intel_wm_need_update(const struct intel_plane_state *cur,
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struct intel_plane_state *new)
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{
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/* Update watermarks on tiling or size changes. */
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if (new->uapi.visible != cur->uapi.visible)
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return true;
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if (!cur->hw.fb || !new->hw.fb)
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return false;
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if (cur->hw.fb->modifier != new->hw.fb->modifier ||
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cur->hw.rotation != new->hw.rotation ||
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drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
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drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
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drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
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drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
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return true;
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return false;
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}
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static bool needs_scaling(const struct intel_plane_state *state)
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{
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int src_w = drm_rect_width(&state->uapi.src) >> 16;
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int src_h = drm_rect_height(&state->uapi.src) >> 16;
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int dst_w = drm_rect_width(&state->uapi.dst);
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int dst_h = drm_rect_height(&state->uapi.dst);
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return (src_w != dst_w || src_h != dst_h);
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}
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static bool intel_plane_do_async_flip(struct intel_plane *plane,
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const struct intel_crtc_state *old_crtc_state,
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const struct intel_crtc_state *new_crtc_state)
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{
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struct drm_i915_private *i915 = to_i915(plane->base.dev);
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if (!plane->async_flip)
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return false;
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if (!new_crtc_state->uapi.async_flip)
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return false;
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/*
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* In platforms after DISPLAY13, we might need to override
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* first async flip in order to change watermark levels
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* as part of optimization.
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* So for those, we are checking if this is a first async flip.
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* For platforms earlier than DISPLAY13 we always do async flip.
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*/
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return DISPLAY_VER(i915) < 13 || old_crtc_state->uapi.async_flip;
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}
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int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
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struct intel_crtc_state *new_crtc_state,
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const struct intel_plane_state *old_plane_state,
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struct intel_plane_state *new_plane_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
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struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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bool mode_changed = intel_crtc_needs_modeset(new_crtc_state);
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bool was_crtc_enabled = old_crtc_state->hw.active;
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bool is_crtc_enabled = new_crtc_state->hw.active;
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bool turn_off, turn_on, visible, was_visible;
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int ret;
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if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
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ret = skl_update_scaler_plane(new_crtc_state, new_plane_state);
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if (ret)
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return ret;
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}
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was_visible = old_plane_state->uapi.visible;
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visible = new_plane_state->uapi.visible;
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if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))
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was_visible = false;
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/*
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* Visibility is calculated as if the crtc was on, but
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* after scaler setup everything depends on it being off
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* when the crtc isn't active.
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*
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* FIXME this is wrong for watermarks. Watermarks should also
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* be computed as if the pipe would be active. Perhaps move
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* per-plane wm computation to the .check_plane() hook, and
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* only combine the results from all planes in the current place?
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*/
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if (!is_crtc_enabled) {
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intel_plane_set_invisible(new_crtc_state, new_plane_state);
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visible = false;
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}
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if (!was_visible && !visible)
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return 0;
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turn_off = was_visible && (!visible || mode_changed);
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turn_on = visible && (!was_visible || mode_changed);
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drm_dbg_atomic(&dev_priv->drm,
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"[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
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crtc->base.base.id, crtc->base.name,
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plane->base.base.id, plane->base.name,
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was_visible, visible,
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turn_off, turn_on, mode_changed);
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if (turn_on) {
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|
||||||
if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
|
|
||||||
new_crtc_state->update_wm_pre = true;
|
|
||||||
|
|
||||||
/* must disable cxsr around plane enable/disable */
|
|
||||||
if (plane->id != PLANE_CURSOR)
|
|
||||||
new_crtc_state->disable_cxsr = true;
|
|
||||||
} else if (turn_off) {
|
|
||||||
if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
|
|
||||||
new_crtc_state->update_wm_post = true;
|
|
||||||
|
|
||||||
/* must disable cxsr around plane enable/disable */
|
|
||||||
if (plane->id != PLANE_CURSOR)
|
|
||||||
new_crtc_state->disable_cxsr = true;
|
|
||||||
} else if (intel_wm_need_update(old_plane_state, new_plane_state)) {
|
|
||||||
if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) {
|
|
||||||
/* FIXME bollocks */
|
|
||||||
new_crtc_state->update_wm_pre = true;
|
|
||||||
new_crtc_state->update_wm_post = true;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
if (visible || was_visible)
|
|
||||||
new_crtc_state->fb_bits |= plane->frontbuffer_bit;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* ILK/SNB DVSACNTR/Sprite Enable
|
|
||||||
* IVB SPR_CTL/Sprite Enable
|
|
||||||
* "When in Self Refresh Big FIFO mode, a write to enable the
|
|
||||||
* plane will be internally buffered and delayed while Big FIFO
|
|
||||||
* mode is exiting."
|
|
||||||
*
|
|
||||||
* Which means that enabling the sprite can take an extra frame
|
|
||||||
* when we start in big FIFO mode (LP1+). Thus we need to drop
|
|
||||||
* down to LP0 and wait for vblank in order to make sure the
|
|
||||||
* sprite gets enabled on the next vblank after the register write.
|
|
||||||
* Doing otherwise would risk enabling the sprite one frame after
|
|
||||||
* we've already signalled flip completion. We can resume LP1+
|
|
||||||
* once the sprite has been enabled.
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* WaCxSRDisabledForSpriteScaling:ivb
|
|
||||||
* IVB SPR_SCALE/Scaling Enable
|
|
||||||
* "Low Power watermarks must be disabled for at least one
|
|
||||||
* frame before enabling sprite scaling, and kept disabled
|
|
||||||
* until sprite scaling is disabled."
|
|
||||||
*
|
|
||||||
* ILK/SNB DVSASCALE/Scaling Enable
|
|
||||||
* "When in Self Refresh Big FIFO mode, scaling enable will be
|
|
||||||
* masked off while Big FIFO mode is exiting."
|
|
||||||
*
|
|
||||||
* Despite the w/a only being listed for IVB we assume that
|
|
||||||
* the ILK/SNB note has similar ramifications, hence we apply
|
|
||||||
* the w/a on all three platforms.
|
|
||||||
*
|
|
||||||
* With experimental results seems this is needed also for primary
|
|
||||||
* plane, not only sprite plane.
|
|
||||||
*/
|
|
||||||
if (plane->id != PLANE_CURSOR &&
|
|
||||||
(IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv) ||
|
|
||||||
IS_IVYBRIDGE(dev_priv)) &&
|
|
||||||
(turn_on || (!needs_scaling(old_plane_state) &&
|
|
||||||
needs_scaling(new_plane_state))))
|
|
||||||
new_crtc_state->disable_lp_wm = true;
|
|
||||||
|
|
||||||
if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state))
|
|
||||||
new_plane_state->do_async_flip = true;
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static bool encoders_cloneable(const struct intel_encoder *a,
|
static bool encoders_cloneable(const struct intel_encoder *a,
|
||||||
const struct intel_encoder *b)
|
const struct intel_encoder *b)
|
||||||
{
|
{
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user