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powerpc/32: Merge the new memset() with the old one

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cacheable_memzero() which has become the new memset() and the old
memset() are quite similar, so just merge them.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
LEROY Christophe 2015-05-19 12:07:52 +02:00 committed by Scott Wood
parent 5b2a32e806
commit c152f149ce
1 changed files with 7 additions and 27 deletions
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34
arch/powerpc/lib/copy_32.S
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@ -75,8 +75,9 @@ CACHELINE_MASK = (L1_CACHE_BYTES-1)
* area is cacheable. -- paulus * area is cacheable. -- paulus
*/ */
_GLOBAL(memset) _GLOBAL(memset)
cmplwi r4,0 rlwimi r4,r4,8,16,23
bne- generic_memset rlwimi r4,r4,16,0,15
addi r6,r3,-4 addi r6,r3,-4
cmplwi 0,r5,4 cmplwi 0,r5,4
blt 7f blt 7f
@ -85,6 +86,9 @@ _GLOBAL(memset)
andi. r0,r6,3 andi. r0,r6,3
add r5,r0,r5 add r5,r0,r5
subf r6,r0,r6 subf r6,r0,r6
cmplwi 0,r4,0
bne 2f /* Use normal procedure if r4 is not zero */
clrlwi r7,r6,32-LG_CACHELINE_BYTES clrlwi r7,r6,32-LG_CACHELINE_BYTES
add r8,r7,r5 add r8,r7,r5
srwi r9,r8,LG_CACHELINE_BYTES srwi r9,r8,LG_CACHELINE_BYTES
@ -103,32 +107,8 @@ _GLOBAL(memset)
bdnz 10b bdnz 10b
clrlwi r5,r8,32-LG_CACHELINE_BYTES clrlwi r5,r8,32-LG_CACHELINE_BYTES
addi r5,r5,4 addi r5,r5,4
2: srwi r0,r5,2
mtctr r0
bdz 6f
1: stwu r4,4(r6)
bdnz 1b
6: andi. r5,r5,3
7: cmpwi 0,r5,0
beqlr
mtctr r5
addi r6,r6,3
8: stbu r4,1(r6)
bdnz 8b
blr
_GLOBAL(generic_memset) 2: srwi r0,r5,2
rlwimi r4,r4,8,16,23
rlwimi r4,r4,16,0,15
addi r6,r3,-4
cmplwi 0,r5,4
blt 7f
stwu r4,4(r6)
beqlr
andi. r0,r6,3
add r5,r0,r5
subf r6,r0,r6
srwi r0,r5,2
mtctr r0 mtctr r0
bdz 6f bdz 6f
1: stwu r4,4(r6) 1: stwu r4,4(r6)