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amdgpu/dc: another round of dce/dcn construct cleanups.

Browse Source 
This removes any remaining pointless return codepaths from the
DCE code.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dave Airlie
2017-09-29 14:34:39 +10:00
committed by Alex Deucher
parent 0e1c42fd18
commit c13b408b81
32 changed files with 47 additions and 108 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
View File

@@ -142,13 +142,11 @@ void dce100_set_bandwidth(
/**************************************************************************/ /**************************************************************************/
bool dce100_hw_sequencer_construct(struct dc *dc) void dce100_hw_sequencer_construct(struct dc *dc)
{ {
dce110_hw_sequencer_construct(dc); dce110_hw_sequencer_construct(dc);
dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating; dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
dc->hwss.set_bandwidth = dce100_set_bandwidth; dc->hwss.set_bandwidth = dce100_set_bandwidth;
return true;
} }

2
drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h
View File

@@ -31,7 +31,7 @@
struct dc; struct dc;
struct dc_state; struct dc_state;
bool dce100_hw_sequencer_construct(struct dc *dc); void dce100_hw_sequencer_construct(struct dc *dc);
void dce100_set_bandwidth( void dce100_set_bandwidth(
struct dc *dc, struct dc *dc,

4
drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
View File

@@ -909,9 +909,7 @@ static bool construct(
goto res_create_fail; goto res_create_fail;
/* Create hardware sequencer */ /* Create hardware sequencer */
if (!dce100_hw_sequencer_construct(dc)) dce100_hw_sequencer_construct(dc);
goto res_create_fail;
return true; return true;
res_create_fail: res_create_fail:

11
drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
View File

@@ -393,12 +393,8 @@ struct compressor *dce110_compressor_create(struct dc_context *ctx)
if (!cp110) if (!cp110)
return NULL; return NULL;
if (dce110_compressor_construct(cp110, ctx)) dce110_compressor_construct(cp110, ctx);
return &cp110->base; return &cp110->base;
BREAK_TO_DEBUGGER();
kfree(cp110);
return NULL;
} }
void dce110_compressor_destroy(struct compressor **compressor) void dce110_compressor_destroy(struct compressor **compressor)
@@ -485,7 +481,7 @@ static const struct compressor_funcs dce110_compressor_funcs = {
}; };
bool dce110_compressor_construct(struct dce110_compressor *compressor, void dce110_compressor_construct(struct dce110_compressor *compressor,
struct dc_context *ctx) struct dc_context *ctx)
{ {
@@ -522,6 +518,5 @@ bool dce110_compressor_construct(struct dce110_compressor *compressor,
compressor->base.funcs = &dce110_compressor_funcs; compressor->base.funcs = &dce110_compressor_funcs;
#endif #endif
return true;
} }

2
drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h
View File

@@ -42,7 +42,7 @@ struct dce110_compressor {
struct compressor *dce110_compressor_create(struct dc_context *ctx); struct compressor *dce110_compressor_create(struct dc_context *ctx);
bool dce110_compressor_construct(struct dce110_compressor *cp110, void dce110_compressor_construct(struct dce110_compressor *cp110,
struct dc_context *ctx); struct dc_context *ctx);
void dce110_compressor_destroy(struct compressor **cp); void dce110_compressor_destroy(struct compressor **cp);

4
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
View File

@@ -2723,10 +2723,8 @@ static const struct hw_sequencer_funcs dce110_funcs = {
}; };
bool dce110_hw_sequencer_construct(struct dc *dc) void dce110_hw_sequencer_construct(struct dc *dc)
{ {
dc->hwss = dce110_funcs; dc->hwss = dce110_funcs;
return true;
} }

2
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
View File

@@ -33,7 +33,7 @@ struct dc;
struct dc_state; struct dc_state;
struct dm_pp_display_configuration; struct dm_pp_display_configuration;
bool dce110_hw_sequencer_construct(struct dc *dc); void dce110_hw_sequencer_construct(struct dc *dc);
enum dc_status dce110_apply_ctx_to_hw( enum dc_status dce110_apply_ctx_to_hw(
struct dc *dc, struct dc *dc,

4
drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c
View File

@@ -44,13 +44,11 @@ static const struct opp_funcs funcs = {
dce110_opp_program_bit_depth_reduction dce110_opp_program_bit_depth_reduction
}; };
bool dce110_opp_v_construct(struct dce110_opp *opp110, void dce110_opp_v_construct(struct dce110_opp *opp110,
struct dc_context *ctx) struct dc_context *ctx)
{ {
opp110->base.funcs = &funcs; opp110->base.funcs = &funcs;
opp110->base.ctx = ctx; opp110->base.ctx = ctx;
return true;
} }

2
drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h
View File

@@ -29,7 +29,7 @@
#include "opp.h" #include "opp.h"
#include "core_types.h" #include "core_types.h"
bool dce110_opp_v_construct(struct dce110_opp *opp110, void dce110_opp_v_construct(struct dce110_opp *opp110,
struct dc_context *ctx); struct dc_context *ctx);
/* underlay callbacks */ /* underlay callbacks */

6
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
View File

@@ -1041,8 +1041,7 @@ static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool)
(dce110_oppv == NULL)) (dce110_oppv == NULL))
return false; return false;
if (!dce110_opp_v_construct(dce110_oppv, ctx)) dce110_opp_v_construct(dce110_oppv, ctx);
return false;
dce110_timing_generator_v_construct(dce110_tgv, ctx); dce110_timing_generator_v_construct(dce110_tgv, ctx);
dce110_mem_input_v_construct(dce110_miv, ctx); dce110_mem_input_v_construct(dce110_miv, ctx);
@@ -1292,8 +1291,7 @@ static bool construct(
goto res_create_fail; goto res_create_fail;
/* Create hardware sequencer */ /* Create hardware sequencer */
if (!dce110_hw_sequencer_construct(dc)) dce110_hw_sequencer_construct(dc);
goto res_create_fail;
dc->caps.max_planes = pool->base.pipe_count; dc->caps.max_planes = pool->base.pipe_count;

7
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
View File

@@ -668,13 +668,10 @@ static const struct timing_generator_funcs dce110_tg_v_funcs = {
dce110_timing_generator_v_enable_advanced_request dce110_timing_generator_v_enable_advanced_request
}; };
bool dce110_timing_generator_v_construct( void dce110_timing_generator_v_construct(
struct dce110_timing_generator *tg110, struct dce110_timing_generator *tg110,
struct dc_context *ctx) struct dc_context *ctx)
{ {
if (!tg110)
return false;
tg110->controller_id = CONTROLLER_ID_UNDERLAY0; tg110->controller_id = CONTROLLER_ID_UNDERLAY0;
tg110->base.funcs = &dce110_tg_v_funcs; tg110->base.funcs = &dce110_tg_v_funcs;
@@ -688,6 +685,4 @@ bool dce110_timing_generator_v_construct(
tg110->min_h_blank = 56; tg110->min_h_blank = 56;
tg110->min_h_front_porch = 4; tg110->min_h_front_porch = 4;
tg110->min_h_back_porch = 4; tg110->min_h_back_porch = 4;
return true;
} }

2
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.h
View File

@@ -26,7 +26,7 @@
#ifndef __DC_TIMING_GENERATOR_V_DCE110_H__ #ifndef __DC_TIMING_GENERATOR_V_DCE110_H__
#define __DC_TIMING_GENERATOR_V_DCE110_H__ #define __DC_TIMING_GENERATOR_V_DCE110_H__
bool dce110_timing_generator_v_construct( void dce110_timing_generator_v_construct(
struct dce110_timing_generator *tg110, struct dce110_timing_generator *tg110,
struct dc_context *ctx); struct dc_context *ctx);

11
drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c
View File

@@ -791,7 +791,7 @@ void dce112_compressor_set_fbc_invalidation_triggers(
dm_write_reg(compressor->ctx, addr, value); dm_write_reg(compressor->ctx, addr, value);
} }
bool dce112_compressor_construct(struct dce112_compressor *compressor, void dce112_compressor_construct(struct dce112_compressor *compressor,
struct dc_context *ctx) struct dc_context *ctx)
{ {
struct dc_bios *bp = ctx->dc_bios; struct dc_bios *bp = ctx->dc_bios;
@@ -833,7 +833,6 @@ bool dce112_compressor_construct(struct dce112_compressor *compressor,
compressor->base.embedded_panel_v_size = compressor->base.embedded_panel_v_size =
panel_info.lcd_timing.vertical_addressable; panel_info.lcd_timing.vertical_addressable;
} }
return true;
} }
struct compressor *dce112_compressor_create(struct dc_context *ctx) struct compressor *dce112_compressor_create(struct dc_context *ctx)
@@ -844,12 +843,8 @@ struct compressor *dce112_compressor_create(struct dc_context *ctx)
if (!cp110) if (!cp110)
return NULL; return NULL;
if (dce112_compressor_construct(cp110, ctx)) dce112_compressor_construct(cp110, ctx);
return &cp110->base; return &cp110->base;
BREAK_TO_DEBUGGER();
kfree(cp110);
return NULL;
} }
void dce112_compressor_destroy(struct compressor **compressor) void dce112_compressor_destroy(struct compressor **compressor)

2
drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h
View File

@@ -42,7 +42,7 @@ struct dce112_compressor {
struct compressor *dce112_compressor_create(struct dc_context *ctx); struct compressor *dce112_compressor_create(struct dc_context *ctx);
bool dce112_compressor_construct(struct dce112_compressor *cp110, void dce112_compressor_construct(struct dce112_compressor *cp110,
struct dc_context *ctx); struct dc_context *ctx);
void dce112_compressor_destroy(struct compressor **cp); void dce112_compressor_destroy(struct compressor **cp);

4
drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c
View File

@@ -152,14 +152,12 @@ static bool dce112_enable_display_power_gating(
return false; return false;
} }
bool dce112_hw_sequencer_construct(struct dc *dc) void dce112_hw_sequencer_construct(struct dc *dc)
{ {
/* All registers used by dce11.2 match those in dce11 in offset and /* All registers used by dce11.2 match those in dce11 in offset and
* structure * structure
*/ */
dce110_hw_sequencer_construct(dc); dce110_hw_sequencer_construct(dc);
dc->hwss.enable_display_power_gating = dce112_enable_display_power_gating; dc->hwss.enable_display_power_gating = dce112_enable_display_power_gating;
return true;
} }

2
drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h
View File

@@ -30,7 +30,7 @@
struct dc; struct dc;
bool dce112_hw_sequencer_construct(struct dc *dc); void dce112_hw_sequencer_construct(struct dc *dc);
#endif /* __DC_HWSS_DCE112_H__ */ #endif /* __DC_HWSS_DCE112_H__ */

3
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
View File

@@ -1256,8 +1256,7 @@ static bool construct(
dc->caps.max_planes = pool->base.pipe_count; dc->caps.max_planes = pool->base.pipe_count;
/* Create hardware sequencer */ /* Create hardware sequencer */
if (!dce112_hw_sequencer_construct(dc)) dce112_hw_sequencer_construct(dc);
goto res_create_fail;
bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);

4
drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
View File

@@ -245,7 +245,7 @@ static void dce120_update_dchub(
bool dce120_hw_sequencer_construct(struct dc *dc) void dce120_hw_sequencer_construct(struct dc *dc)
{ {
/* All registers used by dce11.2 match those in dce11 in offset and /* All registers used by dce11.2 match those in dce11 in offset and
* structure * structure
@@ -253,7 +253,5 @@ bool dce120_hw_sequencer_construct(struct dc *dc)
dce110_hw_sequencer_construct(dc); dce110_hw_sequencer_construct(dc);
dc->hwss.enable_display_power_gating = dce120_enable_display_power_gating; dc->hwss.enable_display_power_gating = dce120_enable_display_power_gating;
dc->hwss.update_dchub = dce120_update_dchub; dc->hwss.update_dchub = dce120_update_dchub;
return true;
} }

2
drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h
View File

@@ -30,7 +30,7 @@
struct dc; struct dc;
bool dce120_hw_sequencer_construct(struct dc *dc); void dce120_hw_sequencer_construct(struct dc *dc);
#endif /* __DC_HWSS_DCE112_H__ */ #endif /* __DC_HWSS_DCE112_H__ */

8
drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
View File

@@ -429,12 +429,8 @@ static struct timing_generator *dce120_timing_generator_create(
if (!tg110) if (!tg110)
return NULL; return NULL;
if (dce120_timing_generator_construct(tg110, ctx, instance, offsets)) dce120_timing_generator_construct(tg110, ctx, instance, offsets);
return &tg110->base; return &tg110->base;
BREAK_TO_DEBUGGER();
kfree(tg110);
return NULL;
} }
static void dce120_transform_destroy(struct transform **xfm) static void dce120_transform_destroy(struct transform **xfm)

7
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
View File

@@ -1143,15 +1143,12 @@ static const struct timing_generator_funcs dce120_tg_funcs = {
}; };
bool dce120_timing_generator_construct( void dce120_timing_generator_construct(
struct dce110_timing_generator *tg110, struct dce110_timing_generator *tg110,
struct dc_context *ctx, struct dc_context *ctx,
uint32_t instance, uint32_t instance,
const struct dce110_timing_generator_offsets *offsets) const struct dce110_timing_generator_offsets *offsets)
{ {
if (!tg110)
return false;
tg110->controller_id = CONTROLLER_ID_D0 + instance; tg110->controller_id = CONTROLLER_ID_D0 + instance;
tg110->base.inst = instance; tg110->base.inst = instance;
@@ -1175,6 +1172,4 @@ bool dce120_timing_generator_construct(
tg110->min_h_sync_width = 8; tg110->min_h_sync_width = 8;
tg110->min_v_sync_width = 1; tg110->min_v_sync_width = 1;
tg110->min_v_blank = 3; tg110->min_v_blank = 3;
return true;
} }

2
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.h
View File

@@ -32,7 +32,7 @@
#include "dce110/dce110_timing_generator.h" #include "dce110/dce110_timing_generator.h"
bool dce120_timing_generator_construct( void dce120_timing_generator_construct(
struct dce110_timing_generator *tg110, struct dce110_timing_generator *tg110,
struct dc_context *ctx, struct dc_context *ctx,
uint32_t instance, uint32_t instance,

11
drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c
View File

@@ -771,7 +771,7 @@ void dce80_compressor_set_fbc_invalidation_triggers(
dm_write_reg(compressor->ctx, addr, value); dm_write_reg(compressor->ctx, addr, value);
} }
bool dce80_compressor_construct(struct dce80_compressor *compressor, void dce80_compressor_construct(struct dce80_compressor *compressor,
struct dc_context *ctx) struct dc_context *ctx)
{ {
struct dc_bios *bp = ctx->dc_bios; struct dc_bios *bp = ctx->dc_bios;
@@ -813,7 +813,6 @@ bool dce80_compressor_construct(struct dce80_compressor *compressor,
compressor->base.embedded_panel_v_size = compressor->base.embedded_panel_v_size =
panel_info.lcd_timing.vertical_addressable; panel_info.lcd_timing.vertical_addressable;
} }
return true;
} }
struct compressor *dce80_compressor_create(struct dc_context *ctx) struct compressor *dce80_compressor_create(struct dc_context *ctx)
@@ -824,12 +823,8 @@ struct compressor *dce80_compressor_create(struct dc_context *ctx)
if (!cp80) if (!cp80)
return NULL; return NULL;
if (dce80_compressor_construct(cp80, ctx)) dce80_compressor_construct(cp80, ctx);
return &cp80->base; return &cp80->base;
BREAK_TO_DEBUGGER();
kfree(cp80);
return NULL;
} }
void dce80_compressor_destroy(struct compressor **compressor) void dce80_compressor_destroy(struct compressor **compressor)

2
drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.h
View File

@@ -42,7 +42,7 @@ struct dce80_compressor {
struct compressor *dce80_compressor_create(struct dc_context *ctx); struct compressor *dce80_compressor_create(struct dc_context *ctx);
bool dce80_compressor_construct(struct dce80_compressor *cp80, void dce80_compressor_construct(struct dce80_compressor *cp80,
struct dc_context *ctx); struct dc_context *ctx);
void dce80_compressor_destroy(struct compressor **cp); void dce80_compressor_destroy(struct compressor **cp);

4
drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c
View File

@@ -106,14 +106,12 @@ static bool dce80_enable_display_power_gating(
return false; return false;
} }
bool dce80_hw_sequencer_construct(struct dc *dc) void dce80_hw_sequencer_construct(struct dc *dc)
{ {
dce110_hw_sequencer_construct(dc); dce110_hw_sequencer_construct(dc);
dc->hwss.enable_display_power_gating = dce80_enable_display_power_gating; dc->hwss.enable_display_power_gating = dce80_enable_display_power_gating;
dc->hwss.pipe_control_lock = dce_pipe_control_lock; dc->hwss.pipe_control_lock = dce_pipe_control_lock;
dc->hwss.set_bandwidth = dce100_set_bandwidth; dc->hwss.set_bandwidth = dce100_set_bandwidth;
return true;
} }

2
drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h
View File

@@ -30,7 +30,7 @@
struct dc; struct dc;
bool dce80_hw_sequencer_construct(struct dc *dc); void dce80_hw_sequencer_construct(struct dc *dc);
#endif /* __DC_HWSS_DCE80_H__ */ #endif /* __DC_HWSS_DCE80_H__ */

9
drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
View File

@@ -910,8 +910,7 @@ static bool dce80_construct(
goto res_create_fail; goto res_create_fail;
/* Create hardware sequencer */ /* Create hardware sequencer */
if (!dce80_hw_sequencer_construct(dc)) dce80_hw_sequencer_construct(dc);
goto res_create_fail;
return true; return true;
@@ -1075,8 +1074,7 @@ static bool dce81_construct(
goto res_create_fail; goto res_create_fail;
/* Create hardware sequencer */ /* Create hardware sequencer */
if (!dce80_hw_sequencer_construct(dc)) dce80_hw_sequencer_construct(dc);
goto res_create_fail;
return true; return true;
@@ -1236,8 +1234,7 @@ static bool dce83_construct(
goto res_create_fail; goto res_create_fail;
/* Create hardware sequencer */ /* Create hardware sequencer */
if (!dce80_hw_sequencer_construct(dc)) dce80_hw_sequencer_construct(dc);
goto res_create_fail;
return true; return true;

4
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
View File

@@ -397,7 +397,7 @@ static const struct transform_funcs dcn10_dpp_funcs = {
/* Constructor, Destructor */ /* Constructor, Destructor */
/*****************************************/ /*****************************************/
bool dcn10_dpp_construct( void dcn10_dpp_construct(
struct dcn10_dpp *xfm, struct dcn10_dpp *xfm,
struct dc_context *ctx, struct dc_context *ctx,
uint32_t inst, uint32_t inst,
@@ -421,6 +421,4 @@ bool dcn10_dpp_construct(
xfm->lb_bits_per_entry = LB_BITS_PER_ENTRY; xfm->lb_bits_per_entry = LB_BITS_PER_ENTRY;
xfm->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/ xfm->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/
return true;
} }

2
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
View File

@@ -1356,7 +1356,7 @@ void ippn10_cnv_setup (
void ippn10_full_bypass(struct transform *xfm_base); void ippn10_full_bypass(struct transform *xfm_base);
bool dcn10_dpp_construct(struct dcn10_dpp *xfm110, void dcn10_dpp_construct(struct dcn10_dpp *xfm110,
struct dc_context *ctx, struct dc_context *ctx,
uint32_t inst, uint32_t inst,
const struct dcn_dpp_registers *tf_regs, const struct dcn_dpp_registers *tf_regs,

4
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
View File

@@ -786,7 +786,7 @@ static struct mem_input_funcs dcn10_mem_input_funcs = {
/* Constructor, Destructor */ /* Constructor, Destructor */
/*****************************************/ /*****************************************/
bool dcn10_mem_input_construct( void dcn10_mem_input_construct(
struct dcn10_mem_input *mi, struct dcn10_mem_input *mi,
struct dc_context *ctx, struct dc_context *ctx,
uint32_t inst, uint32_t inst,
@@ -802,7 +802,5 @@ bool dcn10_mem_input_construct(
mi->base.inst = inst; mi->base.inst = inst;
mi->base.opp_id = 0xf; mi->base.opp_id = 0xf;
mi->base.mpcc_id = 0xf; mi->base.mpcc_id = 0xf;
return true;
} }

2
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
View File

@@ -538,7 +538,7 @@ struct dcn10_mem_input {
const struct dcn_mi_mask *mi_mask; const struct dcn_mi_mask *mi_mask;
}; };
bool dcn10_mem_input_construct( void dcn10_mem_input_construct(
struct dcn10_mem_input *mi, struct dcn10_mem_input *mi,
struct dc_context *ctx, struct dc_context *ctx,
uint32_t inst, uint32_t inst,

20
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
View File

@@ -462,13 +462,9 @@ static struct transform *dcn10_dpp_create(
if (!dpp) if (!dpp)
return NULL; return NULL;
if (dcn10_dpp_construct(dpp, ctx, inst, dcn10_dpp_construct(dpp, ctx, inst,
&tf_regs[inst], &tf_shift, &tf_mask)) &tf_regs[inst], &tf_shift, &tf_mask);
return &dpp->base; return &dpp->base;
BREAK_TO_DEBUGGER();
kfree(dpp);
return NULL;
} }
static struct input_pixel_processor *dcn10_ipp_create( static struct input_pixel_processor *dcn10_ipp_create(
@@ -771,13 +767,9 @@ static struct mem_input *dcn10_mem_input_create(
if (!mem_inputn10) if (!mem_inputn10)
return NULL; return NULL;
if (dcn10_mem_input_construct(mem_inputn10, ctx, inst, dcn10_mem_input_construct(mem_inputn10, ctx, inst,
&mi_regs[inst], &mi_shift, &mi_mask)) &mi_regs[inst], &mi_shift, &mi_mask);
return &mem_inputn10->base; return &mem_inputn10->base;
BREAK_TO_DEBUGGER();
kfree(mem_inputn10);
return NULL;
} }
static void get_pixel_clock_parameters( static void get_pixel_clock_parameters(