arm64: Add level-hinted TLB invalidation helper
Add a level-hinted TLB invalidation helper that only gets used if ARMv8.4-TTL gets detected. Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
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@ -256,4 +256,13 @@ stage2_pgd_addr_end(struct kvm *kvm, phys_addr_t addr, phys_addr_t end)
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return (boundary - 1 < end - 1) ? boundary : end;
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}
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/*
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* Level values for the ARMv8.4-TTL extension, mapping PUD/PMD/PTE and
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* the architectural page-table level.
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*/
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#define S2_NO_LEVEL_HINT 0
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#define S2_PUD_LEVEL 1
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#define S2_PMD_LEVEL 2
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#define S2_PTE_LEVEL 3
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#endif /* __ARM64_S2_PGTABLE_H_ */
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@ -10,6 +10,7 @@
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#ifndef __ASSEMBLY__
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#include <linux/bitfield.h>
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#include <linux/mm_types.h>
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#include <linux/sched.h>
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#include <asm/cputype.h>
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@ -59,6 +60,50 @@
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__ta; \
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})
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/*
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* Level-based TLBI operations.
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*
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* When ARMv8.4-TTL exists, TLBI operations take an additional hint for
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* the level at which the invalidation must take place. If the level is
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* wrong, no invalidation may take place. In the case where the level
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* cannot be easily determined, a 0 value for the level parameter will
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* perform a non-hinted invalidation.
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*
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* For Stage-2 invalidation, use the level values provided to that effect
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* in asm/stage2_pgtable.h.
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*/
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#define TLBI_TTL_MASK GENMASK_ULL(47, 44)
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#define TLBI_TTL_TG_4K 1
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#define TLBI_TTL_TG_16K 2
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#define TLBI_TTL_TG_64K 3
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#define __tlbi_level(op, addr, level) \
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do { \
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u64 arg = addr; \
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\
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if (cpus_have_const_cap(ARM64_HAS_ARMv8_4_TTL) && \
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level) { \
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u64 ttl = level & 3; \
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\
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switch (PAGE_SIZE) { \
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case SZ_4K: \
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ttl |= TLBI_TTL_TG_4K << 2; \
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break; \
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case SZ_16K: \
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ttl |= TLBI_TTL_TG_16K << 2; \
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break; \
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case SZ_64K: \
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ttl |= TLBI_TTL_TG_64K << 2; \
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break; \
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} \
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\
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arg &= ~TLBI_TTL_MASK; \
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arg |= FIELD_PREP(TLBI_TTL_MASK, ttl); \
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} \
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\
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__tlbi(op, arg); \
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} while(0)
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/*
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* TLB Invalidation
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* ================
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