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irqchip: mips-cpu: Replace magic 0x100 with IE_SW0

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Replace use of the magic number 0x100 (ie. bit 8) with the more
explanatory IE_SW0 (ie. interrupt enable for software interrupt 0) or
C_SW0 (ie. cause bit for software interrupt 0) as appropriate.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/15834/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Paul Burton 2017-03-30 12:06:09 -07:00 committed by Ralf Baechle
parent ca452b95e3
commit c0cfbe6941
1 changed files with 4 additions and 4 deletions
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8
drivers/irqchip/irq-mips-cpu.c
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@ -41,13 +41,13 @@
static inline void unmask_mips_irq(struct irq_data *d) static inline void unmask_mips_irq(struct irq_data *d)
{ {
set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); set_c0_status(IE_SW0 << (d->irq - MIPS_CPU_IRQ_BASE));
irq_enable_hazard(); irq_enable_hazard();
} }
static inline void mask_mips_irq(struct irq_data *d) static inline void mask_mips_irq(struct irq_data *d)
{ {
clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); clear_c0_status(IE_SW0 << (d->irq - MIPS_CPU_IRQ_BASE));
irq_disable_hazard(); irq_disable_hazard();
} }
@ -70,7 +70,7 @@ static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
{ {
unsigned int vpflags = dvpe(); unsigned int vpflags = dvpe();
clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); clear_c0_cause(C_SW0 << (d->irq - MIPS_CPU_IRQ_BASE));
evpe(vpflags); evpe(vpflags);
unmask_mips_irq(d); unmask_mips_irq(d);
return 0; return 0;
@ -83,7 +83,7 @@ static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
static void mips_mt_cpu_irq_ack(struct irq_data *d) static void mips_mt_cpu_irq_ack(struct irq_data *d)
{ {
unsigned int vpflags = dvpe(); unsigned int vpflags = dvpe();
clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); clear_c0_cause(C_SW0 << (d->irq - MIPS_CPU_IRQ_BASE));
evpe(vpflags); evpe(vpflags);
mask_mips_irq(d); mask_mips_irq(d);
} }