media: dt-bindings: Update bindings for Cadence CSI2TX version 2.1
This patch adds a DT bindings documentation for Cadence CSI2TX v2.1 controller. Signed-off-by: Jan Kotas <jank@cadence.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
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@ -5,7 +5,8 @@ The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
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4 CSI lanes in output, and up to 4 different pixel streams in input.
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Required properties:
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- compatible: must be set to "cdns,csi2tx"
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- compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3"
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for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.1
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- reg: base address and size of the memory mapped region
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- clocks: phandles to the clocks driving the controller
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- clock-names: must contain:
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