forked from Minki/linux
ARM: dts: dra7: cpsw: fix clocks tree
Current clocks tree definition for CPSW/CPTS doesn't correspond TRM for dra7/am57 SoCs. CPTS: has to be sourced from gmac_rft_clk_mux clock CPSW: DPLL_GMAC -> CLKOUT_M2 -> GMAC_250M_CLK -> 1/2 -> -> GMAC_MAIN_CLK (125 MHZ) Hence, correct clock tree for GMAC_MAIN_CLK and use proper clock for CPTS. This also require updating of CPTS clock multiplier. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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dbb9c19632
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@ -1719,7 +1719,7 @@
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mac: ethernet@48484000 {
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compatible = "ti,dra7-cpsw","ti,cpsw";
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ti,hwmods = "gmac";
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clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
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clocks = <&gmac_main_clk>, <&gmac_rft_clk_mux>;
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clock-names = "fck", "cpts";
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cpdma_channels = <8>;
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ale_entries = <1024>;
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@ -1728,7 +1728,7 @@
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mac_control = <0x20>;
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slaves = <2>;
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active_slave = <0>;
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cpts_clock_mult = <0x80000000>;
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cpts_clock_mult = <0x784CFE14>;
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cpts_clock_shift = <29>;
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reg = <0x48484000 0x1000
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0x48485200 0x2E00>;
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@ -1003,6 +1003,14 @@
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ti,index-power-of-two;
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};
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gmac_main_clk: gmac_main_clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&gmac_250m_dclk_div>;
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clock-mult = <1>;
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clock-div = <2>;
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};
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l3init_480m_dclk_div: l3init_480m_dclk_div@1ac {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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@ -1726,14 +1734,6 @@
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reg = <0x13d0>;
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};
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gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_gmac_m2_ck>;
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clock-mult = <1>;
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clock-div = <2>;
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};
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gmac_rft_clk_mux: gmac_rft_clk_mux@13d0 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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