e1000e: ICHx/PCHx LOMs should use LPLU setting in NVM when going to Sx
When going to Sx with an ICHx/PCH device, the default Low Power Link Up (LPLU, a.k.a. reverse auto-negotiation) behavior should be whatever is set in the NVM. However, the function e1000_suspend_workarounds_ich8lan() called when going to Sx always enabled LPLU in all power states. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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@ -3698,9 +3698,10 @@ void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
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*
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*
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* During S0 to Sx transition, it is possible the link remains at gig
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* During S0 to Sx transition, it is possible the link remains at gig
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* instead of negotiating to a lower speed. Before going to Sx, set
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* instead of negotiating to a lower speed. Before going to Sx, set
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* 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
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* 'Gig Disable' to force link speed negotiation to a lower speed based on
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* to a lower speed. For PCH and newer parts, the OEM bits PHY register
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* the LPLU setting in the NVM or custom setting. For PCH and newer parts,
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* (LED, GbE disable and LPLU configurations) also needs to be written.
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* the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
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* needs to be written.
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**/
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**/
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void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
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void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
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{
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{
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@ -3708,7 +3709,7 @@ void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
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s32 ret_val;
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s32 ret_val;
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phy_ctrl = er32(PHY_CTRL);
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phy_ctrl = er32(PHY_CTRL);
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phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
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phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
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ew32(PHY_CTRL, phy_ctrl);
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ew32(PHY_CTRL, phy_ctrl);
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if (hw->mac.type == e1000_ich8lan)
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if (hw->mac.type == e1000_ich8lan)
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