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ARM: tegra: do v7_invalidate_l1 only when CPU is Cortex-A9

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The v7_invalidate_l1 was used for the L1 cache that come out from reset
in a undefined state. This is no need for Cortex-A15. We do it for A9
only.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
Joseph Lo 2013-07-03 17:50:37 +08:00 committed by Stephen Warren
parent 3045cb33eb
commit c04c77540a
2 changed files with 7 additions and 3 deletions
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3
arch/arm/mach-tegra/headsmp.S
View File

@ -6,6 +6,7 @@
.section ".text.head", "ax"
ENTRY(tegra_secondary_startup)
bl v7_invalidate_l1
check_cpu_part_num 0xc09, r8, r9
bleq v7_invalidate_l1
b secondary_startup
ENDPROC(tegra_secondary_startup)

7
arch/arm/mach-tegra/reset-handler.S
View File

@ -40,9 +40,11 @@
* re-enabling sdram.
*
* r6: SoC ID
* r8: CPU part number
*/
ENTRY(tegra_resume)
bl v7_invalidate_l1
check_cpu_part_num 0xc09, r8, r9
bleq v7_invalidate_l1
cpu_id r0
tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
@ -70,7 +72,8 @@ no_cpu0_chk:
str r1, [r2]
1:
check_cpu_part_num 0xc09, r8, r9
mov32 r9, 0xc09
cmp r8, r9
bne not_ca9
#ifdef CONFIG_HAVE_ARM_SCU
/* enable SCU */