igc: Add HW initialization code
Add code for hardware initialization and reset Add code for semaphore handling Signed-off-by: Sasha Neftin <sasha.neftin@intel.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Sasha Neftin
Jeff Kirsher
parent
0507ef8a03
commit
c0071c7aa5
@ -7,4 +7,4 @@
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obj-$(CONFIG_IGC) += igc.o
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igc-objs := igc_main.o igc_mac.o igc_base.o
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igc-objs := igc_main.o igc_mac.o igc_i225.o igc_base.o
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@ -5,6 +5,184 @@
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#include "igc_hw.h"
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#include "igc_i225.h"
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#include "igc_mac.h"
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#include "igc_base.h"
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#include "igc.h"
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/**
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* igc_set_pcie_completion_timeout - set pci-e completion timeout
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* @hw: pointer to the HW structure
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*/
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static s32 igc_set_pcie_completion_timeout(struct igc_hw *hw)
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{
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u32 gcr = rd32(IGC_GCR);
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u16 pcie_devctl2;
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s32 ret_val = 0;
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/* only take action if timeout value is defaulted to 0 */
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if (gcr & IGC_GCR_CMPL_TMOUT_MASK)
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goto out;
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/* if capabilities version is type 1 we can write the
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* timeout of 10ms to 200ms through the GCR register
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*/
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if (!(gcr & IGC_GCR_CAP_VER2)) {
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gcr |= IGC_GCR_CMPL_TMOUT_10ms;
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goto out;
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}
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/* for version 2 capabilities we need to write the config space
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* directly in order to set the completion timeout value for
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* 16ms to 55ms
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*/
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ret_val = igc_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
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&pcie_devctl2);
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if (ret_val)
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goto out;
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pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
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ret_val = igc_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
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&pcie_devctl2);
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out:
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/* disable completion timeout resend */
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gcr &= ~IGC_GCR_CMPL_TMOUT_RESEND;
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wr32(IGC_GCR, gcr);
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return ret_val;
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}
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/**
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* igc_reset_hw_base - Reset hardware
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* @hw: pointer to the HW structure
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*
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* This resets the hardware into a known state. This is a
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* function pointer entry point called by the api module.
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*/
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static s32 igc_reset_hw_base(struct igc_hw *hw)
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{
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s32 ret_val;
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u32 ctrl;
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/* Prevent the PCI-E bus from sticking if there is no TLP connection
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* on the last TLP read/write transaction when MAC is reset.
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*/
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ret_val = igc_disable_pcie_master(hw);
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if (ret_val)
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hw_dbg("PCI-E Master disable polling has failed.\n");
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/* set the completion timeout for interface */
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ret_val = igc_set_pcie_completion_timeout(hw);
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if (ret_val)
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hw_dbg("PCI-E Set completion timeout has failed.\n");
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hw_dbg("Masking off all interrupts\n");
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wr32(IGC_IMC, 0xffffffff);
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wr32(IGC_RCTL, 0);
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wr32(IGC_TCTL, IGC_TCTL_PSP);
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wrfl();
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usleep_range(10000, 20000);
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ctrl = rd32(IGC_CTRL);
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hw_dbg("Issuing a global reset to MAC\n");
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wr32(IGC_CTRL, ctrl | IGC_CTRL_RST);
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ret_val = igc_get_auto_rd_done(hw);
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if (ret_val) {
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/* When auto config read does not complete, do not
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* return with an error. This can happen in situations
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* where there is no eeprom and prevents getting link.
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*/
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hw_dbg("Auto Read Done did not complete\n");
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}
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/* Clear any pending interrupt events. */
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wr32(IGC_IMC, 0xffffffff);
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rd32(IGC_ICR);
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return ret_val;
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}
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/**
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* igc_init_mac_params_base - Init MAC func ptrs.
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* @hw: pointer to the HW structure
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*/
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static s32 igc_init_mac_params_base(struct igc_hw *hw)
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{
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struct igc_mac_info *mac = &hw->mac;
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/* Set mta register count */
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mac->mta_reg_count = 128;
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mac->rar_entry_count = IGC_RAR_ENTRIES;
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/* reset */
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mac->ops.reset_hw = igc_reset_hw_base;
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mac->ops.acquire_swfw_sync = igc_acquire_swfw_sync_i225;
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mac->ops.release_swfw_sync = igc_release_swfw_sync_i225;
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return 0;
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}
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static s32 igc_get_invariants_base(struct igc_hw *hw)
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{
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u32 link_mode = 0;
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u32 ctrl_ext = 0;
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s32 ret_val = 0;
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ctrl_ext = rd32(IGC_CTRL_EXT);
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link_mode = ctrl_ext & IGC_CTRL_EXT_LINK_MODE_MASK;
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/* mac initialization and operations */
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ret_val = igc_init_mac_params_base(hw);
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if (ret_val)
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goto out;
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out:
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return ret_val;
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}
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/**
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* igc_init_hw_base - Initialize hardware
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* @hw: pointer to the HW structure
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*
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* This inits the hardware readying it for operation.
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*/
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static s32 igc_init_hw_base(struct igc_hw *hw)
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{
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struct igc_mac_info *mac = &hw->mac;
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u16 i, rar_count = mac->rar_entry_count;
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s32 ret_val = 0;
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/* Setup the receive address */
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igc_init_rx_addrs(hw, rar_count);
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/* Zero out the Multicast HASH table */
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hw_dbg("Zeroing the MTA\n");
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for (i = 0; i < mac->mta_reg_count; i++)
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array_wr32(IGC_MTA, i, 0);
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/* Zero out the Unicast HASH table */
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hw_dbg("Zeroing the UTA\n");
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for (i = 0; i < mac->uta_reg_count; i++)
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array_wr32(IGC_UTA, i, 0);
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/* Setup link and flow control */
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ret_val = igc_setup_link(hw);
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/* Clear all of the statistics registers (clear on read). It is
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* important that we do this after we have tried to establish link
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* because the symbol error count will increment wildly if there
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* is no link.
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*/
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igc_clear_hw_cntrs_base(hw);
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return ret_val;
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}
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/**
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* igc_rx_fifo_flush_base - Clean rx fifo after Rx enable
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@ -81,3 +259,12 @@ void igc_rx_fifo_flush_base(struct igc_hw *hw)
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rd32(IGC_RNBC);
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rd32(IGC_MPC);
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}
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static struct igc_mac_operations igc_mac_ops_base = {
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.init_hw = igc_init_hw_base,
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};
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const struct igc_info igc_base_info = {
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.get_invariants = igc_get_invariants_base,
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.mac_ops = &igc_mac_ops_base,
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};
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@ -33,6 +33,8 @@ union igc_adv_tx_desc {
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#define IGC_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
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#define IGC_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
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#define IGC_RAR_ENTRIES 16
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struct igc_adv_data_desc {
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__le64 buffer_addr; /* Address of the descriptor's data buffer */
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union {
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@ -10,6 +10,22 @@
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#define PCIE_DEVICE_CONTROL2 0x28
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#define PCIE_DEVICE_CONTROL2_16ms 0x0005
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/* Physical Func Reset Done Indication */
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#define IGC_CTRL_EXT_LINK_MODE_MASK 0x00C00000
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/* Number of 100 microseconds we wait for PCI Express master disable */
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#define MASTER_DISABLE_TIMEOUT 800
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/*Blocks new Master requests */
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#define IGC_CTRL_GIO_MASTER_DISABLE 0x00000004
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/* Status of Master requests. */
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#define IGC_STATUS_GIO_MASTER_ENABLE 0x00080000
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/* PCI Express Control */
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#define IGC_GCR_CMPL_TMOUT_MASK 0x0000F000
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#define IGC_GCR_CMPL_TMOUT_10ms 0x00001000
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#define IGC_GCR_CMPL_TMOUT_RESEND 0x00010000
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#define IGC_GCR_CAP_VER2 0x00040000
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/* Receive Address
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* Number of high/low register pairs in the RAR. The RAR (Receive Address
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* Registers) holds the directed and multicast addresses that we monitor.
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@ -28,10 +44,23 @@
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#define IGC_ERR_PARAM 4
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#define IGC_ERR_MAC_INIT 5
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#define IGC_ERR_RESET 9
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#define IGC_ERR_MASTER_REQUESTS_PENDING 10
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#define IGC_ERR_SWFW_SYNC 13
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/* Device Control */
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#define IGC_CTRL_RST 0x04000000 /* Global reset */
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/* PBA constants */
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#define IGC_PBA_34K 0x0022
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/* SW Semaphore Register */
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#define IGC_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
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#define IGC_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
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/* Number of milliseconds for NVM auto read done after MAC reset. */
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#define AUTO_READ_DONE_TIMEOUT 10
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#define IGC_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
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/* Device Status */
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#define IGC_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
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#define IGC_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
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@ -118,6 +147,13 @@
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#define IGC_CT_SHIFT 4
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#define IGC_COLLISION_THRESHOLD 15
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/* Flow Control Constants */
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#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
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#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
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#define FLOW_CONTROL_TYPE 0x8808
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/* Enable XON frame transmission */
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#define IGC_FCRTL_XONE 0x80000000
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/* Management Control */
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#define IGC_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
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@ -6,6 +6,8 @@
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#include <linux/types.h>
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#include <linux/if_ether.h>
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#include <linux/netdevice.h>
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#include "igc_regs.h"
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#include "igc_defines.h"
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#include "igc_mac.h"
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@ -17,6 +19,16 @@
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/* Function pointers for the MAC. */
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struct igc_mac_operations {
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s32 (*check_for_link)(struct igc_hw *hw);
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s32 (*reset_hw)(struct igc_hw *hw);
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s32 (*init_hw)(struct igc_hw *hw);
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s32 (*setup_physical_interface)(struct igc_hw *hw);
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void (*rar_set)(struct igc_hw *hw, u8 *address, u32 index);
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s32 (*read_mac_addr)(struct igc_hw *hw);
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s32 (*get_speed_and_duplex)(struct igc_hw *hw, u16 *speed,
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u16 *duplex);
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s32 (*acquire_swfw_sync)(struct igc_hw *hw, u16 mask);
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void (*release_swfw_sync)(struct igc_hw *hw, u16 mask);
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};
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enum igc_mac_type {
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@ -31,6 +43,19 @@ enum igc_phy_type {
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igc_phy_i225,
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};
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enum igc_nvm_type {
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igc_nvm_unknown = 0,
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igc_nvm_flash_hw,
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igc_nvm_invm,
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};
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struct igc_info {
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s32 (*get_invariants)(struct igc_hw *hw);
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struct igc_mac_operations *mac_ops;
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const struct igc_phy_operations *phy_ops;
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struct igc_nvm_operations *nvm_ops;
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};
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struct igc_mac_info {
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struct igc_mac_operations ops;
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@ -63,11 +88,61 @@ struct igc_mac_info {
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bool get_link_status;
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};
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struct igc_nvm_operations {
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s32 (*acquire)(struct igc_hw *hw);
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s32 (*read)(struct igc_hw *hw, u16 offset, u16 i, u16 *data);
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void (*release)(struct igc_hw *hw);
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s32 (*write)(struct igc_hw *hw, u16 offset, u16 i, u16 *data);
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s32 (*update)(struct igc_hw *hw);
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s32 (*validate)(struct igc_hw *hw);
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s32 (*valid_led_default)(struct igc_hw *hw, u16 *data);
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};
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struct igc_nvm_info {
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struct igc_nvm_operations ops;
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enum igc_nvm_type type;
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u32 flash_bank_size;
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u32 flash_base_addr;
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u16 word_size;
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u16 delay_usec;
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u16 address_bits;
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u16 opcode_bits;
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u16 page_size;
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};
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struct igc_bus_info {
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u16 func;
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u16 pci_cmd_word;
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};
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enum igc_fc_mode {
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igc_fc_none = 0,
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igc_fc_rx_pause,
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igc_fc_tx_pause,
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igc_fc_full,
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igc_fc_default = 0xFF
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};
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struct igc_fc_info {
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u32 high_water; /* Flow control high-water mark */
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u32 low_water; /* Flow control low-water mark */
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u16 pause_time; /* Flow control pause timer */
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bool send_xon; /* Flow control send XON */
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bool strict_ieee; /* Strict IEEE mode */
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enum igc_fc_mode current_mode; /* Type of flow control */
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enum igc_fc_mode requested_mode;
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};
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struct igc_dev_spec_base {
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bool global_device_reset;
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bool eee_disable;
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bool clear_semaphore_once;
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bool module_plugged;
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u8 media_port;
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};
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struct igc_hw {
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void *back;
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@ -75,9 +150,15 @@ struct igc_hw {
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unsigned long io_base;
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struct igc_mac_info mac;
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struct igc_fc_info fc;
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struct igc_nvm_info nvm;
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struct igc_bus_info bus;
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union {
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struct igc_dev_spec_base _base;
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} dev_spec;
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u16 device_id;
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u16 subsystem_vendor_id;
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u16 subsystem_device_id;
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@ -170,6 +251,10 @@ struct igc_hw_stats {
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u64 b2ogprc;
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};
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struct net_device *igc_get_hw_dev(struct igc_hw *hw);
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#define hw_dbg(format, arg...) \
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netdev_dbg(igc_get_hw_dev(hw), format, ##arg)
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s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
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s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
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void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
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141
drivers/net/ethernet/intel/igc/igc_i225.c
Normal file
141
drivers/net/ethernet/intel/igc/igc_i225.c
Normal file
@ -0,0 +1,141 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2018 Intel Corporation */
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#include <linux/delay.h>
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#include "igc_hw.h"
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/**
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* igc_get_hw_semaphore_i225 - Acquire hardware semaphore
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* @hw: pointer to the HW structure
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*
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* Acquire the HW semaphore to access the PHY or NVM
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*/
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static s32 igc_get_hw_semaphore_i225(struct igc_hw *hw)
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{
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s32 timeout = hw->nvm.word_size + 1;
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s32 i = 0;
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u32 swsm;
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/* Get the SW semaphore */
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while (i < timeout) {
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swsm = rd32(IGC_SWSM);
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if (!(swsm & IGC_SWSM_SMBI))
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break;
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usleep_range(500, 600);
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i++;
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}
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if (i == timeout) {
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/* In rare circumstances, the SW semaphore may already be held
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* unintentionally. Clear the semaphore once before giving up.
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*/
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if (hw->dev_spec._base.clear_semaphore_once) {
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hw->dev_spec._base.clear_semaphore_once = false;
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igc_put_hw_semaphore(hw);
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for (i = 0; i < timeout; i++) {
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swsm = rd32(IGC_SWSM);
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if (!(swsm & IGC_SWSM_SMBI))
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break;
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usleep_range(500, 600);
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}
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}
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/* If we do not have the semaphore here, we have to give up. */
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if (i == timeout) {
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hw_dbg("Driver can't access device - SMBI bit is set.\n");
|
||||
return -IGC_ERR_NVM;
|
||||
}
|
||||
}
|
||||
|
||||
/* Get the FW semaphore. */
|
||||
for (i = 0; i < timeout; i++) {
|
||||
swsm = rd32(IGC_SWSM);
|
||||
wr32(IGC_SWSM, swsm | IGC_SWSM_SWESMBI);
|
||||
|
||||
/* Semaphore acquired if bit latched */
|
||||
if (rd32(IGC_SWSM) & IGC_SWSM_SWESMBI)
|
||||
break;
|
||||
|
||||
usleep_range(500, 600);
|
||||
}
|
||||
|
||||
if (i == timeout) {
|
||||
/* Release semaphores */
|
||||
igc_put_hw_semaphore(hw);
|
||||
hw_dbg("Driver can't access the NVM\n");
|
||||
return -IGC_ERR_NVM;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* igc_acquire_swfw_sync_i225 - Acquire SW/FW semaphore
|
||||
* @hw: pointer to the HW structure
|
||||
* @mask: specifies which semaphore to acquire
|
||||
*
|
||||
* Acquire the SW/FW semaphore to access the PHY or NVM. The mask
|
||||
* will also specify which port we're acquiring the lock for.
|
||||
*/
|
||||
s32 igc_acquire_swfw_sync_i225(struct igc_hw *hw, u16 mask)
|
||||
{
|
||||
s32 i = 0, timeout = 200;
|
||||
u32 fwmask = mask << 16;
|
||||
u32 swmask = mask;
|
||||
s32 ret_val = 0;
|
||||
u32 swfw_sync;
|
||||
|
||||
while (i < timeout) {
|
||||
if (igc_get_hw_semaphore_i225(hw)) {
|
||||
ret_val = -IGC_ERR_SWFW_SYNC;
|
||||
goto out;
|
||||
}
|
||||
|
||||
swfw_sync = rd32(IGC_SW_FW_SYNC);
|
||||
if (!(swfw_sync & (fwmask | swmask)))
|
||||
break;
|
||||
|
||||
/* Firmware currently using resource (fwmask) */
|
||||
igc_put_hw_semaphore(hw);
|
||||
mdelay(5);
|
||||
i++;
|
||||
}
|
||||
|
||||
if (i == timeout) {
|
||||
hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
|
||||
ret_val = -IGC_ERR_SWFW_SYNC;
|
||||
goto out;
|
||||
}
|
||||
|
||||
swfw_sync |= swmask;
|
||||
wr32(IGC_SW_FW_SYNC, swfw_sync);
|
||||
|
||||
igc_put_hw_semaphore(hw);
|
||||
out:
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* igc_release_swfw_sync_i225 - Release SW/FW semaphore
|
||||
* @hw: pointer to the HW structure
|
||||
* @mask: specifies which semaphore to acquire
|
||||
*
|
||||
* Release the SW/FW semaphore used to access the PHY or NVM. The mask
|
||||
* will also specify which port we're releasing the lock for.
|
||||
*/
|
||||
void igc_release_swfw_sync_i225(struct igc_hw *hw, u16 mask)
|
||||
{
|
||||
u32 swfw_sync;
|
||||
|
||||
while (igc_get_hw_semaphore_i225(hw))
|
||||
; /* Empty */
|
||||
|
||||
swfw_sync = rd32(IGC_SW_FW_SYNC);
|
||||
swfw_sync &= ~mask;
|
||||
wr32(IGC_SW_FW_SYNC, swfw_sync);
|
||||
|
||||
igc_put_hw_semaphore(hw);
|
||||
}
|
||||
@ -2,4 +2,319 @@
|
||||
/* Copyright (c) 2018 Intel Corporation */
|
||||
|
||||
#include <linux/pci.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include "igc_mac.h"
|
||||
#include "igc_hw.h"
|
||||
|
||||
/* forward declaration */
|
||||
static s32 igc_set_default_fc(struct igc_hw *hw);
|
||||
static s32 igc_set_fc_watermarks(struct igc_hw *hw);
|
||||
|
||||
/**
|
||||
* igc_disable_pcie_master - Disables PCI-express master access
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Returns 0 (0) if successful, else returns -10
|
||||
* (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
|
||||
* the master requests to be disabled.
|
||||
*
|
||||
* Disables PCI-Express master access and verifies there are no pending
|
||||
* requests.
|
||||
*/
|
||||
s32 igc_disable_pcie_master(struct igc_hw *hw)
|
||||
{
|
||||
s32 timeout = MASTER_DISABLE_TIMEOUT;
|
||||
s32 ret_val = 0;
|
||||
u32 ctrl;
|
||||
|
||||
ctrl = rd32(IGC_CTRL);
|
||||
ctrl |= IGC_CTRL_GIO_MASTER_DISABLE;
|
||||
wr32(IGC_CTRL, ctrl);
|
||||
|
||||
while (timeout) {
|
||||
if (!(rd32(IGC_STATUS) &
|
||||
IGC_STATUS_GIO_MASTER_ENABLE))
|
||||
break;
|
||||
usleep_range(2000, 3000);
|
||||
timeout--;
|
||||
}
|
||||
|
||||
if (!timeout) {
|
||||
hw_dbg("Master requests are pending.\n");
|
||||
ret_val = -IGC_ERR_MASTER_REQUESTS_PENDING;
|
||||
goto out;
|
||||
}
|
||||
|
||||
out:
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* igc_init_rx_addrs - Initialize receive addresses
|
||||
* @hw: pointer to the HW structure
|
||||
* @rar_count: receive address registers
|
||||
*
|
||||
* Setup the receive address registers by setting the base receive address
|
||||
* register to the devices MAC address and clearing all the other receive
|
||||
* address registers to 0.
|
||||
*/
|
||||
void igc_init_rx_addrs(struct igc_hw *hw, u16 rar_count)
|
||||
{
|
||||
u8 mac_addr[ETH_ALEN] = {0};
|
||||
u32 i;
|
||||
|
||||
/* Setup the receive address */
|
||||
hw_dbg("Programming MAC Address into RAR[0]\n");
|
||||
|
||||
hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
|
||||
|
||||
/* Zero out the other (rar_entry_count - 1) receive addresses */
|
||||
hw_dbg("Clearing RAR[1-%u]\n", rar_count - 1);
|
||||
for (i = 1; i < rar_count; i++)
|
||||
hw->mac.ops.rar_set(hw, mac_addr, i);
|
||||
}
|
||||
|
||||
/**
|
||||
* igc_setup_link - Setup flow control and link settings
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Determines which flow control settings to use, then configures flow
|
||||
* control. Calls the appropriate media-specific link configuration
|
||||
* function. Assuming the adapter has a valid link partner, a valid link
|
||||
* should be established. Assumes the hardware has previously been reset
|
||||
* and the transmitter and receiver are not enabled.
|
||||
*/
|
||||
s32 igc_setup_link(struct igc_hw *hw)
|
||||
{
|
||||
s32 ret_val = 0;
|
||||
|
||||
/* In the case of the phy reset being blocked, we already have a link.
|
||||
* We do not need to set it up again.
|
||||
*/
|
||||
|
||||
/* If requested flow control is set to default, set flow control
|
||||
* based on the EEPROM flow control settings.
|
||||
*/
|
||||
if (hw->fc.requested_mode == igc_fc_default) {
|
||||
ret_val = igc_set_default_fc(hw);
|
||||
if (ret_val)
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* We want to save off the original Flow Control configuration just
|
||||
* in case we get disconnected and then reconnected into a different
|
||||
* hub or switch with different Flow Control capabilities.
|
||||
*/
|
||||
hw->fc.current_mode = hw->fc.requested_mode;
|
||||
|
||||
hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
|
||||
|
||||
/* Call the necessary media_type subroutine to configure the link. */
|
||||
ret_val = hw->mac.ops.setup_physical_interface(hw);
|
||||
if (ret_val)
|
||||
goto out;
|
||||
|
||||
/* Initialize the flow control address, type, and PAUSE timer
|
||||
* registers to their default values. This is done even if flow
|
||||
* control is disabled, because it does not hurt anything to
|
||||
* initialize these registers.
|
||||
*/
|
||||
hw_dbg("Initializing the Flow Control address, type and timer regs\n");
|
||||
wr32(IGC_FCT, FLOW_CONTROL_TYPE);
|
||||
wr32(IGC_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
|
||||
wr32(IGC_FCAL, FLOW_CONTROL_ADDRESS_LOW);
|
||||
|
||||
wr32(IGC_FCTTV, hw->fc.pause_time);
|
||||
|
||||
ret_val = igc_set_fc_watermarks(hw);
|
||||
|
||||
out:
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* igc_set_default_fc - Set flow control default values
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Read the EEPROM for the default values for flow control and store the
|
||||
* values.
|
||||
*/
|
||||
static s32 igc_set_default_fc(struct igc_hw *hw)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* igc_set_fc_watermarks - Set flow control high/low watermarks
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Sets the flow control high/low threshold (watermark) registers. If
|
||||
* flow control XON frame transmission is enabled, then set XON frame
|
||||
* transmission as well.
|
||||
*/
|
||||
static s32 igc_set_fc_watermarks(struct igc_hw *hw)
|
||||
{
|
||||
u32 fcrtl = 0, fcrth = 0;
|
||||
|
||||
/* Set the flow control receive threshold registers. Normally,
|
||||
* these registers will be set to a default threshold that may be
|
||||
* adjusted later by the driver's runtime code. However, if the
|
||||
* ability to transmit pause frames is not enabled, then these
|
||||
* registers will be set to 0.
|
||||
*/
|
||||
if (hw->fc.current_mode & igc_fc_tx_pause) {
|
||||
/* We need to set up the Receive Threshold high and low water
|
||||
* marks as well as (optionally) enabling the transmission of
|
||||
* XON frames.
|
||||
*/
|
||||
fcrtl = hw->fc.low_water;
|
||||
if (hw->fc.send_xon)
|
||||
fcrtl |= IGC_FCRTL_XONE;
|
||||
|
||||
fcrth = hw->fc.high_water;
|
||||
}
|
||||
wr32(IGC_FCRTL, fcrtl);
|
||||
wr32(IGC_FCRTH, fcrth);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* igc_clear_hw_cntrs_base - Clear base hardware counters
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Clears the base hardware counters by reading the counter registers.
|
||||
*/
|
||||
void igc_clear_hw_cntrs_base(struct igc_hw *hw)
|
||||
{
|
||||
rd32(IGC_CRCERRS);
|
||||
rd32(IGC_SYMERRS);
|
||||
rd32(IGC_MPC);
|
||||
rd32(IGC_SCC);
|
||||
rd32(IGC_ECOL);
|
||||
rd32(IGC_MCC);
|
||||
rd32(IGC_LATECOL);
|
||||
rd32(IGC_COLC);
|
||||
rd32(IGC_DC);
|
||||
rd32(IGC_SEC);
|
||||
rd32(IGC_RLEC);
|
||||
rd32(IGC_XONRXC);
|
||||
rd32(IGC_XONTXC);
|
||||
rd32(IGC_XOFFRXC);
|
||||
rd32(IGC_XOFFTXC);
|
||||
rd32(IGC_FCRUC);
|
||||
rd32(IGC_GPRC);
|
||||
rd32(IGC_BPRC);
|
||||
rd32(IGC_MPRC);
|
||||
rd32(IGC_GPTC);
|
||||
rd32(IGC_GORCL);
|
||||
rd32(IGC_GORCH);
|
||||
rd32(IGC_GOTCL);
|
||||
rd32(IGC_GOTCH);
|
||||
rd32(IGC_RNBC);
|
||||
rd32(IGC_RUC);
|
||||
rd32(IGC_RFC);
|
||||
rd32(IGC_ROC);
|
||||
rd32(IGC_RJC);
|
||||
rd32(IGC_TORL);
|
||||
rd32(IGC_TORH);
|
||||
rd32(IGC_TOTL);
|
||||
rd32(IGC_TOTH);
|
||||
rd32(IGC_TPR);
|
||||
rd32(IGC_TPT);
|
||||
rd32(IGC_MPTC);
|
||||
rd32(IGC_BPTC);
|
||||
|
||||
rd32(IGC_PRC64);
|
||||
rd32(IGC_PRC127);
|
||||
rd32(IGC_PRC255);
|
||||
rd32(IGC_PRC511);
|
||||
rd32(IGC_PRC1023);
|
||||
rd32(IGC_PRC1522);
|
||||
rd32(IGC_PTC64);
|
||||
rd32(IGC_PTC127);
|
||||
rd32(IGC_PTC255);
|
||||
rd32(IGC_PTC511);
|
||||
rd32(IGC_PTC1023);
|
||||
rd32(IGC_PTC1522);
|
||||
|
||||
rd32(IGC_ALGNERRC);
|
||||
rd32(IGC_RXERRC);
|
||||
rd32(IGC_TNCRS);
|
||||
rd32(IGC_CEXTERR);
|
||||
rd32(IGC_TSCTC);
|
||||
rd32(IGC_TSCTFC);
|
||||
|
||||
rd32(IGC_MGTPRC);
|
||||
rd32(IGC_MGTPDC);
|
||||
rd32(IGC_MGTPTC);
|
||||
|
||||
rd32(IGC_IAC);
|
||||
rd32(IGC_ICRXOC);
|
||||
|
||||
rd32(IGC_ICRXPTC);
|
||||
rd32(IGC_ICRXATC);
|
||||
rd32(IGC_ICTXPTC);
|
||||
rd32(IGC_ICTXATC);
|
||||
rd32(IGC_ICTXQEC);
|
||||
rd32(IGC_ICTXQMTC);
|
||||
rd32(IGC_ICRXDMTC);
|
||||
|
||||
rd32(IGC_CBTMPC);
|
||||
rd32(IGC_HTDPMC);
|
||||
rd32(IGC_CBRMPC);
|
||||
rd32(IGC_RPTHC);
|
||||
rd32(IGC_HGPTC);
|
||||
rd32(IGC_HTCBDPC);
|
||||
rd32(IGC_HGORCL);
|
||||
rd32(IGC_HGORCH);
|
||||
rd32(IGC_HGOTCL);
|
||||
rd32(IGC_HGOTCH);
|
||||
rd32(IGC_LENERRS);
|
||||
}
|
||||
|
||||
/**
|
||||
* igc_get_auto_rd_done - Check for auto read completion
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Check EEPROM for Auto Read done bit.
|
||||
*/
|
||||
s32 igc_get_auto_rd_done(struct igc_hw *hw)
|
||||
{
|
||||
s32 ret_val = 0;
|
||||
s32 i = 0;
|
||||
|
||||
while (i < AUTO_READ_DONE_TIMEOUT) {
|
||||
if (rd32(IGC_EECD) & IGC_EECD_AUTO_RD)
|
||||
break;
|
||||
usleep_range(1000, 2000);
|
||||
i++;
|
||||
}
|
||||
|
||||
if (i == AUTO_READ_DONE_TIMEOUT) {
|
||||
hw_dbg("Auto read by HW from NVM has not completed.\n");
|
||||
ret_val = -IGC_ERR_RESET;
|
||||
goto out;
|
||||
}
|
||||
|
||||
out:
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* igc_put_hw_semaphore - Release hardware semaphore
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Release hardware semaphore used to access the PHY or NVM
|
||||
*/
|
||||
void igc_put_hw_semaphore(struct igc_hw *hw)
|
||||
{
|
||||
u32 swsm;
|
||||
|
||||
swsm = rd32(IGC_SWSM);
|
||||
|
||||
swsm &= ~(IGC_SWSM_SMBI | IGC_SWSM_SWESMBI);
|
||||
|
||||
wr32(IGC_SWSM, swsm);
|
||||
}
|
||||
|
||||
@ -4,8 +4,19 @@
|
||||
#ifndef _IGC_MAC_H_
|
||||
#define _IGC_MAC_H_
|
||||
|
||||
#include "igc_hw.h"
|
||||
#include "igc_defines.h"
|
||||
|
||||
#ifndef IGC_REMOVED
|
||||
#define IGC_REMOVED(a) (0)
|
||||
#endif /* IGC_REMOVED */
|
||||
|
||||
/* forward declaration */
|
||||
s32 igc_disable_pcie_master(struct igc_hw *hw);
|
||||
void igc_init_rx_addrs(struct igc_hw *hw, u16 rar_count);
|
||||
s32 igc_setup_link(struct igc_hw *hw);
|
||||
void igc_clear_hw_cntrs_base(struct igc_hw *hw);
|
||||
s32 igc_get_auto_rd_done(struct igc_hw *hw);
|
||||
void igc_put_hw_semaphore(struct igc_hw *hw);
|
||||
|
||||
#endif
|
||||
|
||||
@ -64,6 +64,14 @@ enum latency_range {
|
||||
|
||||
static void igc_reset(struct igc_adapter *adapter)
|
||||
{
|
||||
struct pci_dev *pdev = adapter->pdev;
|
||||
struct igc_hw *hw = &adapter->hw;
|
||||
|
||||
hw->mac.ops.reset_hw(hw);
|
||||
|
||||
if (hw->mac.ops.init_hw(hw))
|
||||
dev_err(&pdev->dev, "Hardware Error\n");
|
||||
|
||||
if (!netif_running(adapter->netdev))
|
||||
igc_power_down_link(adapter);
|
||||
}
|
||||
@ -3555,6 +3563,19 @@ static int igc_sw_init(struct igc_adapter *adapter)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* igc_get_hw_dev - return device
|
||||
* @hw: pointer to hardware structure
|
||||
*
|
||||
* used by hardware layer to print debugging information
|
||||
*/
|
||||
struct net_device *igc_get_hw_dev(struct igc_hw *hw)
|
||||
{
|
||||
struct igc_adapter *adapter = hw->back;
|
||||
|
||||
return adapter->netdev;
|
||||
}
|
||||
|
||||
/**
|
||||
* igc_init_module - Driver Registration Routine
|
||||
*
|
||||
|
||||
@ -7,6 +7,7 @@
|
||||
/* General Register Descriptions */
|
||||
#define IGC_CTRL 0x00000 /* Device Control - RW */
|
||||
#define IGC_STATUS 0x00008 /* Device Status - RO */
|
||||
#define IGC_EECD 0x00010 /* EEPROM/Flash Control - RW */
|
||||
#define IGC_CTRL_EXT 0x00018 /* Extended Device Control - RW */
|
||||
#define IGC_MDIC 0x00020 /* MDI Control - RW */
|
||||
#define IGC_MDICNFG 0x00E04 /* MDC/MDIO Configuration - RW */
|
||||
@ -56,6 +57,23 @@
|
||||
#define IGC_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
|
||||
#define IGC_GPIE 0x01514 /* General Purpose Intr Enable - RW */
|
||||
|
||||
/* Interrupt Cause */
|
||||
#define IGC_ICRXPTC 0x04104 /* Rx Packet Timer Expire Count */
|
||||
#define IGC_ICRXATC 0x04108 /* Rx Absolute Timer Expire Count */
|
||||
#define IGC_ICTXPTC 0x0410C /* Tx Packet Timer Expire Count */
|
||||
#define IGC_ICTXATC 0x04110 /* Tx Absolute Timer Expire Count */
|
||||
#define IGC_ICTXQEC 0x04118 /* Tx Queue Empty Count */
|
||||
#define IGC_ICTXQMTC 0x0411C /* Tx Queue Min Threshold Count */
|
||||
#define IGC_ICRXDMTC 0x04120 /* Rx Descriptor Min Threshold Count */
|
||||
#define IGC_ICRXOC 0x04124 /* Receiver Overrun Count */
|
||||
|
||||
#define IGC_CBTMPC 0x0402C /* Circuit Breaker TX Packet Count */
|
||||
#define IGC_HTDPMC 0x0403C /* Host Transmit Discarded Packets */
|
||||
#define IGC_CBRMPC 0x040FC /* Circuit Breaker RX Packet Count */
|
||||
#define IGC_RPTHC 0x04104 /* Rx Packets To Host */
|
||||
#define IGC_HGPTC 0x04118 /* Host Good Packets TX Count */
|
||||
#define IGC_HTCBDPC 0x04124 /* Host TX Circ.Breaker Drop Count */
|
||||
|
||||
/* MSI-X Table Register Descriptions */
|
||||
#define IGC_PBACL 0x05B68 /* MSIx PBA Clear - R/W 1 to clear */
|
||||
|
||||
@ -73,6 +91,8 @@
|
||||
#define IGC_RXCSUM 0x05000 /* Rx Checksum Control - RW */
|
||||
#define IGC_RLPML 0x05004 /* Rx Long Packet Max Length */
|
||||
#define IGC_RFCTL 0x05008 /* Receive Filter Control*/
|
||||
#define IGC_MTA 0x05200 /* Multicast Table Array - RW Array */
|
||||
#define IGC_UTA 0x0A000 /* Unicast Table Array - RW */
|
||||
#define IGC_RAL(_n) (0x05400 + ((_n) * 0x08))
|
||||
#define IGC_RAH(_n) (0x05404 + ((_n) * 0x08))
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user