drm/msm/adreno: split adreno device out into it's own file
We'd rather not duplicate these parts as support for additional gpu generations is added. Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rob Clark
parent
dac746e04e
commit
bfd28b1362
@ -4,6 +4,7 @@ ifeq (, $(findstring -W,$(EXTRA_CFLAGS)))
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endif
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msm-y := \
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adreno/adreno_device.o \
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adreno/adreno_gpu.o \
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adreno/a3xx_gpu.o \
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hdmi/hdmi.o \
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@ -549,158 +549,3 @@ fail:
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return ERR_PTR(ret);
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}
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/*
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* The a3xx device:
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*/
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#if defined(CONFIG_MSM_BUS_SCALING) && !defined(CONFIG_OF)
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# include <mach/kgsl.h>
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#endif
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static void set_gpu_pdev(struct drm_device *dev,
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struct platform_device *pdev)
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{
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struct msm_drm_private *priv = dev->dev_private;
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priv->gpu_pdev = pdev;
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}
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static int a3xx_bind(struct device *dev, struct device *master, void *data)
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{
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static struct adreno_platform_config config = {};
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#ifdef CONFIG_OF
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struct device_node *child, *node = dev->of_node;
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u32 val;
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int ret;
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ret = of_property_read_u32(node, "qcom,chipid", &val);
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if (ret) {
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dev_err(dev, "could not find chipid: %d\n", ret);
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return ret;
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}
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config.rev = ADRENO_REV((val >> 24) & 0xff,
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(val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff);
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/* find clock rates: */
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config.fast_rate = 0;
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config.slow_rate = ~0;
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for_each_child_of_node(node, child) {
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if (of_device_is_compatible(child, "qcom,gpu-pwrlevels")) {
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struct device_node *pwrlvl;
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for_each_child_of_node(child, pwrlvl) {
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ret = of_property_read_u32(pwrlvl, "qcom,gpu-freq", &val);
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if (ret) {
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dev_err(dev, "could not find gpu-freq: %d\n", ret);
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return ret;
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}
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config.fast_rate = max(config.fast_rate, val);
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config.slow_rate = min(config.slow_rate, val);
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}
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}
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}
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if (!config.fast_rate) {
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dev_err(dev, "could not find clk rates\n");
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return -ENXIO;
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}
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#else
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struct kgsl_device_platform_data *pdata = dev->platform_data;
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uint32_t version = socinfo_get_version();
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if (cpu_is_apq8064ab()) {
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config.fast_rate = 450000000;
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config.slow_rate = 27000000;
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config.bus_freq = 4;
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config.rev = ADRENO_REV(3, 2, 1, 0);
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} else if (cpu_is_apq8064()) {
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config.fast_rate = 400000000;
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config.slow_rate = 27000000;
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config.bus_freq = 4;
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if (SOCINFO_VERSION_MAJOR(version) == 2)
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config.rev = ADRENO_REV(3, 2, 0, 2);
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else if ((SOCINFO_VERSION_MAJOR(version) == 1) &&
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(SOCINFO_VERSION_MINOR(version) == 1))
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config.rev = ADRENO_REV(3, 2, 0, 1);
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else
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config.rev = ADRENO_REV(3, 2, 0, 0);
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} else if (cpu_is_msm8960ab()) {
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config.fast_rate = 400000000;
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config.slow_rate = 320000000;
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config.bus_freq = 4;
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if (SOCINFO_VERSION_MINOR(version) == 0)
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config.rev = ADRENO_REV(3, 2, 1, 0);
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else
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config.rev = ADRENO_REV(3, 2, 1, 1);
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} else if (cpu_is_msm8930()) {
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config.fast_rate = 400000000;
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config.slow_rate = 27000000;
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config.bus_freq = 3;
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if ((SOCINFO_VERSION_MAJOR(version) == 1) &&
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(SOCINFO_VERSION_MINOR(version) == 2))
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config.rev = ADRENO_REV(3, 0, 5, 2);
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else
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config.rev = ADRENO_REV(3, 0, 5, 0);
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}
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# ifdef CONFIG_MSM_BUS_SCALING
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config.bus_scale_table = pdata->bus_scale_table;
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# endif
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#endif
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dev->platform_data = &config;
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set_gpu_pdev(dev_get_drvdata(master), to_platform_device(dev));
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return 0;
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}
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static void a3xx_unbind(struct device *dev, struct device *master,
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void *data)
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{
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set_gpu_pdev(dev_get_drvdata(master), NULL);
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}
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static const struct component_ops a3xx_ops = {
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.bind = a3xx_bind,
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.unbind = a3xx_unbind,
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};
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static int a3xx_probe(struct platform_device *pdev)
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{
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return component_add(&pdev->dev, &a3xx_ops);
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}
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static int a3xx_remove(struct platform_device *pdev)
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{
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component_del(&pdev->dev, &a3xx_ops);
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return 0;
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}
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static const struct of_device_id dt_match[] = {
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{ .compatible = "qcom,adreno-3xx" },
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/* for backwards compat w/ downstream kgsl DT files: */
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{ .compatible = "qcom,kgsl-3d0" },
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{}
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};
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static struct platform_driver a3xx_driver = {
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.probe = a3xx_probe,
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.remove = a3xx_remove,
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.driver = {
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.name = "kgsl-3d0",
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.of_match_table = dt_match,
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},
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};
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void __init a3xx_register(void)
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{
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platform_driver_register(&a3xx_driver);
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}
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void __exit a3xx_unregister(void)
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{
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platform_driver_unregister(&a3xx_driver);
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}
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169
drivers/gpu/drm/msm/adreno/adreno_device.c
Normal file
169
drivers/gpu/drm/msm/adreno/adreno_device.c
Normal file
@ -0,0 +1,169 @@
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/*
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* Copyright (C) 2013-2014 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "adreno_gpu.h"
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#if defined(CONFIG_MSM_BUS_SCALING) && !defined(CONFIG_OF)
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# include <mach/kgsl.h>
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#endif
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static void set_gpu_pdev(struct drm_device *dev,
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struct platform_device *pdev)
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{
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struct msm_drm_private *priv = dev->dev_private;
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priv->gpu_pdev = pdev;
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}
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static int adreno_bind(struct device *dev, struct device *master, void *data)
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{
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static struct adreno_platform_config config = {};
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#ifdef CONFIG_OF
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struct device_node *child, *node = dev->of_node;
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u32 val;
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int ret;
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ret = of_property_read_u32(node, "qcom,chipid", &val);
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if (ret) {
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dev_err(dev, "could not find chipid: %d\n", ret);
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return ret;
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}
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config.rev = ADRENO_REV((val >> 24) & 0xff,
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(val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff);
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/* find clock rates: */
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config.fast_rate = 0;
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config.slow_rate = ~0;
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for_each_child_of_node(node, child) {
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if (of_device_is_compatible(child, "qcom,gpu-pwrlevels")) {
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struct device_node *pwrlvl;
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for_each_child_of_node(child, pwrlvl) {
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ret = of_property_read_u32(pwrlvl, "qcom,gpu-freq", &val);
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if (ret) {
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dev_err(dev, "could not find gpu-freq: %d\n", ret);
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return ret;
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}
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config.fast_rate = max(config.fast_rate, val);
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config.slow_rate = min(config.slow_rate, val);
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}
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}
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}
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if (!config.fast_rate) {
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dev_err(dev, "could not find clk rates\n");
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return -ENXIO;
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}
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#else
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struct kgsl_device_platform_data *pdata = dev->platform_data;
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uint32_t version = socinfo_get_version();
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if (cpu_is_apq8064ab()) {
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config.fast_rate = 450000000;
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config.slow_rate = 27000000;
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config.bus_freq = 4;
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config.rev = ADRENO_REV(3, 2, 1, 0);
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} else if (cpu_is_apq8064()) {
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config.fast_rate = 400000000;
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config.slow_rate = 27000000;
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config.bus_freq = 4;
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if (SOCINFO_VERSION_MAJOR(version) == 2)
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config.rev = ADRENO_REV(3, 2, 0, 2);
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else if ((SOCINFO_VERSION_MAJOR(version) == 1) &&
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(SOCINFO_VERSION_MINOR(version) == 1))
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config.rev = ADRENO_REV(3, 2, 0, 1);
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else
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config.rev = ADRENO_REV(3, 2, 0, 0);
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} else if (cpu_is_msm8960ab()) {
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config.fast_rate = 400000000;
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config.slow_rate = 320000000;
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config.bus_freq = 4;
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if (SOCINFO_VERSION_MINOR(version) == 0)
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config.rev = ADRENO_REV(3, 2, 1, 0);
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else
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config.rev = ADRENO_REV(3, 2, 1, 1);
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} else if (cpu_is_msm8930()) {
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config.fast_rate = 400000000;
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config.slow_rate = 27000000;
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config.bus_freq = 3;
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if ((SOCINFO_VERSION_MAJOR(version) == 1) &&
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(SOCINFO_VERSION_MINOR(version) == 2))
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config.rev = ADRENO_REV(3, 0, 5, 2);
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else
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config.rev = ADRENO_REV(3, 0, 5, 0);
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}
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# ifdef CONFIG_MSM_BUS_SCALING
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config.bus_scale_table = pdata->bus_scale_table;
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# endif
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#endif
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dev->platform_data = &config;
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set_gpu_pdev(dev_get_drvdata(master), to_platform_device(dev));
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return 0;
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}
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static void adreno_unbind(struct device *dev, struct device *master,
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void *data)
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{
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set_gpu_pdev(dev_get_drvdata(master), NULL);
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}
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static const struct component_ops a3xx_ops = {
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.bind = adreno_bind,
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.unbind = adreno_unbind,
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};
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static int adreno_probe(struct platform_device *pdev)
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{
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return component_add(&pdev->dev, &a3xx_ops);
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}
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static int adreno_remove(struct platform_device *pdev)
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{
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component_del(&pdev->dev, &a3xx_ops);
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return 0;
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}
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static const struct of_device_id dt_match[] = {
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{ .compatible = "qcom,adreno-3xx" },
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/* for backwards compat w/ downstream kgsl DT files: */
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{ .compatible = "qcom,kgsl-3d0" },
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{}
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};
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static struct platform_driver adreno_driver = {
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.probe = adreno_probe,
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.remove = adreno_remove,
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.driver = {
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.name = "adreno",
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.of_match_table = dt_match,
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},
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};
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void __init adreno_register(void)
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{
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platform_driver_register(&adreno_driver);
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}
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void __exit adreno_unregister(void)
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{
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platform_driver_unregister(&adreno_driver);
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}
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@ -1027,7 +1027,7 @@ static int __init msm_drm_register(void)
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{
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DBG("init");
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hdmi_register();
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a3xx_register();
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adreno_register();
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return platform_driver_register(&msm_platform_driver);
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}
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@ -1036,7 +1036,7 @@ static void __exit msm_drm_unregister(void)
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DBG("fini");
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platform_driver_unregister(&msm_platform_driver);
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hdmi_unregister();
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a3xx_unregister();
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adreno_unregister();
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}
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module_init(msm_drm_register);
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@ -167,7 +167,7 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
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void msm_gpu_cleanup(struct msm_gpu *gpu);
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struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
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void __init a3xx_register(void);
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void __exit a3xx_unregister(void);
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void __init adreno_register(void);
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void __exit adreno_unregister(void);
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#endif /* __MSM_GPU_H__ */
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