Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle:
"This is the main pull request for MIPS for Linux 4.1. Most
noteworthy:
- Add more Octeon-optimized crypto functions
- Octeon crypto preemption and locking fixes
- Little endian support for Octeon
- Use correct CSR to soft reset Octeons
- Support LEDs on the Octeon-based DSR-1000N
- Fix PCI interrupt mapping for the Octeon-based DSR-1000N
- Mark prom_free_prom_memory() as __init for a number of systems
- Support for Imagination's Pistachio SOC. This includes arch and
CLK bits. I'd like to merge pinctrl bits later
- Improve parallelism of csum_partial for certain pipelines
- Organize DTB files in subdirs like other architectures
- Implement read_sched_clock for all MIPS platforms other than
Octeon
- Massive series of 38 fixes and cleanups for the FPU emulator /
kernel
- Further FPU remulator work to support new features. This sits on a
separate branch which also has been pulled into the 4.1 KVM branch
- Clean up and fixes for the SEAD3 eval board; remove unused file
- Various updates for Netlogic platforms
- A number of small updates for Loongson 3 platforms
- Increase the memory limit for ATH79 platforms to 256MB
- A fair number of fixes and updates for BCM47xx platforms
- Finish the implementation of XPA support
- MIPS FDC support. No, not floppy controller but Fast Debug Channel :)
- Detect the R16000 used in SGI legacy platforms
- Fix Kconfig dependencies for the SSB bus support"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (265 commits)
MIPS: Makefile: Fix MIPS ASE detection code
MIPS: asm: elf: Set O32 default FPU flags
MIPS: BCM47XX: Fix detecting Microsoft MN-700 & Asus WL500G
MIPS: Kconfig: Disable SMP/CPS for 64-bit
MIPS: Hibernate: flush TLB entries earlier
MIPS: smp-cps: cpu_set FPU mask if FPU present
MIPS: lose_fpu(): Disable FPU when MSA enabled
MIPS: ralink: add missing symbol for RALINK_ILL_ACC
MIPS: ralink: Fix bad config symbol in PCI makefile.
SSB: fix Kconfig dependencies
MIPS: Malta: Detect and fix bad memsize values
Revert "MIPS: Avoid pipeline stalls on some MIPS32R2 cores."
MIPS: Octeon: Delete override of cpu_has_mips_r2_exec_hazard.
MIPS: Fix cpu_has_mips_r2_exec_hazard.
MIPS: kernel: entry.S: Set correct ISA level for mips_ihb
MIPS: asm: spinlock: Fix addiu instruction for R10000_LLSC_WAR case
MIPS: r4kcache: Use correct base register for MIPS R6 cache flushes
MIPS: Kconfig: Fix typo for the r2-to-r6 emulator kernel parameter
MIPS: unaligned: Fix regular load/store instruction emulation for EVA
MIPS: unaligned: Surround load/store macros in do {} while statements
...
This commit is contained in:
Linus Torvalds
123
Documentation/devicetree/bindings/clock/pistachio-clock.txt
Normal file
123
Documentation/devicetree/bindings/clock/pistachio-clock.txt
Normal file
@@ -0,0 +1,123 @@
|
||||
Imagination Technologies Pistachio SoC clock controllers
|
||||
========================================================
|
||||
|
||||
Pistachio has four clock controllers (core clock, peripheral clock, peripheral
|
||||
general control, and top general control) which are instantiated individually
|
||||
from the device-tree.
|
||||
|
||||
External clocks:
|
||||
----------------
|
||||
|
||||
There are three external inputs to the clock controllers which should be
|
||||
defined with the following clock-output-names:
|
||||
- "xtal": External 52Mhz oscillator (required)
|
||||
- "audio_clk_in": Alternate audio reference clock (optional)
|
||||
- "enet_clk_in": Alternate ethernet PHY clock (optional)
|
||||
|
||||
Core clock controller:
|
||||
----------------------
|
||||
|
||||
The core clock controller generates clocks for the CPU, RPU (WiFi + BT
|
||||
co-processor), audio, and several peripherals.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "img,pistachio-clk".
|
||||
- reg: Must contain the base address and length of the core clock controller.
|
||||
- #clock-cells: Must be 1. The single cell is the clock identifier.
|
||||
See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
|
||||
- clocks: Must contain an entry for each clock in clock-names.
|
||||
- clock-names: Must include "xtal" (see "External clocks") and
|
||||
"audio_clk_in_gate", "enet_clk_in_gate" which are generated by the
|
||||
top-level general control.
|
||||
|
||||
Example:
|
||||
clk_core: clock-controller@18144000 {
|
||||
compatible = "img,pistachio-clk";
|
||||
reg = <0x18144000 0x800>;
|
||||
clocks = <&xtal>, <&cr_top EXT_CLK_AUDIO_IN>,
|
||||
<&cr_top EXT_CLK_ENET_IN>;
|
||||
clock-names = "xtal", "audio_clk_in_gate", "enet_clk_in_gate";
|
||||
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Peripheral clock controller:
|
||||
----------------------------
|
||||
|
||||
The peripheral clock controller generates clocks for the DDR, ROM, and other
|
||||
peripherals. The peripheral system clock ("periph_sys") generated by the core
|
||||
clock controller is the input clock to the peripheral clock controller.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "img,pistachio-periph-clk".
|
||||
- reg: Must contain the base address and length of the peripheral clock
|
||||
controller.
|
||||
- #clock-cells: Must be 1. The single cell is the clock identifier.
|
||||
See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
|
||||
- clocks: Must contain an entry for each clock in clock-names.
|
||||
- clock-names: Must include "periph_sys", the peripheral system clock generated
|
||||
by the core clock controller.
|
||||
|
||||
Example:
|
||||
clk_periph: clock-controller@18144800 {
|
||||
compatible = "img,pistachio-clk-periph";
|
||||
reg = <0x18144800 0x800>;
|
||||
clocks = <&clk_core CLK_PERIPH_SYS>;
|
||||
clock-names = "periph_sys";
|
||||
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Peripheral general control:
|
||||
---------------------------
|
||||
|
||||
The peripheral general control block generates system interface clocks and
|
||||
resets for various peripherals. It also contains miscellaneous peripheral
|
||||
control registers. The system clock ("sys") generated by the peripheral clock
|
||||
controller is the input clock to the system clock controller.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must include "img,pistachio-periph-cr" and "syscon".
|
||||
- reg: Must contain the base address and length of the peripheral general
|
||||
control registers.
|
||||
- #clock-cells: Must be 1. The single cell is the clock identifier.
|
||||
See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
|
||||
- clocks: Must contain an entry for each clock in clock-names.
|
||||
- clock-names: Must include "sys", the system clock generated by the peripheral
|
||||
clock controller.
|
||||
|
||||
Example:
|
||||
cr_periph: syscon@18144800 {
|
||||
compatible = "img,pistachio-cr-periph", "syscon";
|
||||
reg = <0x18148000 0x1000>;
|
||||
clocks = <&clock_periph PERIPH_CLK_PERIPH_SYS>;
|
||||
clock-names = "sys";
|
||||
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Top-level general control:
|
||||
--------------------------
|
||||
|
||||
The top-level general control block contains miscellaneous control registers and
|
||||
gates for the external clocks "audio_clk_in" and "enet_clk_in".
|
||||
|
||||
Required properties:
|
||||
- compatible: Must include "img,pistachio-cr-top" and "syscon".
|
||||
- reg: Must contain the base address and length of the top-level
|
||||
control registers.
|
||||
- clocks: Must contain an entry for each clock in clock-names.
|
||||
- clock-names: Two optional clocks, "audio_clk_in" and "enet_clk_in" (see
|
||||
"External clocks").
|
||||
- #clock-cells: Must be 1. The single cell is the clock identifier.
|
||||
See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
|
||||
|
||||
Example:
|
||||
cr_top: syscon@18144800 {
|
||||
compatible = "img,pistachio-cr-top", "syscon";
|
||||
reg = <0x18149000 0x200>;
|
||||
clocks = <&audio_refclk>, <&ext_enet_in>;
|
||||
clock-names = "audio_clk_in", "enet_clk_in";
|
||||
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@@ -0,0 +1,41 @@
|
||||
Broadcom BCM3380-style Level 1 / Level 2 interrupt controller
|
||||
|
||||
This interrupt controller shows up in various forms on many BCM338x/BCM63xx
|
||||
chipsets. It has the following properties:
|
||||
|
||||
- outputs a single interrupt signal to its interrupt controller parent
|
||||
|
||||
- contains one or more enable/status word pairs, which often appear at
|
||||
different offsets in different blocks
|
||||
|
||||
- no atomic set/clear operations
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: should be "brcm,bcm3380-l2-intc"
|
||||
- reg: specifies one or more enable/status pairs, in the following format:
|
||||
<enable_reg 0x4 status_reg 0x4>...
|
||||
- interrupt-controller: identifies the node as an interrupt controller
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
|
||||
source, should be 1.
|
||||
- interrupt-parent: specifies the phandle to the parent interrupt controller
|
||||
this one is cascaded from
|
||||
- interrupts: specifies the interrupt line in the interrupt-parent controller
|
||||
node, valid values depend on the type of parent interrupt controller
|
||||
|
||||
Optional properties:
|
||||
|
||||
- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
|
||||
wakeup source for system suspend/resume.
|
||||
|
||||
Example:
|
||||
|
||||
irq0_intc: interrupt-controller@10000020 {
|
||||
compatible = "brcm,bcm3380-l2-intc";
|
||||
reg = <0x10000024 0x4 0x1000002c 0x4>,
|
||||
<0x10000020 0x4 0x10000028 0x4>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
interrupts = <2>;
|
||||
};
|
||||
@@ -0,0 +1,52 @@
|
||||
Broadcom BCM7038-style Level 1 interrupt controller
|
||||
|
||||
This block is a first level interrupt controller that is typically connected
|
||||
directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip
|
||||
since BCM7038 has contained this hardware.
|
||||
|
||||
Key elements of the hardware design include:
|
||||
|
||||
- 64, 96, 128, or 160 incoming level IRQ lines
|
||||
|
||||
- Most onchip peripherals are wired directly to an L1 input
|
||||
|
||||
- A separate instance of the register set for each CPU, allowing individual
|
||||
peripheral IRQs to be routed to any CPU
|
||||
|
||||
- Atomic mask/unmask operations
|
||||
|
||||
- No polarity/level/edge settings
|
||||
|
||||
- No FIFO or priority encoder logic; software is expected to read all
|
||||
2-5 status words to determine which IRQs are pending
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: should be "brcm,bcm7038-l1-intc"
|
||||
- reg: specifies the base physical address and size of the registers;
|
||||
the number of supported IRQs is inferred from the size argument
|
||||
- interrupt-controller: identifies the node as an interrupt controller
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
|
||||
source, should be 1.
|
||||
- interrupt-parent: specifies the phandle to the parent interrupt controller(s)
|
||||
this one is cascaded from
|
||||
- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
|
||||
node; valid values depend on the type of parent interrupt controller
|
||||
|
||||
If multiple reg ranges and interrupt-parent entries are present on an SMP
|
||||
system, the driver will allow IRQ SMP affinity to be set up through the
|
||||
/proc/irq/ interface. In the simplest possible configuration, only one
|
||||
reg range and one interrupt-parent is needed.
|
||||
|
||||
Example:
|
||||
|
||||
periph_intc: periph_intc@1041a400 {
|
||||
compatible = "brcm,bcm7038-l1-intc";
|
||||
reg = <0x1041a400 0x30 0x1041a600 0x30>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
interrupts = <2>, <3>;
|
||||
};
|
||||
@@ -13,8 +13,7 @@ Such an interrupt controller has the following hardware design:
|
||||
or if they will output an interrupt signal at this 2nd level interrupt
|
||||
controller, in particular for UARTs
|
||||
|
||||
- typically has one 32-bit enable word and one 32-bit status word, but on
|
||||
some hardware may have more than one enable/status pair
|
||||
- has one 32-bit enable word and one 32-bit status word
|
||||
|
||||
- no atomic set/clear operations
|
||||
|
||||
@@ -53,9 +52,7 @@ The typical hardware layout for this controller is represented below:
|
||||
Required properties:
|
||||
|
||||
- compatible: should be "brcm,bcm7120-l2-intc"
|
||||
- reg: specifies the base physical address and size of the registers;
|
||||
multiple pairs may be specified, with the first pair handling IRQ offsets
|
||||
0..31 and the second pair handling 32..63
|
||||
- reg: specifies the base physical address and size of the registers
|
||||
- interrupt-controller: identifies the node as an interrupt controller
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
|
||||
source, should be 1.
|
||||
@@ -66,10 +63,7 @@ Required properties:
|
||||
- brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts
|
||||
are wired to this 2nd level interrupt controller, and how they match their
|
||||
respective interrupt parents. Should match exactly the number of interrupts
|
||||
specified in the 'interrupts' property, multiplied by the number of
|
||||
enable/status register pairs implemented by this controller. For
|
||||
multiple parent IRQs with multiple enable/status words, this looks like:
|
||||
<irq0_w0 irq0_w1 irq1_w0 irq1_w1 ...>
|
||||
specified in the 'interrupts' property.
|
||||
|
||||
Optional properties:
|
||||
|
||||
|
||||
@@ -27,8 +27,13 @@ Optional properties:
|
||||
Required properties for timer sub-node:
|
||||
- compatible : Should be "mti,gic-timer".
|
||||
- interrupts : Interrupt for the GIC local timer.
|
||||
|
||||
Optional properties for timer sub-node:
|
||||
- clocks : GIC timer operating clock.
|
||||
- clock-frequency : Clock frequency at which the GIC timers operate.
|
||||
|
||||
Note that one of clocks or clock-frequency must be specified.
|
||||
|
||||
Example:
|
||||
|
||||
gic: interrupt-controller@1bdc0000 {
|
||||
|
||||
@@ -1,37 +0,0 @@
|
||||
* Interrupt Controller
|
||||
|
||||
Properties:
|
||||
- compatible: "brcm,bcm3384-intc"
|
||||
|
||||
Compatibility with BCM3384 and possibly other BCM33xx/BCM63xx SoCs.
|
||||
|
||||
- reg: Address/length pairs for each mask/status register set. Length must
|
||||
be 8. If multiple register sets are specified, the first set will
|
||||
handle IRQ offsets 0..31, the second set 32..63, and so on.
|
||||
|
||||
- interrupt-controller: This is an interrupt controller.
|
||||
|
||||
- #interrupt-cells: Must be <1>. Just a simple IRQ offset; no level/edge
|
||||
or polarity configuration is possible with this controller.
|
||||
|
||||
- interrupt-parent: This controller is cascaded from a MIPS CPU HW IRQ, or
|
||||
from another INTC.
|
||||
|
||||
- interrupts: The IRQ on the parent controller.
|
||||
|
||||
Example:
|
||||
periph_intc: periph_intc@14e00038 {
|
||||
compatible = "brcm,bcm3384-intc";
|
||||
|
||||
/*
|
||||
* IRQs 0..31: mask reg 0x14e00038, status reg 0x14e0003c
|
||||
* IRQs 32..63: mask reg 0x14e00340, status reg 0x14e00344
|
||||
*/
|
||||
reg = <0x14e00038 0x8 0x14e00340 0x8>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
interrupts = <4>;
|
||||
};
|
||||
@@ -1,11 +0,0 @@
|
||||
* Broadcom cable/DSL platforms
|
||||
|
||||
SoCs:
|
||||
|
||||
Required properties:
|
||||
- compatible: "brcm,bcm3384", "brcm,bcm33843"
|
||||
|
||||
Boards:
|
||||
|
||||
Required properties:
|
||||
- compatible: "brcm,bcm93384wvg"
|
||||
12
Documentation/devicetree/bindings/mips/brcm/soc.txt
Normal file
12
Documentation/devicetree/bindings/mips/brcm/soc.txt
Normal file
@@ -0,0 +1,12 @@
|
||||
* Broadcom cable/DSL/settop platforms
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: "brcm,bcm3384", "brcm,bcm33843"
|
||||
"brcm,bcm3384-viper", "brcm,bcm33843-viper"
|
||||
"brcm,bcm6328", "brcm,bcm6368",
|
||||
"brcm,bcm7125", "brcm,bcm7346", "brcm,bcm7358", "brcm,bcm7360",
|
||||
"brcm,bcm7362", "brcm,bcm7420", "brcm,bcm7425"
|
||||
|
||||
The experimental -viper variants are for running Linux on the 3384's
|
||||
BMIPS4355 cable modem CPU instead of the BMIPS5000 application processor.
|
||||
42
Documentation/devicetree/bindings/mips/img/pistachio.txt
Normal file
42
Documentation/devicetree/bindings/mips/img/pistachio.txt
Normal file
@@ -0,0 +1,42 @@
|
||||
Imagination Pistachio SoC
|
||||
=========================
|
||||
|
||||
Required properties:
|
||||
--------------------
|
||||
- compatible: Must include "img,pistachio".
|
||||
|
||||
CPU nodes:
|
||||
----------
|
||||
A "cpus" node is required. Required properties:
|
||||
- #address-cells: Must be 1.
|
||||
- #size-cells: Must be 0.
|
||||
A CPU sub-node is also required for at least CPU 0. Since the topology may
|
||||
be probed via CPS, it is not necessary to specify secondary CPUs. Required
|
||||
propertis:
|
||||
- device_type: Must be "cpu".
|
||||
- compatible: Must be "mti,interaptiv".
|
||||
- reg: CPU number.
|
||||
- clocks: Must include the CPU clock. See ../../clock/clock-bindings.txt for
|
||||
details on clock bindings.
|
||||
Example:
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "mti,interaptiv";
|
||||
reg = <0>;
|
||||
clocks = <&clk_core CLK_MIPS>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Boot protocol:
|
||||
--------------
|
||||
In accordance with the MIPS UHI specification[1], the bootloader must pass the
|
||||
following arguments to the kernel:
|
||||
- $a0: -2.
|
||||
- $a1: KSEG0 address of the flattened device-tree blob.
|
||||
|
||||
[1] http://prplfoundation.org/wiki/MIPS_documentation
|
||||
@@ -15,6 +15,7 @@ Table of Contents
|
||||
1) Entry point for arch/arm
|
||||
2) Entry point for arch/powerpc
|
||||
3) Entry point for arch/x86
|
||||
4) Entry point for arch/mips/bmips
|
||||
|
||||
II - The DT block format
|
||||
1) Header
|
||||
@@ -288,6 +289,33 @@ it with special cases.
|
||||
or initrd address. It simply holds information which can not be retrieved
|
||||
otherwise like interrupt routing or a list of devices behind an I2C bus.
|
||||
|
||||
4) Entry point for arch/mips/bmips
|
||||
----------------------------------
|
||||
|
||||
Some bootloaders only support a single entry point, at the start of the
|
||||
kernel image. Other bootloaders will jump to the ELF start address.
|
||||
Both schemes are supported; CONFIG_BOOT_RAW=y and CONFIG_NO_EXCEPT_FILL=y,
|
||||
so the first instruction immediately jumps to kernel_entry().
|
||||
|
||||
Similar to the arch/arm case (b), a DT-aware bootloader is expected to
|
||||
set up the following registers:
|
||||
|
||||
a0 : 0
|
||||
|
||||
a1 : 0xffffffff
|
||||
|
||||
a2 : Physical pointer to the device tree block (defined in chapter
|
||||
II) in RAM. The device tree can be located anywhere in the first
|
||||
512MB of the physical address space (0x00000000 - 0x1fffffff),
|
||||
aligned on a 64 bit boundary.
|
||||
|
||||
Legacy bootloaders do not use this convention, and they do not pass in a
|
||||
DT block. In this case, Linux will look for a builtin DTB, selected via
|
||||
CONFIG_DT_*.
|
||||
|
||||
This convention is defined for 32-bit systems only, as there are not
|
||||
currently any 64-bit BMIPS implementations.
|
||||
|
||||
II - The DT block format
|
||||
========================
|
||||
|
||||
|
||||
Reference in New Issue
Block a user